JPS599930B2 - Status setting key determination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state setting key determining device for an electronic desktop calculator, and more particularly to a state setting key determining device that sends a determination result to a calculation order generating circuit.

Generally, electronic desk calculators are equipped with keys for setting states such as constant calculation state, rounding off state, automatic memory calculation state, etc., and digits are used as key signals to determine whether or not these state setting keys are pressed. There are some that use a digit signal to indicate.

Conventionally, this type of status setting key determination device allocates sequentially generated digit signals as each key signal of each status setting key, and after matching with the corresponding digit signal, each of the corresponding digit signals is assigned. Each state is determined by setting the flip-flop.

In this state setting key determination device, since a flip-flop is provided for each state setting key, it is possible to inform the calculation order generation circuit that all the state setting keys are in a pressed state. However, since the status setting key determination device having the above-mentioned configuration uses one flip-flop for each status setting key, the more the number of status setting keys increases, the more flip-flops are used for the determination. need to be increased.

An object of the present invention is to provide a status setting key determination device that does not require an increase in the number of flip-flops for making determinations corresponding to status setting keys.

In the present invention, in the calculation order generation circuit that receives the output from the state setting key determination device, we have focused on the fact that it is not necessary to simultaneously perform the determination of multiple state setting keys, A state setting key determining device with a simple configuration that can determine whether or not a setting key is pressed is obtained.

According to the present invention, when setting a plurality of states, a time order signal corresponding to each individual state setting is input as a state setting key signal from one input terminal, and the state is determined from this state setting key signal. A state setting key determining device includes means for generating a time order signal corresponding to a state to be determined at each time when a state is to be determined, and a time order signal generated by the means and input from the state setting key. There is obtained a state setting key determination device characterized in that the present invention comprises only one means for detecting coincidence with a time order signal, and both means determine a plurality of states. This will be explained below with reference to the drawings.

FIG. 1 is a diagram showing a time chart of basic signals in the state setting key determination device.

As shown in FIG. 1, signals T1 to TlO are generated sequentially.
are digit signals each indicating a digit, and here the case of 10 digits is shown. Therefore, as the number of digits increases, the digit signal also naturally increases. FIG. 2 is a block diagram for explaining a conventional status setting key determination device, and FIG. 3 shows its time chart.

First, referring to Fig. 2, in this example, the status setting keys include a constant calculation status setting key (K key), a rounding person status setting key (4/5 key), and an automatic memory calculation status setting key (Σ key). ) is provided. In addition, the digit signal T2 is added to the constant calculation state setting key as a key signal.
is assigned, a digit signal T3 is assigned as a key signal to the rounding person status setting key, and a digit signal T4 is assigned as a key signal to the automatic memory calculation status setting key. Here, referring also to FIG. 3, since there is a digit signal T2 in the status setting key in period 1, AND gate 1 has a logical value of "1" in digit time T2, but other AND gates 3, 5 is a logical value of 101 over period 1. Therefore, only flip-flop (hereinafter abbreviated as F/F) 2 is set at digit time T2. Since this F/F2 is reset by the digit signal T1, the F/F2 is reset by the digit signal T1.
The Q output of F2 has a logical value of 111 at the digit time TlO of period 1.
It shows. Therefore, the output of the AND gate 7 becomes the logical value r'l at the digit time TlO of period 1, and it is determined that the constant calculation state is in progress. Similarly, it is determined that the period is in the rounding off state and that the period is in the automatic memory calculation state. In this way, only the constant calculation setting key is pressed in period 1, the rounding calculation setting key in period, and the automatic memory calculation setting key in period, but all three status setting keys are pressed in period 1. Indicates a pressed state. In this case, since F/Fs 2, 4, and 6 are all set, the logic value 1F1f is sent from AND gates 7, 8, and 9 to the calculation order generation circuit at digit time TlO.
I is sent. However, since the calculation order generation circuit does not need to execute the judgment of the state setting keys at the same time, the calculation time is reduced by the outputs of all AND gates 7, 8, and 9 becoming the logical value "゜1" at the same time. There is little contribution to shortening the period.

In this way, in a status setting key determination device in which one F/F is provided for each status setting key, as the number of status setting keys increases, it is necessary to increase the F/F, and there is little benefit from increasing the number of F/Fs. .

FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is a timing chart showing waveforms of various parts thereof. Referring to FIG. 4, AND gates 20 and 40, F
/F3O, and a time order signal generation circuit 5 that generates a time order signal TJ according to the state to be determined when making a decision.
0. Here, if FIG. 5 is also referred to, in period a, the key signal digit time T2 indicating the constant calculation state
is applied to one end of the AND gate 20 as a state setting key signal.

On the other hand, when determining whether or not it is in the constant calculation state, the time order signal generating circuit 50 generates the signal TJ at the digit time T2.
As a result, the AND gate 20 at digit time T2 of period a
becomes a logical value 81f1, F/F3O is set, and reset at digit time T1 of period b. Therefore, the output of the AND gate 40 becomes the logical value ゜''14 at the digit time TlO of the period a, and it is determined that the constant calculation state is in effect, and the output is sent to the calculation order generation circuit. , when digit time T3 is generated as signal TJ, F/
F3O is not set. That is, when the digit signal T3 is generated in the key signal of the status setting key, it means that the rounding person status setting key is being pressed, but since F/F3O is not set, the rounding person status is not set. It is determined that the In period a, signal TJ is applied at digit time T3.
The state when this occurs is as shown by the broken line in period a in FIG. Further, in period b, it is determined whether the round-off state is set, and in period c, it is determined whether the automatic memory calculation state is set. Next, in the case of period d, the digit signals T,, T3,
T4 is generated, and the digit signal T2 is generated as the signal TJ.

Therefore, in this case, only whether or not it is in the constant calculation state is determined, but as mentioned above, the calculation order generation circuit does not need to simultaneously execute the determination of the state setting key, so this configuration is a reasonable configuration. As mentioned above,
According to the present invention, even if the number of status setting keys is increased, only one F
It is possible to determine the state set by /F, and a state setting key determination device with a simple configuration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a timing chart of basic signals, FIG. 2 is a diagram showing an example of a conventional state setting key determination circuit, FIG. 3 is a timing chart thereof, and FIG. 4 is a diagram showing an embodiment of the present invention. Figure 5 is the timing chart. Explanation of symbols, (Figure 4) 20, 40: AND gate, 3
0: Flip-flop, 50: Time sequential signal generation circuit.

Claims (1)

[Claims] 1 Allocate digit signals with different timings to multiple states to be set, introduce the signal whose state should be determined from one input terminal, and identify the timing of the signal to be determined. A state setting key determination device for determining a state setting key includes: a first circuit that takes the repetition period of the digit signal as a unit period and generates only one digit signal to a single output terminal for each unit period; a second circuit that detects timing coincidence between the digit signal generated from the output terminal of the digit signal and the signal to be determined introduced from the input terminal; a storage circuit that stores the output of the second circuit; A state setting key determination device comprising means for resetting the memory circuit at the start of each of the unit cycles, so that a plurality of different states can be determined by repeating the unit cycle a plurality of times.