JPS599939B2 - Data search - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data processing device that can efficiently execute programs written in a high-level language, and in particular, directly executes statements defined in the high-level C language with high performance using dedicated hardware. The present invention relates to a data processing device.

When processing data using an electronic computer, COBOL and FORT, which are said to be high-level languages close to natural languages, are recently used.
Programs are created using RAN and PL/1, etc., but the source program written in a high-level language is usually converted into a target program created using machine language instructions by a translation program called a compiler. ,It is running.

However, because there is a functional difference between statement statements, which correspond to high-level language instructions, and machine language instructions, one statement is converted into a sequence of multiple machine language instructions.
Since the conversion is performed serially, the target program after conversion is not necessarily processed with high performance. SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that is equipped with and executes machine language instructions that are close to the functions of high-level language statements so that old programs can be created efficiently.

Another object of the present invention is to provide a data processing device that can execute machine language instructions corresponding to high-level language statements with high performance using dedicated hardware.

Still another object of the present invention is to provide a data processing device that facilitates the construction of a compiler used as a translation program for converting a source program into a target program by providing machine language instructions corresponding to statements in a high-level language. There is a particular thing.

The data processing device of the present invention includes an instruction for specifying a plurality of branch destinations and data locations and branches to a branch destination corresponding to an integer value of the data, and a main memory that stores the instructions and the data. a program counter for storing the memory location of the instruction to be executed; a register for storing the instruction; a data register for storing the data; and a positive counter in which the data does not exceed the number of branch destinations. It is composed of a determination circuit that checks whether the data is an integer, an address creation circuit that creates a branch destination storage location corresponding to the positive integer indicated by the data, and a control circuit that controls the processing specified by the branch instruction. .

The statements executed in the present invention are provided in the various high-level languages mentioned above and are frequently used by users, such as GOT in COBOL.
C in ODEPENDINGONlFORTRAN
O! Targets VPUTEDGOTO and destination variable type GOTO in PL/1.

For example, one of the statements in the high-level office language COBOL is GOTOLlL2L3DEPENDIN.
GONP (This statement branches to Ll.L2 or L3, which indicates the branch destination position according to the value of P, if the variable P indicating the decimal number is a positive integer 1, 2, or 3,
(When variable P is negative or greater than 3, execute the next statement without branching) will be specifically explained.

In conventional data processing devices, the above COBOL statements are processed by a δ translation program called a compiler (
1) Check whether the variable P is not negative (2) Check whether the variable P is not greater than 3 (3) Check the variable P
(4) Extract the branch destination corresponding to the value of be done.

On the other hand, in the data processing device using the present invention, the process corresponding to the above statement is executed by simply executing four machine language instructions for executing the above statement using one CASE instruction. .

Next, the present invention will be explained in detail with reference to the drawings.

Figure 1 shows CAS, which is a branch instruction used in the present invention.
It is a figure showing the composition of E command. The instruction code 0PC in the CASE instruction is 8 bits long, the 16 bits long field A1 indicates the storage location of the 16 bits long data n, and the 8 bits long field N indicates the number of branch destinations. Field A2 points to a storage location where N branch targets, each 16 bits long, are stored.

Thus, the CASE instruction has a total length of 48 bits. The data n pointed to by field A1 of this CASE instruction is 16 bits long and is expressed in two's complement format, so
When the leftmost bit of field A1 has a binary value of 1, it indicates that data n is negative.

Further, field N of the instruction expresses the number of branch destinations in 8-bit binary format, and can be expressed as a decimal number from +0 to +255. Next, the role of the CASE command will be explained.

When the data n pointed to by the A1 field of the instruction is in the range of positive integers 1 to N, branch to the branch destination 1r1 corresponding to n, and when the data n is negative or larger than N, change the instruction order without branching. It will be kept as is. FIG. 2 is a block diagram showing one embodiment of the present invention.

The data processing device of the present invention shown in FIG. 2 includes a main memory 1 for storing instructions and data, a program counter 2 for storing the memory address of the next instruction to be executed, an instruction storage register 3, and a data register 4. , a judgment circuit 5 for determining whether the input data is a positive integer not exceeding N, and a storage address creation circuit 6 for the branch destination 1n corresponding to the positive integer indicated by the input data.
and instruction retrieval, instruction code determination and CASE
It is composed of a control circuit 7 that controls processing specified by instructions. The main memory 1 is constituted by an ordinary semiconductor memory, each word of stored data consists of 16 bits, and access to the data is performed by 16 bits of address information.

The program counter 2 consists of a regular 16-bit register and has an increment function so that instructions can be fetched continuously and a function to set the data fetched from the main memory 1 to itself. . The instruction register 3 consists of a regular 48-bit register and temporarily stores instructions retrieved from the main memory 1 according to the program counter 2. In the above-mentioned 48-bit CASE instruction, each field of the instruction is sequentially read out from the main memory 1 into the instruction register 3 in three 16-bit increments. Data register 4 is a normal register with a length of 16 bits, and the CASE instruction is A1.
Temporarily saves the data specified in the field.

The contents of this data register 4 are sent to a determination circuit 5 and an address creation circuit 6 in order to execute the CASE instruction. The determination circuit 5 has a structure 1 as shown in FIG. 3 in detail.
It consists of a 6-bit binary subtracter 51 and a NOR gate 52. In FIG. 3, a binary subtracter 51 is a binary subtracter for subtracting data n in the data register 4 from the N field 33 in the instruction register 3, and as a result of the operation, when data n>N, Binary value 1 due to signal 53
give. The NOR gate 52 is composed of a commercially available ordinary IC, and outputs the NOR logic result of the leftmost bit 55 in the data register 4 and the signal 53 as a signal 54.
Therefore, the signal 54 gives a binary value of 0 when data n>N or when n is negative, and gives a binary value of 1 when data n satisfies the condition 0 and n≦N. As shown in FIG. 4 in detail, the address generation circuit 6 consists of a 16-bit binary subtracter 61 for subtracting a binary value of 1 and a 16-bit binary adder 62. In FIG. 4, a binary subtracter 61 is a gate circuit that subtracts 1 from data n in the data register 4 of FIG. 2 and outputs the value n-1 as a signal 63. It can be configured as follows. Further, the binary adder 62 is a gate circuit that performs binary addition of the A2 field 34 of the instruction register 3 in FIG. 2 and the signal 63 giving the value n-1. Can be configured. The output 64 of the binary adder 62 corresponds to the value of data n among the N branch destinations (n
is in the range from 1 to N, so the storage location is n-1
gives the storage location in main memory 1 where the branch destination (indicated by ) is stored.

FIG. 5 is a diagram showing a detailed configuration of the control circuit 7, which is a typical D-type flip-flop (hereinafter abbreviated as DFF) 71-J.
MoV, AND gates 78-80, and NAND gate 8
1 and a decoder 82.
7l-JMoV is a flip-flop that controls the execution order, and a timing signal (not shown) is connected to the clock terminal (
(not shown), and the outputs of the flip-flops in the previous stage are respectively applied to data terminals (not shown) in the next stage.

For this reason, the DFF7l-JMoV sequentially enters the operating state, and thereby various control signals (described later) are sent to the DFF7l-JMoV.
Generated by 7l-JMoV. N1 gates 78-80 and NAND gate 81 can be directly configured with commercially available ICs,
Further, the decoder 82 can be easily configured by combining a NAND gate and an 8-input M1 gate. Next, a control procedure for executing the CASE instruction by the control circuit 7 shown in FIG. 5 will be explained with reference to FIGS. 2 to 5.

First, when the instruction execution start signal 83 is sent and the DFF 7l becomes operational, the instruction address signal 21 indicated by the program counter 2 in FIG. 2 is sent to the main memory 1, and fetching of instructions is started.

After a certain period of time after DFF7l becomes operational, DFF
7.2 becomes operational, the instructions read from the main memory 1 are set in the instruction storage register 3.

When the instruction is a CASE instruction, since it is 48 bits long, the instruction is fetched from the main memory 1 into the instruction register 3 in three parts under the control of the DFF 72 using the increment function of the program counter 2. When the instruction is set in the register 3 of FIG. 2 in this manner, the instruction code portion 0PC31 is sent to the decoder 82 of the control circuit 7 (FIG. 5). In this case, the instruction is CA
If it is an SE command, the output signal 84 of the decoder 82 becomes valid, and the DFF 73 becomes operational through the AND gate 78. This DFF73 is the A1 field 32 of the instruction.
is sent to the main memory 1, and a read start signal for data n is generated. After a certain period of time, when the DFF 74 becomes operational, data n read from the main memory 1 is transferred to the data register 4.
A signal is generated from the DFF 74 to set the . When data n is set in the data register 4, this data value n and the N field in the instruction register 3 are determined by the judgment circuit 5.
When the data n is in the range of positive integers 1 to N, the binary signal 54 is set to a logic value 1 by the logic circuit 5.
When data n is negative or greater than N, it becomes a logical value 0. As a result, if the range determination signal 54 of data n has a logical value of 1, the M1 gate 79 in FIG. 5 is activated, and the DFF 75
becomes operational. On the other hand, if the logical value is 0, NAN
The logic value is inverted through the D gate 81, and the D1 gate 8
0 is activated, the DFF 77 becomes operational. D
When the FF 75 enters the operating state, the address creation circuit 6 of FIG.
The storage location of the branch destination address created by [A2+(n
-1)] is connected to the main memory 1 through the data path 64 in FIG.
is sent to start reading. As a result, when the DFF 76 becomes active after a certain period of time, the branch address read from the main memory I is set in the program counter 2, and the operation of the CASE instruction is completed. On the other hand, when the DFF 77 becomes operational, a value obtained by adding the binary value 1 to the program counter 2 is set in the program counter 2, and execution of the next instruction following the CASE instruction is continued.

The present invention has been described above in detail using Examples.

By using a data processing device using the present invention, statements allowed in a high-level language can be executed without converting them into multiple machine language instructions as in the past. This has the advantage that it can be performed using machine language instructions that correspond one-to-one to statements. Although the data n in the above embodiment represents an integer value, it may be a decimal number, for example. In this case, if the decimal number has a value below the decimal point, preprocessing such as truncation is performed. After this, the processing in the previous embodiment is performed.

Further, instead of data n, it may be data expressed by an arithmetic expression, and in this case, the A1 field of the CASE instruction will point to the data expressed by an arithmetic expression.
Further, although the branch destination in this embodiment is 16 bits long and directly indicates the main memory location, it may be a branch address that requires some kind of conversion (for example, a commonly used logical address). In addition, in this embodiment, when the data n is negative or larger than N, the next instruction is executed, but it is also possible to branch to an address specified from the outside.

[Brief explanation of the drawing]

Figure 1 shows CASE as a branch instruction used in the present invention.
2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a block diagram of the determination circuit of FIG. 2, and FIG. 4 is a block diagram of the address generation circuit of FIG. FIG. 5 is a configuration diagram of a control circuit that controls the CASE command. In Figure 2, reference numeral 1 is the main memory, reference numeral 2 is the program counter, reference numeral 3 is the instruction register, reference numeral 4 is the data register, reference numeral 5 is the judgment circuit, reference numeral 6 is the address creation circuit and reference. Number 7 represents a control circuit, respectively.

Claims (1)

[Claims] 1. A main memory including an instruction for specifying a plurality of branch destinations and the location of data and branching to a branch destination corresponding to an integer value of the data, and storing the instruction and the data, and the instruction to be executed. a program counter that stores the memory location of the instruction, a register that stores the instruction, a data register that stores the data, and a determination to determine whether the data is a positive integer that does not exceed the number of branch destinations. A data processing device comprising: a circuit; an address creation circuit that creates a branch destination storage location corresponding to a positive integer indicated by the data; and a control circuit that controls processing specified by the branch instruction. .