JPS6010506B2 - Malfunction prevention circuit for inverse converter - Google Patents
Malfunction prevention circuit for inverse converterInfo
- Publication number
- JPS6010506B2 JPS6010506B2 JP52084707A JP8470777A JPS6010506B2 JP S6010506 B2 JPS6010506 B2 JP S6010506B2 JP 52084707 A JP52084707 A JP 52084707A JP 8470777 A JP8470777 A JP 8470777A JP S6010506 B2 JPS6010506 B2 JP S6010506B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- converter
- circuit
- inverse converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007257 malfunction Effects 0.000 title claims description 5
- 230000002265 prevention Effects 0.000 title claims description 5
- 238000006243 chemical reaction Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 235000003642 hunger Nutrition 0.000 description 1
- 230000037351 starvation Effects 0.000 description 1
Landscapes
- Ac-Ac Conversion (AREA)
- Inverter Devices (AREA)
Description
【発明の詳細な説明】 本発明は逆変換装置の誤動作防止回路に関する。[Detailed description of the invention] The present invention relates to a malfunction prevention circuit for an inverse conversion device.
第１図はｍ項変換装置１を図示しない位相制御装置によ
り制御してその制御出力で逆変換装置２を運転する場合
の概略的な構成図である。FIG. 1 is a schematic configuration diagram when the m-term conversion device 1 is controlled by a phase control device (not shown) and the inverse conversion device 2 is operated by the control output thereof.
３は直流リアクトルで、この直流ＩＪァクトル３は順変
換装置１を位相制御した際、その直流出力が第２図ａに
示すように断続的になったときでも電流は第２図ｂに示
すように零にならないようにするためのものである。Reference numeral 3 denotes a DC reactor, and when the DC IJ reactor 3 controls the phase of the forward converter 1, even when its DC output becomes intermittent as shown in Figure 2a, the current remains as shown in Figure 2b. This is to prevent it from becoming zero.
４は負荷となるタンク回路である。4 is a tank circuit serving as a load.
上記第１図に示したように逆変換装置２は日頃変換装置
１の直流電圧がある程度まで断続しても直流リアクトル
３により電流が多少流れるため、運転に支障はない。し
かし、第２図ｂに示す電流の最小値が普通ｑ点以下とな
るような直流電圧になるまで位相制御すると逆変換装置
２は動作が停止してしまい負荷に電力を供給し得なくな
ってしまう欠点がある。逆変換装置２の動作が停止して
しまうと再度起動するには負荷等の関係から容易にでき
ないので、上記のような動作停止を避ける必要がある。
本発明は上記の事情に鑑みてなされたもので、逆変換装
置が直流電流の断続により動作停止しないようにした逆
変換装置の誤動作防止回路を提供することを目的とする
。As shown in FIG. 1 above, even if the DC voltage of the converter 1 is interrupted to a certain extent on a daily basis, the inverse converter 2 does not have any trouble in operation because a certain amount of current flows through the DC reactor 3. However, if the phase is controlled until the DC voltage becomes such that the minimum value of the current shown in Fig. 2b is normally below the q point, the inverter 2 will stop operating and will not be able to supply power to the load. There are drawbacks. Once the operation of the inverse conversion device 2 has stopped, it is not easy to start it again due to the load, etc., so it is necessary to avoid the above-mentioned operation stoppage.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a malfunction prevention circuit for an inverse converter that prevents the inverter from stopping its operation due to interruptions in direct current.
以下、図面を参照して本発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第３図において、１１‘ま第１電圧設定器、１２は第１
図に示す逆変換装置２とタンク回路４との間の負荷電圧
を検出する電圧検出器である。In Fig. 3, 11' is the first voltage setting device, and 12 is the first voltage setting device.
This is a voltage detector that detects the load voltage between the inverter 2 and the tank circuit 4 shown in the figure.
１３は第１比較回路で、この第１比較回路１３には前記
設定器１ １と検出器１２の出力が与えられる。Reference numeral 13 denotes a first comparison circuit, to which the outputs of the setter 11 and the detector 12 are applied.
１４は第１増幅回路、１５は順変換装置１を位相制御す
るための信号発生回路である。14 is a first amplifier circuit, and 15 is a signal generation circuit for controlling the phase of forward conversion device 1.
１６は前記信号発生回路１５の出力によ飢項変換装置１
へ位相制御信号を与えるゲート回路である。16 is a starvation term conversion device 1 based on the output of the signal generation circuit 15.
This is a gate circuit that provides a phase control signal to.
１７は第１図に示す逆変換装置２とタンク回路４との間
に流れる負荷電流を検出する電流検出器で、この検出器
１７で検出された電流は電流−電圧変換回路１８により
電圧に変換されて第２比較回路１９のプラス端子に与え
られる。Reference numeral 17 denotes a current detector that detects the load current flowing between the inverter 2 and the tank circuit 4 shown in FIG. and is applied to the positive terminal of the second comparison circuit 19.
この第２比較回路１９のマイナス端子には第２電圧設定
器２０の出力が与えられる。２１は第２増幅回路で、こ
の第２増幅回路２１は前記比較回路１９の両端子に与え
られる出力の偏差によりブラス、マイナスの出力を得る
。The output of the second voltage setter 20 is applied to the negative terminal of the second comparison circuit 19. Reference numeral 21 denotes a second amplifier circuit, and this second amplifier circuit 21 obtains a positive or negative output based on the deviation of the outputs applied to both terminals of the comparator circuit 19.
すなわち、比較回路１９のプラス端子の出力がマイナス
端子の出力より小さくなると増幅回路２１の出力はダイ
オード２２を介して第１比較回路１３に与えられる。次
に上記実施例の動作を述べる。That is, when the output of the positive terminal of the comparison circuit 19 becomes smaller than the output of the negative terminal, the output of the amplifier circuit 21 is applied to the first comparison circuit 13 via the diode 22. Next, the operation of the above embodiment will be described.
いま、順変換装置１の直流電流が断続的になると、逆変
換装置２の負荷電流は小さくなる。この電流は検出器１
７で検出されて、電流−電圧変換回路１８により電圧に
変換される。この変換電圧は検出電流が小さいので、電
圧値も低くなり、第２電圧設定器２０の電圧よりも低く
なってしまう。すると前述したように第２比較回路１９
の偏差値を増幅する第２増幅回路２１の出力はプラスに
なる。このプラス出力はダイオード２２を介して第１比
較回路１３のプラス端子に与えられる。すると、このプ
ラス出力により第１比較回路１３の偏差出力は所定の値
に制限されてしまうため、第１増幅回路１４の出力も所
定の増幅値になる。従って、位相制御信号発生回路１５
は常に一定の制御信号で、すなわち、順変換装置１の直
流電流が断続しない程度の位相制御となる信号で制御さ
れる。この結果、逆変換装置２は定電流設定で動作する
ようになり、負荷の軽重や第１設定電圧の電圧の高低に
関係なく、逆変換装置２は停止することなく運転が断続
される。ここで、タンク回路４すなわち負荷電流が増大
すると電流−電圧変換回路１８の出力は第２電圧設定器
２０の電圧よりも高くなる。このため、第２増幅回路２
１の出力はマイナスになり、ダイオード２２の作用によ
り第２増幅回路２１の出力は第１比較回路１３のプラス
端子に与えられなくなる。すると、電圧検出器１２の出
力と第１電圧設定器１１の出力とによる偏差出力により
」順変換装置１は制御されて逆変換装置２に電力が与え
られて運転される。以上述べたように本発明によれば、
逆変換装置の負荷出力電流を電圧に変換して予め設定し
た電圧と比較し、設定電圧の方が前記電圧より低くなっ
たとき、順変換装置の位相制御の動作を厭変換装置の直
流電流が断続しない程度の位相制御となる信号で制御し
て、逆変換装置の動作停止の防止を図りもって逆変換装
置の再起動の問題を生じないようにさせる逆変換装置の
誤動作防止回路が得られる。Now, when the direct current of the forward converter 1 becomes intermittent, the load current of the inverse converter 2 becomes smaller. This current is
7 and converted into a voltage by a current-voltage conversion circuit 18. Since the detected current of this converted voltage is small, the voltage value is also low and becomes lower than the voltage of the second voltage setting device 20. Then, as mentioned above, the second comparison circuit 19
The output of the second amplifying circuit 21 that amplifies the deviation value becomes positive. This positive output is given to the positive terminal of the first comparison circuit 13 via the diode 22. Then, because of this positive output, the deviation output of the first comparator circuit 13 is limited to a predetermined value, so that the output of the first amplifier circuit 14 also becomes a predetermined amplified value. Therefore, the phase control signal generation circuit 15
is always controlled by a constant control signal, that is, by a signal that provides phase control to the extent that the DC current of the forward converter 1 is not interrupted. As a result, the inverse converter 2 comes to operate with a constant current setting, and the inverse converter 2 continues to operate intermittently without stopping, regardless of the weight of the load or the level of the first set voltage. Here, when the tank circuit 4, that is, the load current increases, the output of the current-voltage conversion circuit 18 becomes higher than the voltage of the second voltage setting device 20. Therefore, the second amplifier circuit 2
1 becomes negative, and the output of the second amplifier circuit 21 is no longer given to the positive terminal of the first comparator circuit 13 due to the action of the diode 22. Then, the forward converter 1 is controlled by the deviation output between the output of the voltage detector 12 and the output of the first voltage setter 11, and power is supplied to the inverse converter 2 to operate it. As described above, according to the present invention,
The load output current of the inverse converter is converted into voltage and compared with a preset voltage, and when the set voltage is lower than the voltage, the phase control operation of the forward converter is changed and the direct current of the converter is changed. It is possible to obtain a malfunction prevention circuit for an inverse converter that performs control using a signal that provides non-intermittent phase control to prevent the inverse converter from stopping its operation, thereby preventing the problem of restarting the inverse converter.
第１図は順変換装置の制御出力で運転される逆変換装置
の概略的な構成図、第２図は従来例の作用を述べたため
の順変換装置の出力電圧および出力電流の波形図、第３
図は本発明の一実施例を示すブロック図である。
１・・・・・・順変換装置、２・・・・・・逆変換装置
、１ １，２０・…・・第１、第２電圧設定器、１２・
・・・・・電圧検出器「 １３，１９……第１、第２比
較回路、１４，２１・・・・・・第１、第２増幅回路、
１５・・・・・・位相制御信号発生回路、１６・・・・
・・ゲート回路、１７・・・・・・電流検出器、１８…
・・・電流−電圧変換回路、２２……ダイオード。
第１図
第２図
第３図Figure 1 is a schematic configuration diagram of an inverse converter operated by the control output of the forward converter, Figure 2 is a waveform diagram of the output voltage and output current of the forward converter to describe the operation of the conventional example, and Figure 2 is a waveform diagram of the output voltage and output current of the forward converter. 3
The figure is a block diagram showing one embodiment of the present invention. 1... Forward conversion device, 2... Inverse conversion device, 1 1, 20... First and second voltage setter, 12.
...Voltage detector "13, 19...First and second comparison circuits, 14,21...First and second amplifier circuits,
15... Phase control signal generation circuit, 16...
...Gate circuit, 17...Current detector, 18...
...Current-voltage conversion circuit, 22...Diode. Figure 1 Figure 2 Figure 3
Claims (1)
を比較し、その比較偏差値に応じて順変換装置を位相制
御して得られる順変換装置の制御出力により運転される
逆変換装置において、前記逆変換装置の負荷出力電流を
電圧に変換し、この変換電圧が予め設定された電圧より
低いとき前記順変換装置の位相制御を順変換装置の直流
電流が断続しない程度の位相制御となる信号で制御し、
その制御出力を逆変換装置に供給させるようにしたこと
を特徴とする逆変換装置の誤動作防止回路。1 In an inverse converter operated by the control output of a forward converter obtained by comparing the load output voltage of the inverter with a preset voltage and controlling the phase of the forward converter according to the comparison deviation value. , converts the load output current of the inverse converter into a voltage, and when this converted voltage is lower than a preset voltage, the phase control of the forward converter is controlled to such an extent that the direct current of the forward converter is not intermittent. Controlled by signals,
A malfunction prevention circuit for an inverse converter, characterized in that the control output is supplied to the inverse converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52084707A JPS6010506B2 (en) | 1977-07-14 | 1977-07-14 | Malfunction prevention circuit for inverse converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52084707A JPS6010506B2 (en) | 1977-07-14 | 1977-07-14 | Malfunction prevention circuit for inverse converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5419125A JPS5419125A (en) | 1979-02-13 |
| JPS6010506B2 true JPS6010506B2 (en) | 1985-03-18 |
Family
ID=13838124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52084707A Expired JPS6010506B2 (en) | 1977-07-14 | 1977-07-14 | Malfunction prevention circuit for inverse converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010506B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644375B2 (en) * | 1986-07-22 | 1994-06-08 | 株式会社日立製作所 | Digital signal recording / reproducing device |
-
1977
- 1977-07-14 JP JP52084707A patent/JPS6010506B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5419125A (en) | 1979-02-13 |
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