JPS6010517B2 - Step motor operation detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operation detection circuit for a step motor of an analog display type electronic timepiece.

Conventionally, a step motor of a commonly used analog display type quartz watch is constructed as shown in FIG.

A motor constituted by a stator 1, a rotor 2, and a coil 3 is engaged with a display mechanism such as a second hand, a minute hand, an hour hand, and in some cases a calendar through several wheel trains (not shown). The output generated by the motor is transmitted to the display mechanism via the wheel train, and conversely, the rotational torque generated in the display mechanism, particularly the second hand, is transmitted to the motor. Therefore, the movement of the second hand appears as the movement of the motor rotor. Conventionally, in analog display type quartz watches, external disturbances such as dropping may cause the second hand to err, which is known as hand skipping, resulting in poor time accuracy.

FIG. 2 shows the reverse induced current generated in the coil 3 due to the rotation of the rotor when a rotational force is applied to the second hand to cause the hand to shift. Figure 1 shows the reverse induced current when the second hand rotates clockwise.

2 is the reverse induced current when the second hand rotates counterclockwise and lags behind.

In FIG. 1, a back electromotive current 8 is a current waveform when the rotor shown in FIG. 1 rotates 180 degrees in the direction of arrow 4 from a stationary state and stops.

At this time, the magnetic poles of the rotor are stationary with N' and S swapped. The reverse induced current generated when the motor rotates 180 degrees in the direction of arrow 5 from this state and stops is 9. In the reverse induced current 8, the current waveform 8a is generated because when the rotor rotates in the direction of the arrow 4 and the magnetic pole N of the rotor passes near the narrow portion la of the stator 1, there is a large change in the magnetic flux that crosses the coil. Current waveform 8b is generated due to the change in the magnetic flux across the coil and the large rotational speed of the rotor when the magnetic pole N of the rotor rotates 180°. In the reverse induced current 9, the current waveform 9a is generated due to a large change in the magnetic east across the coil when the rotor rotates in the direction of the arrow 5 and the magnetic pole N of the rotor passes near the narrow portion lb of the stator 1. Current waveform 9
Similar to 8b, b occurs because the magnetic flux that crosses the coil changes when the rotor's magnetic pole N rotates by 180 degrees and the rotational speed of the rotor is large. In the reverse induced current 10, the current waveform 10a is generated because there is a large change in the magnetic flux that crosses the coil when the rotor 2 rotates in the direction of the arrow 6 and the magnetic pole N passes near the narrow portion lb of the stator. In the reverse induced current 11, the current waveform 11a is generated due to a large change in the magnetic flux that crosses the coil when the rotor 2 rotates in the direction of the arrow 7 and the magnetic pole N passes near the narrow part la of the stator. Current waveform 8a,
Waveforms 8b, 9a, 9b, 10a, and 10b are characterized in that their peak values are particularly large compared to other waveforms. When the second hand shifts clockwise by one second, the rotor rotates 1800 times as shown in FIG. 2, causing two large peak values in the current waveform. Conversely, when the second hand moves counterclockwise by one second, the rotor rotates 1800 times as shown in FIG. 2, producing one large peak value in the current waveform. Next, FIG. 3 shows a circuit for detecting the rotation of the rotor of a conventional analog quartz watch using reverse induced current.

In Figure 3, when the rotor rotates and a reverse induced current is generated in the coil 3 of the motor, this reverse induced current flows from ground to N
MOSFET29 Coil 3→N MOSFET30→
Resistor 32 → Ground loop and N MOSFET 29 →
Coil 3 → NMOSFET27 → NMOSFET2
Repeat the loop of 9 alternately, or ground → N M○SFET27 → Coil 3 → N M○SFET
ET31 → Resistor 32 → Ground loop and N MOSF
ET27→Coil 3→N M○SFET29→NMOS
The current flows through the FET 27 loop alternately. Since the voltage is input from the resistor 32 to the positive side of the comparator 37, a potential difference is generated between both ends of the resistor due to the reverse induced current generated in the coil 3, and the comparator 37 compares this potential difference. A reference potential for comparing potentials input to the comparator is determined by resistance division between resistors 34 and 35. When the potential input to the comparator becomes higher than the reference potential, the output To of the comparator becomes ``H'', and when the potential input to the comparator is lower than the reference voltage, the output To of the comparator becomes ``L''. When a reverse induced current as shown in Figures 1 and 2 in Figure 2 flows, current waveforms 8b, 9a, 1
0a is detected and the output of the comparator becomes "H", but 8a, 9b, and 11a are not detected and the output of the comparator is "L". Therefore, the subordinate detection circuit 43 could not detect rotation when the needle shifted counterclockwise. Further, although "H" was output to the comparator and rotation could be detected, it was not possible to determine whether the rotation was clockwise or counterclockwise. The present invention has been proposed in order to eliminate the above-mentioned drawbacks of the conventional technology, and includes an operation detection circuit for accurately detecting needle deviation due to external disturbances, etc., and correcting deviations in time accuracy caused by this needle deviation. This is what we provide.

The present invention will be explained in detail below.

FIG. 4 shows an example of the circuit configuration of an analog crystal clock used in the present invention. The oscillation signal of the oscillation circuit 38 is sequentially frequency-divided by a frequency dividing circuit 39. These frequency-divided signals are converted into reference signals for the control circuit 41, detection circuit 43, and drive circuit 42 by the waveform synthesis circuit 40. The control circuit 41 controls the motor 4 by the clockwise rotation detection signal T and the counterclockwise rotation detection signal T2 of the second hand of the detection circuit 43.
This circuit corrects the error in the second hand by rotating the second hand, and further corrects it by outputting a correction pulse if the motor does not rotate when the motor is rotated by the drive pulse. Drive circuit 4
Reference numeral 2 denotes a circuit that applies an inversion pulse to the coil of the step motor 44 to change the direction of current flow every second based on the output signal of the control circuit. The detection circuit 43 is a step motor 44
This circuit compares and counts the potential waveform T4 generated in the coil with a comparator to determine whether the second hand is incorrect or whether the rotor is rotating due to the drive pulse. FIG. 5 is an example of the detection circuit of the present invention. 13 is a flip-flop,
P of the waveform synthesizer 40 is connected to the clock input C.

The signal is input and the Q output is EX-OR gate 15
The Q output is input to the EX-OR gate 16. The T3 signal of the control circuit 41 is the EX-OR gate 1
5 and 16, and the output of EX-OR gate 15 is N.
The output of the EX-OR gate 16 is input to the NAND gate 19.
P of the waveform synthesizer, output is NAN via inverter 4
It is input to D gates 18 and 19. The output of the NAND gate 18 is input to the inverter 23 and the NAND gate 24, and the output of the inverter 23 is input to the P MOSFET 28.
has been entered. The output of the NAND gate 19 is input to an inverter 21 and a NAND gate 22, and the output of the inverter 21 is input to a PMOSFET 26. The output P3 of the waveform synthesizer is the NAND gate 22, NMOSF
It is input to ET3 0N, MOS FET3 1, NAND gate 24, and AND gate 46. The output of the NAND gate 22 is input to the N MOSFET 27,
The output of the AND gate 24 is input to the N MOBFET 29. Coil 3 has one end connected to PMOS FET2 6
, NMOS FET2 7, NMOSFET30, and the other end is PMOSFET2 8, NMOS
It is connected to FET29 and N MOSFET31.

Diodes 47, 48, 49, and 50 constitute a bridge-type full-wave rectifier circuit, one end of diode 48 is connected to diode 47 and N MOSFET 30, and the end is connected to comparator 37 and a set of SR-F-F45. Input S,
It is connected to diode 47. The diode 50 has one end connected to the diode 47 and the NMOSFET 31, and the other end connected to the resistor 51 and the diode 49.
Resistors 54 and 53 are connected to the positive side of the comparator 37, and one end of the resistor 53 is connected to an NMOSFET 52. The Q output of the SR-F-F 46 is input to an AND gate 46, and its output is input to the D terminal of an N MOSFET 52 and a D type flip-flop 56. The P4 output of the waveform synthesizer is input to the clock input of a D-type flip-flop, AND gate 58. The output of the comparator 37 is input to the D terminal of the D type flip-flop 55, the Q output of the D type flip-flop 56 is input to the clock input C, and the Q output is input to the clock of the binary counter 61. It is input to input C, AND gate 62, and set input S of SR-F-F57. Q of binary counter 61, output is AND gate 6
2, is input to the NOR gate 63, and the Q2 output is input to the AND gate 62. The Q output of the SR-F-F57 is input to an AND gate 58, and the Q output is input to a NOR gate 63. In the embodiment, the binary counter 59 is composed of five stages of flip-flops, and the output of the AND gate 58 is inputted to the clock input C. The Q, , Q2, Q3, Q4, and Q5 outputs of the binar + counter 59 are AND gate 60 and the Q,, Q2, Q3, and Q4 outputs are N.
It is input to AND gate 64. AND gate 60
The output is input to the reset inputs of SR-F-F45, 57 and the reset inputs of binary counters 59, 61. The output of the NAND gate 64 is input to the NOR gate 63. Next, circuit operation will be explained.

FIG. 6 shows a time chart of circuit operation.
When the P and output of the waveform synthesis circuit 40 becomes “L”, PM○S
FETs 26 and 28 are connected to “H” via inverters 21 and 23.
” is input, and both ends of the coil 3 are cut off to VD.
At this time, the P3 output is ``H'' and ``L'' as shown in Figure 6.
When repeating, when it is “H”, N MOSFET27
, 29 become conductive, both ends of the coil 3 are short-circuited, and "
When the voltage is "L", the NMOSFETs 30 and 31 are turned on and connected to the bridge type full-wave rectifier circuit.At this time, the rotor of the clock is rotated, and a reverse induced current as shown in L in Fig. 6 flows through the coil. 3, the reverse induced current is N MOS
By turning on and off the FETs 30 and 31, an intermittent reverse induced current is generated and input to the bridge type full-wave rectifier circuit. The intermittent reverse induced current is rectified by the bridge type full-wave rectifier circuit and becomes the signal a shown in FIG. When the a signal exceeds the threshold voltage of the set input S of SR-FF45, the SR-F
The output Q of F45 becomes “H”, and the N MOSFET52
is suitable. Comparator 37 is activated by conduction of N MOSFET 52. A reference voltage is set on the positive side of the comparator 37 by dividing the resistors 54 and 53, so when the a signal is input to the - side of the comparator, it is compared with the reference voltage and the b signal in Figure 6 is output from the comparator. becomes. Input D of D type flip-flop 56
When the P8 signal of the 102nd group 2 is inputted to the clock input C and the P4 signal of 4096Hz is inputted to the clock input C, the output Q is a signal of 102Hz Z whose phase is delayed by 0.12 seconds from the P3 signal. This signal is ○ type flip-flop 55
When inputting the clock input C to the clock input C and inputting the signal b to the input D, the output Q becomes the C signal shown in FIG. As is clear from this, by the comparator 37 and the D-type flip-flop 55, two pulses are generated when the rotor is rotating clockwise, and one pulse is output when the rotor is rotating counterclockwise. and constitutes a waveform shaping circuit. ○Type flip-flop 55 is 0.5ws
It functions to convert a signal that repeats "H" and "L" continuously at ec intervals into a continuous "H" signal. When the C signal becomes “H”, SR-FF57 is set and the output Q becomes “H”
Therefore, the clock signal of the P4 signal of 4096 Hz is inputted to the binary counter 59. In this embodiment, a five-stage binary counter 59 is used, which is determined by the back electromotive current waveform. In other words, the number of stages is determined so that the time from 8a to 8b appears in Figure 1 of Figure 2 is slightly longer than the time from ga to 9b. , a binary counter 59 is configured as a predetermined time counting circuit that starts operating in synchronization with the first pulse of the c signal. When the outputs of Q, Q2, Q, Q4, and Q5 of the binary counter 59 all become "H", the output of the AND gate 60 becomes "H", the SR-FF 45 is reset, and the comparator 37 and
The current flowing through the voltage dividing resistors 53 and 54 is cut off to reduce the increase in current consumption. Furthermore, the SR-FF 57 is reset and input of the clock signal to the binary counter 59 is prohibited. Also, the binary counter 59 is reset and the Q. , Q2, Q3, Q, all public outputs are set to "L". Furthermore, the binary counter 61 is reset and Q
, output to "H" and Q2 output to "L". NA
The ND gate 64 outputs the binary counter 59 Q, , Q2,
The output becomes "L" only when all Q and Q outputs become "H", and since the SR-FF 57 is set at that time, the "H" signal is input to the clock input C of the binary counter 61 only once. Then, Q becomes “L”,
At that time, the output L of the NOR gate becomes "H" for 0.12 seconds. T2 becomes "H" when the reverse induced current waveform is waveform 2 in FIG. 2, that is, when the rotor rotates in the reverse direction, T2 becomes "H". binary counter 61
If an “H” signal is input to the clock input of the Q
,,Q2 output becomes ``H'', and the output of AND gate 62 ``, becomes ``H'' for 0.5 seconds.T, becomes ``H''.
T becomes "H" when the reverse induced current waveform is waveform 1 in Figure 2, that is, when the rotor rotates forward, T becomes "H".
becomes. If "H" is not input to the clock input C of the binary counter 61 even once, its output Q is "H".
, Q2 is "L", so the output of the AND gate 62 is '
It is 'L'. In addition, the Q output of SR-FF57 is “H”
", since the output of the NAND gate 64 is "H", N
The output of OR gate 63 is "L". Therefore, T,,
No signal appears on the T2 output. Therefore, the binary counter 61 counts the number of pulses of the signal and detects the rotational direction of the rotor, and the binary counter 61 serves as a circuit for determining the rotor rotational direction. As described above, according to the present invention, when a needle trip occurs due to a disturbance such as a drop, it is possible to detect whether the needle trip occurs in a forward rotation or a reverse rotation. can be provided.

[Brief explanation of drawings]

Figure 2: Step motor plan view, Figure 2: Reverse induced current waveform, Figure 3: Conventional detection circuit diagram, Figure 4: Circuit block diagram of the present invention, Figure 5: Detection circuit diagram of the present invention. Figure 6:
3 is a time chart of waveforms of the detection circuit of the present invention. 1...Status ``2...Rota, 3...Koinore.

Claims (1)

[Claims] 1 Consisting of a permanent magnet rotor, a stator, and a coil, it has a drive circuit that rotates the rotor in steps by applying intermittent reversal pulses to the coil, and a control circuit that detects malfunction of the rotor and outputs a correction signal. In the step motor operation detection circuit, a first state in which the terminal of the coil is closed loop at least when the intermittent inversion pulse is not output, and a second state in which the terminal of the coil is connected to full-wave rectification means. and a switch means that alternately repeats the above, and shapes the output of the full-wave rectifier into a waveform so that when the rotor rotates in one direction, two pulses are generated and when the rotor rotates in the other direction, one pulse is generated. a waveform shaping circuit including a comparator, a predetermined time counting circuit that starts operating in synchronization with the first pulse of the waveform shaping circuit, and output from the waveform shaping circuit at a time set by the predetermined time counting circuit. 1. An operation detection circuit for a step motor, comprising a determination circuit that determines the rotational direction of the rotor according to the number of pulses.