JPS6011488B2 - digital tuning receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver that performs channel selection using digital settings.

The channel spacing for long wave (LF) and medium wave (MF) is currently 10 KHz in Japan, the United States, etc., and HZ in Europe, but the 10 KHz separation in Japan was established in 1973 by the Regional Administration Conference on Medium Wave Broadcasting. Since then, the rule has been KHb separation, and 1978 balls have been held.

In view of the above, the present invention provides a circuit that can easily change a 10 KHz separation digital channel selection receiver to a ratio separation one. The digital tuning receiver of the present invention includes a high-frequency stage of a superheterodyne receiver having a voltage variable capacitance element, a voltage generation circuit that outputs a control voltage to the voltage variable capacitance element, and a local oscillator of the high-frequency stage. A gate circuit that samples the output frequency for a certain period of time, a first n-ary counter that counts the output pulses of the gate circuit and generates an output, and an m-ary/n-ary switching signal that controls m-ary (where m<n). Activates when instructed, and the first
a reset circuit that generates a reset signal every time the count value of the counter reaches m to cause the first counter to operate in m-ary, and a memory dedicated to the start-up storing the m-ary/n-ary switching signal along with the channel number; , a second counter that counts the output pulses of the first counter, compares the output of the second counter with the channel number output of the memory, and controls the output of the voltage generation circuit until the two match. A comparator that generates a signal to be controlled will be described in detail below with reference to embodiments.

FIG. 1 shows an embodiment of the present invention, in which 1 is an antenna, 2 is a high-frequency stage including a high-frequency amplifier, a local oscillator, a mixer, etc.
3 is an intermediate frequency amplification and detection stage, 4 is a low frequency amplification stage, 5
are speakers, and these constitute a well-known superheterodyne radio receiver.

Also, 6 is a reference signal generator, 7 and 9 are NAND gates, 8 is an inverter, 10 is a voltage storage element, 1 1 is a 9-digit/IQ
Hayabusa counter, 15 is a 5x32 binary counter, 12 and 13 are read-only memories (ROM), 14 is a comparator, and 16
is a reception frequency indicator, and these constitute a digital tuning circuit. The reference signal generator 6 consists of an oscillator 20, a 1G ship counter 21 receiving the output of the oscillator, an inverter 22, and NAND gates 23 and 24, as shown in FIG. 1 skin S (positive pulse), gate signal Sg with period lowS, and NAND gate 24 has 1 S (negative pulse) in the pulse.
, leads the gate signal by 1mS and outputs a set signal with a period lowS.

Next, the operation of this device will be explained. For example, when the voltage storage element 10 is supplied with a constant positive input voltage, it generates an output voltage that increases linearly, and when the input voltage is cut off, it maintains the current output voltage for a long period of time, and generates a constant negative input voltage. Together they produce a linearly decreasing output voltage. The output voltage V of this voltage storage element is supplied to a high frequency amplification stage 2 that includes an element such as a variable capacitance diode that changes the capacitance value depending on the applied voltage. change. In this way, electronic channel selection is carried out,
When tuned to the broadcast radio wave, the intermediate frequency amplification and detection stage 3 produces an output, which causes the speaker 5 to sound via the low frequency amplification stage 4. During this tuning operation, the local oscillation frequency is selected to be 45 Hz higher for AM and 10,700 KHz lower for FM, so in the end, for AM, it is 525-455 to 1,605 kHz.
1459KHz, 7600-10700-90 on FM
Generates a frequency of 000-1070 Hz.

One input terminal of the NAND gate 7 is connected to the output terminal of the local oscillator, and receives the local oscillation frequency in the above range. Further, a gate signal Sg is input to the other input terminal of the NAND gate 7, and the gate is opened for a period of 1 S. Therefore, the output of the NAND gate 7 is 1'1000 of the frequency in the above range, and in the case of FM, since an IG Hayabusa counter is additionally provided (not shown), the output is 1/10000. That is, the frequency input to the counter 11, specifically the number of pulses, is A.
980-2060 for M, 6530-79 for FM
It will be 30. As described later, when the NAND gate 9 of the reset circuit is inactive, that is, when its output is always at a high level, the counter 11 becomes a 1G ship counter, and the NAND gate 9
When in operation, it becomes a 9-ary counter.

Assuming that the NAND gate is now inactive, the output frequency of the NAND gate 7 is divided by 1/10 by the counter 11 to become 98 to 200 for AM and 653 to 793 for FM, and these are added to the counter 15. These pulses 1
Since this corresponds to 10 KHb for AM and 100 KHz for FM, the counter 15 counts the channel number of each broadcast wave band. The counter 15 can be preset, and is preset so that all outputs become low level when counting the number of pulses 98, 653 corresponding to the lowest reception frequency in each broadcast wave band. Therefore, when the output Sa of the counter 15 is all low, it becomes the channel number 1 of the broadcast wave band, and thereafter, every time a pulse is counted, the channel number 2, 3, etc. shows. The number of channel numbers is 206-981 for AM =
109 FM, 793 - 653 + 1 = 141, so the output Sa of the counter 15 indicating the channel number is 8.
All you need is a bit. The memory 3 stores the desired channel number, that is, the broadcasting station, as an 8-bit binary code, and stores this signal Sb.
is output to the comparator 14.

It also outputs a signal Sc indicating whether AM reception or FM reception, and outputs this to the NAND gate 9 and memory 12. When the memory 12 receives this signal Sc, it inputs the above preset value into the counter 15. Note that the same effect can be obtained even if this presetting is performed on the counter 11. Comparator 14 receives signal Sa from counter 15 and memory 13
, and while the former is lower than the latter, the output S
Set d to positive polarity, and when both match -, set this output to 0,
Furthermore, if the former is higher than the latter, this world power becomes negative. As a result, the local oscillation frequency is changed via the voltage storage element 10 until the two match, and digital tuning is thus performed. The above is for the case of AMI female position and FMIO plate ratio separation, but the case of AM residence position and FM90K position separation is as follows.

First, to explain the operation of the 9.1G ship counter 11 with reference to the time chart in FIG.
Then, since the counter 11 consists of four stages of flip-flops, the outputs A, B, C, and D of the first, second, third, and fourth stages are as shown in FIG. 4, 2, 3, and 4.5. In other words, the output of each stage is the output of the previous stage divided by 1/2 in sequence, but in the state of the 1G ship counter with the NAND gate 9 closed, it is reset at the 9th pulse, returning to the initial state and counting. Start. In order to close the NAND gate 9, the signal Sc from the memory 13 can be set to low level. At this time, the output of the NAND gate 9 is always high level regardless of the other inputs, and the NAND gate 9 is not reset. Therefore, the counter 11 operates as an original 1-level gravity counter. On the other hand, when the signal Sc is set to the level /., the NAND gate 9 is opened, that is, the output is determined by the other input states. In this example, the other inputs of this NAND gate 9 are the output of the inverter 8, that is, the inverted signal of the local frequency pulse from the NAND gate 7, and the output A of the counter il.
, D, and when they are all high, the reset signal Se shown in FIG. 4 is output at the ninth pulse, and the counter 11 is reset. As a result, the counter 11 is 9
It becomes a forward counter, and each stage AOB. C. The output state of D is as shown in FIG. 4, 6, 7, 8, and 9. Thus memory 1
3 indicates AM reception or FM reception, and the counter 11 can be switched from 1 to 9 by simply outputting a low//-level signal Sc to the NAND gate 9, and the signal Sc is It can also be used to read out the memory 12 and preset the counters 11 and 15.

Of course, this presetting must be performed before counting starts, so the reference signal generator 6 advances the gate signal Sg by 1 S and outputs a set signal Sr to the counter 1 or 15 to reset and preset the counter. let The channel selection memory 13 is a known type of ROM assembled in the form of a rotary switch.

Normally, the number of broadcast stations is limited to a maximum of 1, so this switch has 10/touches from 0 to 9, and the radio receiver turns the knob to select that one notch and select the desired station. The channel selection is performed by outputting an 8-bit binary number indicating the channel number. Furthermore, since the channel numbers of broadcasting stations are generally relatively far apart, the output of the counter 15, ie, the upper five bits of the channel number, is input to the display 16, thereby displaying the station. If there are 5 bits,
Stations with 3 to 5 channel intervals and 32 pupils can be displayed, which is usually sufficient.

Although AM and FM, that is, medium and short waves, have been described above, the present invention can be similarly applied to long waves used in Europe and the like.

As explained in detail above, according to the present invention, 10KHz
The digital channel selection receiver of the separation can be easily switched to that of the shoe Hz separation, and there is no need for dedicated receivers for each, resulting in great benefits in manufacturing, use, maintenance, etc. In the above embodiment, a voltage storage element is used as the voltage generation circuit for the variable reactance element, but the present invention is not limited to this, and for example, a well-known sawtooth wave generator may be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams and circuit diagrams for explaining the operation of the reference signal generator, and FIG. 4 is for explaining the counter's 9-ary and IG Hayabusa switching. FIG. In the drawing, 2 is a high frequency stage, 10 is a voltage storage element, 7 is a gate circuit, 8 and 9 are reset circuits, 11 is a first counter,
15 is a second counter, 13 is a memory, and 14 is a comparator. Figure 1 Figure 2 Figure 3 Bottle '1 Figure

Claims (1)

[Claims] 1. A high-frequency stage of a superheterodyne receiver having a voltage variable capacitance element, a voltage generation circuit that outputs a control voltage to the voltage variable capacitance element, and a local oscillator output frequency of the high-frequency stage for one hour. A gate circuit for sampling and an n-ary first circuit for counting the output pulses of the gate circuit and producing an output.
counter, and the m-ary/n-ary switching signal is m-ary (however, m<n
), the reset circuit operates when an instruction is given to the first counter and generates a reset signal every time the count value of the first counter reaches m to cause the first counter to operate in the m-base; and the m-base/n-base switching signal. A read-only memory that stores the channel number along with a channel number, a second counter that counts the output pulses of the first counter, and a comparison between the output of the second counter and the channel number output of the memory, and a comparison between the two. a comparator that generates a signal that controls the output of the voltage generating circuit until they match. 2. The digital channel selection receiver according to claim 1, wherein the sampling time of the gate circuit is 1 mS, and the first counter is a 9-decimal switching counter. 3. Claims 1 or 2, characterized in that the second counter is a preset counter, and is set to a predetermined number in advance so that the initial value is the first channel number of the broadcast band. Digital tuning receiver as described.