JPS6011814B2 - thyristor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to thyristors, and more particularly to thyristors having improved operating characteristics.

Recently, thyristors have been increasingly used as switches for discharge paths for charged charges.

Figure 1 is a circuit diagram showing an example of this. In the figure, 1 is a DC power supply, 2 is a capacitor, 3 is a charging resistor, 4 is a load,
5 is a thyristor. The capacitor 2 is charged by the DC power source 1 via the charging resistor 3, and after the charging voltage reaches a predetermined value Vo, the thyristor 5 is turned on and the charged charge is discharged through the load 4.
Figure 2 shows this thyristor 5 when the load 4 is resistive.
In the waveform diagram of the discharge current IC flowing through the thyristor 5, the rise rate of the current (called di/dt) at the start of conduction of the thyristor 5 is extremely high, usually reaching several hundred to several hundred A/s. It is.

Therefore, the thyristor used in this circuit is required to have characteristics that can withstand this large di/dt. On the other hand, this type of charging/discharging circuit is often required to perform charging/discharging repeatedly within a short period of time.

In this case, the minimum repetition cycle that can be achieved is the time after the start of discharge until the main discharge current decreases exponentially, becomes less than the holding current IH of the thyristor, and the thyristor is finally cut off. Therefore, in order to reduce the repetition period, it is desirable that the holding current IH of the thyristor be large. However, it is very difficult to simultaneously satisfy a high di/dt tolerance and a large IH value due to the design and manufacturing of the thyristor itself. To explain this point, first we will briefly discuss the phenomenon when the thyristor is turned on. 3A to 3C are diagrams for explaining the state of the thyristor 5 when it is turned on, with FIG. 3A being a sectional view and FIGS. 3B and 3C being a plan view.

In the figure, 6 is a cathode, 7 is an anode, 8 is an n-type emitter layer (n ear layer), 9 is a p-type base layer (PB layer), 10 is an n-type base layer (n8 layer), 11' is a p-type The emitter layer (pE layer) 12 is a gate electrode connected to the pB layer 9. The thyristor 5 receives a gate current i supplied from the gate electrode 12.
Although turn-on starts due to the pB layer 9's sheet resistance y, it does not penetrate sufficiently into the inside of the pB layer 9, and the gate electrode 1
A portion from a position corresponding to the end of the nE layer 8 facing 2 to a predetermined distance 1 (a fraction of one skin to one sail) (illustrated A
(area).

Therefore, the thyristor 5 is turned on in a process in which the region A is first turned on, and the turn-on spreads over time. In fact, if the gate current ig is not sufficiently larger than the gate trigger current of the thyristor 5, only a part of the end of the nE layer 8 may be turned on, as shown by region q in FIG. 3c. As is well known,
When the rise of the main current is large, the main fin flow concentrates in this initial turn-on region, causing overheating breakdown. Therefore, d
In order to increase the i/dt resistance, it is necessary to make the initial turn-on region A caused by the gate current ic as large as possible. In particular, it is necessary to prevent 4. localized dusk-on as shown in FIG. 3c. For this purpose, it is best to make the gate current ig, especially the gate current i6, reach several times the gate trigger current value of the element within 1 ms, but in reality, the gate current j generated in the gate circuit
There is a limit to the rise of g, and the above request is often not honored. Therefore, it is necessary to increase the amplification degree hfe of the transistor composed of the nE layer 8, the p8 layer 9, and the nB layer 10 as much as possible to reduce the gate trigger current as much as possible.
On the other hand, the holding current IH is the minimum current value necessary for the thyristor 5 to maintain the conductive state, and has a strong correlation with the gate trigger current, and has a strong correlation with the gate trigger current.
However, highly sensitive devices can also maintain conduction with small current values.

(holding current IH is small). For these reasons, it has been said that it is difficult to realize a device that has both a high di/dt tolerance and a large IH value.
The current amplification factor Qnpn of the ear pBnB transistor (that is, the thyristor sensitivity of this part) is the gate 12 and cathode 6.
The main current flow path of this thyristor 5 is divided into the above-mentioned area A and the above-mentioned area B which is not affected by the external impedance, and the area B is It has a structure with a large holding current IH, and in region A, a large current amplification factor Qn at turn-on.
By increasing the di/dt tolerance with pn, setting the external impedance to an appropriate value after turn-on, and making the holding current IH in region A higher than that in region B, the di/d tolerance can be increased. The object is to obtain a large thyristor with a large holding current IH.

FIG. 4 is a sectional view showing a first embodiment of the invention.

In the figure, 13 indicates a short circuit point (called a short emitter) of the N8 layer 8 provided in region B, 14 indicates a gate signal source, and 15 indicates the impedance of the gate circuit. first,
Considering the case where the gate circuit is not connected, as is clear from the above structure, region B is short emitter 1.
3 are provided in large numbers, and an anode 7 and a cathode 6 are provided in the small fin region.
Almost all of the current flowing between is bypassed through this short emitter 13 and does not work effectively to switch the PNP material mechanism, so the holding current IH becomes large.

And, as the density of this short-term ivy 13 increases,
The proportion of the bypass current increases and the holding current IH can be made larger and larger. On the other hand, since no short emitter is provided in the nE layer 8 in the region A near the gate electrode 12, the current flowing through this part effectively works to switch the scales of the PNP material, so the holding current IH becomes small. ing. Therefore, when the gate signal source 14 is connected and the gate current ig is supplied, it works to effectively turn on the pnpn mechanism, so the gate trigger current can be made small, and the entire gate can be turned on with a small amount of gate current ig. .
That is, a high di/dt tree weight can be obtained. Moreover, after the turn-on is completed, the output of the gate signal source 14 becomes zero, but there is an impedance of 1 between the gate electrode 12 and the cathode 6.
Since the gate circuit including 5 is connected, this area A
Most of the current flowing through the gate electrode 12 bypasses the gate electrode 12 as shown in FIG. Therefore, by appropriately selecting the value of the impedance 15, the holding current IH in this portion can be selected to be larger than the holding current IH value in the region B described above. That is, the signal source 14 of the gate circuit
The value of the impedance 15 may be about one order of magnitude lower than the internal impedance between the gate and the cathode, although this may vary depending on the nature of the impedance or a capacitor (not shown). For example, in a 3-amp class high-speed switching thyristor, the internal impedance between the gate and cathode is about 1000, whereas the impedance of the gate circuit is 16
It is desirable to select approximately 100. In this way, it is possible to achieve both high di/dt tolerance and large holding current IH. FIG. 5 is a sectional view showing the configuration of a second embodiment of the present invention.
Layer 8 is made thinner and pB layer 9 is made thicker.

By increasing the thickness of the p8 layer 9 in this way, the above-mentioned nE
The base layer of the npn transistor consisting of layer 8, pB layer 9 and nB layer 10 becomes thicker, the current amplification factor Qnpn decreases, and the holding current increases by an order of magnitude. Furthermore, the pB layer 9 is usually formed by a diffusion method, and the p8 layer 9
The impurity concentration increases closer to the surface. Therefore, by making the depth of the n8 layer 8 shallow, an n8pB junction is formed in a region of the pB layer 9 where the impurity concentration is high, and the carrier injection efficiency at that junction becomes low. It has the effect of increasing IH. 6th
The figure is a sectional view showing the configuration of a third embodiment of the invention.

In this embodiment, the structure is similar to the conventional device shown in FIG. 3, but by introducing impurities such as gold or irradiating radiation only in region B, the carrier lifetime in this region is reduced and the carrier retention is reduced. The current IH is increased and is 0. In the second and third embodiments shown in FIGS. 5 and 6, the gate circuits are the same as in the first embodiment explained with reference to FIG. The current value IH and low current can be achieved at the same time.

In the above embodiment, the gate electrode 12 was provided on the pB layer 9, but
The present invention can also be applied to the case where the nB layer 1 and the gate electrode 12 are provided.

As detailed above, in the present invention, in a thyristor having a pnpn structure 0, the holding current value of the region is affected by the impedance of the gate circuit connected between the gate electrode and the cathode. The second region B has a structure in which the holding current value is large, and the first region A has a structure in which the holding current value is large, and the first region A has a large di/
After turning on, the holding current in the first region A was set to 0 so as to exceed that in the second region B by using an appropriately sized impedance of the gate circuit, resulting in a high di/ A thyristor device having both dt withstand capability and a large holding current value can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example in which a thyristor is used as a switch for the discharge path of charged charges, Figure 2 is a waveform diagram of the discharge current passing through the thyristor of this thyristor circuit, and Figures 3 a to c are when the thyristor is turned on. FIG. 2 is a diagram for explaining the state of FIG. Figures 4, 5 and 6 are the first diagrams of this invention, respectively.
FIG. 2 is a cross-sectional view showing the configuration of the second and third embodiments. In the figure, 5 is a thyristor, 6 is a cathode, 7 is an anode,
8 is an n-type emitter layer, 9 is a p-type base layer, 10 is an n-type base layer, 11 is a p-type emitter layer, 12 is a gate electrode, 1
3 is a short emitter, 14 is a gate signal source, 15 is an impedance of the gate circuit, A is a first region, and B is a second region.
This is the area of Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Scope of Claims] 1. N-type emitter layers, p
a semiconductor substrate comprising a type paste layer, an n-type paste layer, a p-type emitter layer, a cathode provided in contact with the n-type emitter layer, an anode provided in contact with the p-type emitter layer; The thyristor has a gate electrode electrically connected to the p-type or n-type space layer, and the thyristor sensitivity at turn-on in the peripheral area of the gate electrode is high, and the thyristor is connected between the gate electrode and the cathode. A first region whose holding current value is affected by the impedance of the gate circuit and a second region other than the first region are provided, and the second region is structured such that the holding current value becomes large, A thyristor device, characterized in that the impedance of the gate circuit is set to a required value so that the holding current value in the first region is further greater than the holding current value in the second region. 2. The thyristor device according to claim 1, wherein the impedance value of the gate circuit is adjusted so that the holding current value in the first region is equal to the holding current value in the second region. . 3. The thyristor device according to claim 1 or 2, wherein the n-type emitter layer in the second region has a structure having a large number of short emitters. 4. Claim 1 or 2, characterized in that the thickness of the emitter layer formed in contact with the paste layer on which the gate electrode is provided is smaller in the second region than in the first region. Thyristor device as described in Section. 5. The thyristor device according to claim 1 or 2, characterized in that the lifetime of the carrier in the second region is shorter than that in the first region.