JPS6011816B2 - semiconductor switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor switch as a PNPN switch, and particularly to a semiconductor switch whose dv/dt withstand capability is improved.

A PNPN switch is useful as a semiconductor switch because it has a high blocking voltage in the positive and negative directions and can control a large amount of power with a small control fin force due to its self-holding action.

However, on the other hand, if there is a sudden increase in forward voltage (noise voltage) between the anode and cathode, there is a problem that ignition may occur erroneously due to the voltage variation rate dv/dt. For this reason, it has been considered to increase the dv/dt resistance, but this requires sufficient consideration. Normally, the dv/dt tolerance is increased by short-circuiting the gate and cathode with a low resistance, but this method has an additional problem of deterioration of control sensitivity. In addition to this method, the methods shown in FIGS. 1 to 3 have been known so far. That is, what is shown in Fig. 1 is PNPN.
Transistor 2 is connected between the gate G and cathode K of switch 1.
The collector and emitter are connected to each other, and the base thereof is connected to the anode A of the PNPN switch via a capacitor 3.

When a sudden forward voltage is applied, the transistor 2 is operated transiently by the charging current of the capacitor 3, and the gate G and cathode K are short-circuited. In this case, normally the transistor 2 is not operating, so the control sensitivity from the gate G does not deteriorate at all, and therefore the first
The one shown in the figure is the best in achieving both dv/dt tolerance and control sensitivity. However, since a capacitor requires a large area in a semiconductor IC, the configuration shown in FIG. 1 is not suitable for integration. For this reason, the applicant has proposed a device as shown in FIG. 2 that is advantageous for integrated circuit implementation. As shown in the figure, a diode 4 is provided between the base of the transistor 2 and the layer (anode gate) adjacent to the anode A of the PNPN switch 1, and the current that charges the junction capacitance of the diode 4 is similar to that shown in FIG. The idea is to perform a transient short circuit. However, when the circuit is configured in this way, a differential current flows from the N layer (anode gate) adjacent to the anode A in the direction of the diode 4, so an anode gate drive is also added.
It is conceivable that the v/dt tolerance is slightly worse than that shown in FIG. Furthermore, the circuit shown in FIG. 3 has been proposed as an integrated circuit version of the circuit shown in FIG. 1 while eliminating the anode gate drive.

In the one shown in FIG. 3, a second transistor 5 is provided between the anode A and the base of the transistor 2.
The space is to be left open. Even with this configuration, there is a drawback that the dv/dt tolerance is slightly degraded. This is because the base terminal of the second transistor 5 is not connected to either, so if a dv/dt pulse is repeatedly applied between the electrode A and the cathode K at a fast cycle,
This is because charges remain accumulated in the base, and the differential current decreases, making it virtually impossible to expect large or medium improvements in dv/dt tolerance. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a semiconductor switch that can be integrated, and has excellent dv/dt tolerance.

For this purpose, the invention provides that the base of the second transistor is connected to a layer adjacent to the main terminal (anode A) of the PNPN switch via a resistive element for discharging charges.

Hereinafter, the present invention will be explained in detail with reference to FIGS. 4 and 5.

First, FIG. 4 shows the basic circuit configuration of a semiconductor switch according to the present invention.

According to this, the collector and emitter of a first transistor (NPN type) 12 are connected between the gate G and cathode K of a PNPN switch 11 having an anode A, a cathode K, and a gate G, and the emitter is connected to the base of the first transistor (NPN type). The collector of a second transistor (PNF type) 16 is connected to the anode A of the PNPN switch 11. Now, the feature of the present invention is that the base of the second transistor 16 is connected to the N layer (anode gate) adjacent to the anode A via the resistor 17. This resistor 17 is for discharging the charge accumulated in the base of the second transistor 16 and keeping it at almost the same potential as the anode gate of the PNPN switch 11 forever, as will be described later.
Generally, it is configured as a specially manufactured resistor, but in addition to this, in high-voltage ICs, the base internal resistance of the transistor 16 (which tends to have a relatively high resistance)
And the anode gate internal resistance of the PNPN switch 11 may be treated as an equivalent resistive part,
Further, in some cases, it may be something that shows resistance in alternating current, such as a coil. According to such a configuration, PNPN
When a forward voltage rise is applied between the anode A and cathode K of the switch 11, the current that charges the junction capacitance present at the base-collector junction of the second transistor 16 is mirror-amplified and flows to the base of the first transistor 12. As a result, the first transistor 12 operates and the gate G,
Since the cathode K is short-circuited, the PNPN switch 1
This is to prevent the rate effect due to the charging current of the central junction of 1.

At this time, there is almost no potential difference between both ends of the resistor 17. This is because both ends of the resistor 17 have a potential from the anode A through one junction, and since they are of equal rank, no current flows, and even if there is a slight potential difference, the current is limited by the resistor, as shown in Figure 2. The problem pointed out in 2 does not occur at all, and a dv/dt protection effect equivalent to that shown in FIG. 1 can be obtained. On the other hand, while a DC voltage is applied between the anode A and cathode K of the PNPN switch 11,
When a current flows through the gate G to turn on the PNPN switch 1 1, the potential difference between the anode A and the cathode K decreases (
(approximately IV) However, if there is no resistor 17, the charge that was charged between the base and collector of the transistor 16 before switching on (the charge where the base is positive and the collector is negative) will be transferred to the base and emitter. Because it is in the blocking direction, the discharge cannot be completed, and as mentioned in Fig. 3, the dv/d decreases significantly.
This will cause the problem that the protective effect will be reduced. For example, a withstand voltage of 500 V/ms or more in slow repetitions may drop to several tens of V/ms in fast repetitions. However, in the present invention, since the resistor 17 is provided, it is clear that the base potential of the transistor 16 quickly approaches the anode gate potential of the PNPN switch according to the resistance value of the resistor 17 and the time constant of the junction capacitance immediately after ignition. . As a result, almost the same level of dv/dt protection effect can be obtained even when the forward voltage rises are repeated at a high speed as when the forward voltage increases are repeated at a constant speed. FIG. 5 shows a circuit configuration when the present invention is applied to a bidirectional semiconductor switch.

A pair of anti-parallel connected PNPN switches 31, 31' having a common anode gate layer (N layer) have respective gates G, , G2, cathodes T2, . The first transistors 32, 32', collectors and emitters are connected between the first transistors 32 and 32', and the resistors 38 and 38' are connected between the first transistors 32 and 32', and the emitters and the bases of the transistors 32 and 32' are connected between the transistors 32 and 32'. diodes 39 and 39' are provided, and each base is connected to a second transistor 36 as shown. The base of the second transistor 36 is connected to the anode gate (common N layer) via a resistor 37. In FIG. 5, the second transistor 36 is shown as having two emitters and no collector; however, depending on the polarity of the applied voltage, one of the two emitters is a true emitter and the other is a true emitter. acts as a true collector; in other polarities, one acts as a collector and the other acts as an emitter. This configuration can be easily realized by configuring it as a lateral transistor in an integrated circuit, and the reverse blocking voltage between the two emitters and the base is both high. Also, resistors 38, 38
' is provided to provide stability against high temperature leakage current of the PNPN switches 31, 31', and may have a relatively high resistance. The diodes 39, 39' are connected to the two emitters of the second transistor 36 connected between the bases of the two transistors 32, 32', and the potential difference between the two main terminals T, T2 of the PNPN switch is an iron diode. It is designed to be applied indirectly through the oscillator, and also has the role of preventing oscillation. In such a configuration, for example, when the potential of the main terminal T, increases in the positive direction with respect to the royal state T2, the potential of the main terminal T, is applied to the illustrated upper emitter of the transistor 36 via the diode 39', and the fourth As shown in the figure, the transistor 32 operates to prevent the PNPN switch 31 from turning on.

In this case, the PNPN switch 31' is in the reverse blocking state, but when the PNPN switch 31 is controlled to fire, the resistor 3
7 has a significant effect on the discharge of charge from the transistor 36, as in the previous example. When the potential relationship is reversed, the diode 39 and the transistors 36 and 32' can prevent the rate effect of the PNPN switch 31'. Here, PNPN switch 3 1, 3 1'
was shown using an example of anti-parallel connected switches with a common anode gate layer (N), but it is possible to connect two normal PNPN switches in anti-parallel and add a resistor to the anode gate layer (N layer) of each PNPN switch. Of course, the same functions can be obtained even when connected. In addition, in the above explanation,
Although the second transistors 16 and 36 are implicitly described as PNP type which can obtain a high withstand voltage in both positive and negative directions when integrated at the same time as a PNPN switch, the P type and N type in these embodiments are all reversed. It goes without saying that a complementary circuit configuration can also be implemented.

As explained above, according to the present invention, not only the DV/DT withstand capability of the PNPN switch is improved, but also the integration becomes easy, and the present invention is useful especially when a fast-cycle voltage change is applied. It has become.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are diagrams showing the circuit configuration of a semiconductor switch according to a known technique, and FIGS. 4 and 5 are diagrams each showing the circuit configuration of a semiconductor switch in an embodiment of the present invention. be. 1 1, 3 1, 3 1'... PNPN switch, 12, 32, 32'... First transistor, 16
, 36, 36'... second transistor, 17, 37,
37'...Resistor, 39,39'...Diode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. Consisting of a PNPN switch element and first and second transistors, the emitter terminal of the first transistor is connected to one main terminal of the PNPN switch element,
The collector terminal is connected to a layer adjacent to the layer from which the main terminal is taken out, while the emitter terminal of the second transistor is directly or indirectly connected to the other main terminal of the PNPN switch element, and the collector terminal is A semiconductor switch characterized in that the base terminal of the first transistor is connected to the base terminal of the second transistor, and the base terminal of the second transistor is connected via a resistor to a layer adjacent to the layer from which the other main terminal is taken out. . 2 The second transistor consists of two P
A semiconductor switch according to claim 1, which is connected in common to an NPN switch element.