JPS6011865B2 - Time division multiplexing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division multiplexing method that has a plurality of data lines and uses a memory that can be accessed only in word units at a time as a buffer for transmitted and received data.

Normally, when performing time-division processing with a data transmission device that accommodates multiple data lines, if the number of data lines is N and the signal transmission rate is Vbit/sec, the transmitting side calculates the processing time per line within 1 bit (time slot). Transmission data written from the central processing unit to the line memory in the data transmission device by being assigned to the MADE eC is bit-multiplexed for each data line and time-division multiplexed on a frame-by-frame basis. The line memory used as a buffer for sending and receiving data in such data transmission equipment is a memory that can only be accessed in word units at a time, that is, one address consists of n bits, and when one address is accessed, n bits are accessed at the same time. When using a memory such as This method has the disadvantage that the transmission data of the line must be read word by word from the line memory for each time slot assigned to the data line. The present invention solves these drawbacks, and allows transmission of each data line from the line memory by allocating line numbers in the bit direction of the line memory, allocating line numbers in the word direction, and accommodating transmission data in the word direction. This makes it possible to read one bit of data at the same time, and eliminates the process of reading out transmission data from the line memory for each time slot, thereby simplifying data transmission processing control to the data line and reducing the amount of processing.

The conventional method will be explained below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a data transmission device for explaining processing of transmission data.

In the figure, 1 is, for example, an 8-bit 1 buffer register for data transfer with the central processing unit;
2 is an address selection circuit that specifies the address of the line memory, and 3 is a control circuit that performs interface control with the central processing unit, control of writing and reading data to the line memory, check bit operation, etc., and a transmission common to all lines. It is also equipped with a bit counter, a line number counter for specifying a line in time division multiplexing, etc. 4 is a line memory for a control information buffer and a transmission/reception data buffer for time-division processing of each line, and is a random access memory that can only be accessed in word units at a time.

Reference numeral 5 denotes a shift register that converts the transmission data retrieved from the line memory into parallel and serial data for each time slot assigned to each data line.

6 is the transmission data by the line number counter in the control circuit.
This is a transmission data distribution circuit that distributes data to data transmission terminal devices.

Reference numeral 7 denotes a data transmission terminal device having 18 data lines each and having an interface function between the data transmission device and the data line, such as sending out transmission data and sampling received data.

8 is a data line.

FIG. 2 shows a method for accommodating transmission data in the line memory 4, in which line numbers 100 to Ion are assigned in the word direction,
Data L to bn for each data line are accommodated in the bit direction.

Therefore, if you can only access in word units at one time, you can only access in line number units at one time. The control operation will be explained below. Transmission data transferred from the central processing unit to the data transmission device (for example, 1
7 frames 32 bits) is 10 in 8 bits (words)
Transferred in parallel to buffer register 1.

In the following explanation, one word is n bits and one frame is four words.The control circuit 3 activates the address selection circuit 2 and writes the data in the 10 buffer registers to the address of the allocated line memory 4 for each line. When the data of the 10 buffer register is written to the line memory 4, the control circuit 3 writes the next n bits of data from the central processing bag counterfeit to the line memory 4.
Receive into buffer register 1.

The n bits of data received by the 10 buffer register 1 are similarly written to the line memory 4.

As described above, one frame of transmission data (2) bits is written into the line memory 4 four times by n bits each.

At this time, the line memory 4 stores transmission data to each data line in the bit direction as shown in FIG. The transmission data to each data line written in the line memory 4 is sent to the control circuit 3 according to the time slot assigned to each line.
8 bits are read from the line memory 4 and set in the shift register 5. Of the n bits set in the shift register 5, the transmission bit is determined by the value of a transmission bit counter (not shown) in the control circuit. That is,
Among the n-bit transmission data set in the shift register, L is specified first from the outside of the transmission bit counter, and one bit of this bo is assigned by the transmission data distribution circuit 6 according to the line number indicated by the line number counter in the control circuit 3. It is distributed to the data transmission terminal device 7 corresponding to the data line and sent out to the data line 8. After the above processing, the shift register 5 is shifted by one bit and written to the corresponding address in the line memory 4 by the control circuit 3.

In this way, for one bit of transmission data to each data line, the processes from reading the transmission data to the shift register 5 to rewriting are performed according to the sequence within the time slot assigned to each line. Therefore, for each 1-bit transmission process to each data line, the transmission data is transferred from the line memory 4.
- Data transmission processing control was complicated because it was necessary to read and rewrite data. Therefore, in the present invention, the data to be transferred is handled by the central processing unit in the word direction (corresponding to the address) by assigning a line number to each of the n bits constituting one address. By doing so, when data is sent from the line memory to each data line, it is possible to simultaneously read out one bit of data transmitted to each data line with one memory access.

Therefore, it is no longer necessary to read and rewrite the transmission data from the line memory every time one bit is transmitted to each data line as in the prior art, which simplifies data transmission processing control and reduces the amount of processing. One embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram of a data transmission device for processing transmitted data according to the present invention.

In the figure, 9 is a 10 buffer register, 12 is a control circuit, 13 is an address selection circuit, 14 is a line memory, 1
6 is a transmission data distribution circuit, 17 is a transmission terminal device, and 18 is a data line, whose functions are roughly the same as in the conventional case. Reference numeral 10 denotes a data register, which is a register of ■ bits for one frame of transmission data, which is used as a buffer when the transmission data transferred in units of n bits from the central processing unit is stored in the line memory 14.

A bit selection circuit 11 selects transmission data bit by bit in order to accommodate data in the word direction of the line memory.

A buffer register 15 is a 1-bit buffer register corresponding to each data line.

FIG. 4 shows a method of accommodating transmission data in a line memory according to the present invention, in which line numbers 100 to 1 are allocated in the bit direction and transmission data b to bn to each data line are accommodated in the word direction.

Therefore, it is possible to simultaneously read specific bits of the transmission data, for example, the value of the pittom, for the data lines 100 to Ion with one memory access. The control operation will be explained below. Transmission data transferred in parallel from the central processing unit to 10 buffer registers 9 in units of n bits is stored in a data register 10 containing 32 bits for one frame of transmission data.

When data for one frame is stored in the data register 10, data transfer from the central processing unit is stopped, and the control circuit 12 is operated by the bit selection circuit 11 and the address selection circuit 13.
is activated, and the transmission data stored in the data register 10' is sequentially written bit by bit into the position of the corresponding line number in the line memory 4. That is, it is possible to write n bits in one access, but in this case, only one bit (for example, Q bit) is written, and other bits are not written. This is because the line memory can only be accessed in word units at a time, so it is necessary to specify an address for each bit of transmission data, and n accesses are required to write all n bits that make up one address. become. In this way, the line memo IJI stores the line number in the bit direction and the transmission data of each data line in the word direction, as shown in FIG. Therefore, by specifying a certain address, it is possible to read out one bit of transmission data from each line at the same time. When all the transmission data stored in the data register 10' is written to the line memory, the control circuit requests the central processing unit to transfer the transmission data to the next data line, and similarly transfers the transmission data and writes it to the line memory. will be carried out. On the other hand, among the transmission data written in the line memory, one bit of transmission data corresponding to the value of a transmission bit counter (not shown) in the control circuit is time-divisionally processed according to the time slot assigned to each line and sent to the data line. Sent out. When the transmission bit counter is incremented, the control circuit increments the line memory 14 according to the value of the transmission bit counter.
access the corresponding bit, for example, wide, and each line 100~
One bit of transmission data of 10m is read out at the same time and set in the buffer register 15. Each bit of transmission data set in the buffer register 5 is distributed to the data transmission terminal device 17 by the transmission data distribution circuit 16 according to the value of a line number counter (not shown) within the time slot assigned to each line, and the data is It is sent to line 18. Next, the transmission bit counter in the control circuit 12 increments, and the next 1 bit of transmission data is processed by the same machine.

The above processing continues for one frame of transmission data, and when the processing for one frame is completed, the transmission bit counter is reset, and the processing is repeated again from the first bit of the transmission data. As explained above, according to the present invention, even if a memory that can only be accessed in word units at a time is used, each bit of transmission data for multiple lines can be simultaneously read out in one memory access, and each data Since memory access for reading and writing the transmission data is not required for each bit of transmission data sent to the line is processed, data transmission processing control becomes easier and the number of memory accesses can be reduced overall, resulting in the amount of transmission data processed. It is possible to reduce the

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a conventional data transmission apparatus, and FIG. 2 shows a state in which transmission data is accommodated in the conventional method. FIG. 3 is a block diagram showing one embodiment of a data transmission device according to the present invention, and FIG. 4 shows a state in which transmission data is accommodated according to the present invention. 9 is a 10 buffer register, 10 is a data register, 11 is a bit selection circuit, 12 is a control circuit,
13 is an address selection circuit, 14 is a line memory, 15 is a buffer register, 16 is a transmission data distribution circuit, 17 is a data transmission terminal device, 100 to Ion are line numbers,
bn indicates each bit of transmission data. Many 1 figures, 2 figures, 3 scales, 48

Claims (1)

[Claims] 1 It is equipped with a memory that accommodates a plurality of data lines, one address consists of a word of n bits, and can only be accessed in word units at a time, and once data from an information processing device is stored in the memory, In a data transmission device that transmits data to multiple data lines in a time-sharing manner, a line number of each data line is assigned to each bit of each address in the memory, and multiple pieces of data to be transmitted to each data line are transmitted. A time division multiplexing method characterized by storing over the same bit position of an address.