JPS6012658B2 - stack memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a plurality of stack memories composed of low-speed memories and a high-speed buffer that holds copies of some of them.
The present invention relates to a stacked memory device with a layered structure including a memory.

Multiple pu.

In so-called multi-process processing in which processes (tasks) are processed in parallel, a stack is prepared for holding the environment of each process, that is, the intermediate results and state of the processing. Since stacks are frequently accessed during processing by the central processing unit, conventional methods have implemented multiple stacks using high-speed memory, but implementing all stacks using high-speed memory poses a cost problem. There is. FIG. 1 shows an overview of such a conventional stacked memory device. In the figure, 1-1 to 11n represent high-speed buffer memories, 2-1 does not exist, and 21n represents low-speed memory stacks created from low-speed memories, respectively. The high-speed buffer memory 1-i and the low-speed memory stack 2-i correspond to the process i, and the environment information of the technology created by the process i is held in the high-speed buffer memory 1-i and is stored in the high-speed buffer memory 1-i. Other or entire environmental information is held in the slow memory stack 2-i. High speed buffer
Each of memory 11i and slow memory stack 21i is divided into a plurality of blocks. The size of the block castle is, for example, an IK word, and a high-speed buffer
Data transfer between memory 1-i and low speed memory stack 2-i is performed in blocks. When a process pushes environment information to the fast buffer memory, when the fast buffer memory 11i becomes full, the environment information in the fast buffer memory is moved to the slow memory stack 21i. Processes also store environment information in high-speed buffer memory 1.
-i, if the desired environment information is no longer in the fast buffer memory 1-i, the slow memory
The environment information of stack 2-i is stored in high-speed buffer memory 1-
moved to i. As shown in Figure 1, the method of providing a high-speed buffer memory for each stack simplifies control, but providing multiple high-speed buffer memories poses a problem in terms of cost and also reduces the startup frequency. The existence of a dedicated high-speed buffer memory even for low-level processes is problematic from the point of view of effective resource utilization.

The present invention is based on the above consideration, and aims to provide a stack memory device that is capable of high-speed processing and is low in cost.

Therefore, the stack memory device of the present invention has a plurality of low-speed memory stacks and a plurality of block areas, each corresponding to a plurality of processes, and a high-speed buffer memory shared by the plurality of processes. a stack memory device in which data transfer between each of the low-speed memory stacks and the high-speed buffer memory is performed in units of blocks; A pointer register, a valid display flag indicating whether the data in the block is valid or not for each block area of the high-speed buffer, a stack number indicating which stack it is assigned to, and a stack number indicating which block within the stack it is assigned to. A tag mechanism in which a block number indicating whether the stack is stored, and a block number specified by the stack number in the stack pointer register and the upper digits of the stack address are registered in the tag mechanism. If the detection mechanism outputs a signal indicating that it was not registered, select the block castle to be replaced, and select it on the condition that the corresponding valid plug is on. The data of the selected block area is transferred to the corresponding low-speed memory stack, and the contents of the selected block area are transferred to the corresponding low-speed memory stack.
It is characterized in that the content is made equal to the contents of the block area of the low-speed memory stack specified by the stack number and block number of the stack point. The present invention will be described below with reference to the drawings.
FIG. 2 is a diagram showing an overview of the stacked memory device of the present invention, FIG. 3 is a block diagram of a first embodiment of the high-speed buffer memory used in the present invention, and FIG. 4 is a diagram showing the first embodiment of the high-speed buffer memory used in the present invention. FIG. 3 is a block diagram of a second embodiment of a high speed buffer memory.

In FIG. 2, 3-1 to 3-n are stack address holding registers, 4 is a stack pointer register, BI to B3 are block castles in the high-speed buffer memory 1, EI to E3 are management information entries, and V is the valid display flag, STKNO is the stack identification number, BLKNO
indicates the block identification number.

As shown in FIG. 2, the stack memory device of the present invention includes one high-speed buffer memory 1 and n low-speed buffer memories.
The stack 2-1 does not have a stack 2-1 to 21n, and this high-speed buffer memory is used in place of the plurality of high-speed buffer memories 1-1 to 11n shown in FIG.

Block areas BI to B3 constitute the data section,
Management information entries EI to E3 constitute a tag section. Stack pointer register 4 indicates the stack to be accessed and the address within the stack to push down or pop up data.
The management information entry EI is in the block castle 81, the management information entry E2 is in the block castle B2, and the management information entry E3 is in the block castle B2.
corresponds to block castle B3. Each management information entry includes a valid display flag V indicating whether the corresponding block is valid or not, a stack identification number indicating which stack the corresponding block belongs to, and the number of stacks to which the corresponding block belongs. A block number is written to indicate the The block number is equal to the upper digit part of the address in the stack. Each of the intra-stack address holding registers 3-1 and 3-n stores the address at which the corresponding process was suspended. When a process is started, the contents of the stack address holding register corresponding to the process are stored in the stack pointer register 4. The low speed memory stacks 2-1 and 21n may be formed within main memory or may be formed within a low speed memory device separate from main memory. The high-speed buffer memory is provided separately from a so-called cache memory. High-speed buffer memory 1 and low-speed memory
Data transfer between the stacks 2-1, 2-2, . . . 2-n is performed in block units. When a request is made to issue or write environment information, it is checked whether the block defined by the stack pointer register 4 exists in the high speed buffer memory 1 or not. If there is no block in fast buffer memory 1 that matches the block defined by stack pointer register 4, then either block BI or B3 is set to the stack pointer register.
Allocated to the block defined by register 4. FIG. 3 is a block diagram of one embodiment of a high speed buffer memory used in the present invention.

In FIG. 3, 5 is a data section, 6 is a tag section, 7 is a selector, 8-1 is not provided, 8-3 is a comparison circuit, and 9 is an OR circuit. Data section 5 is block area BI
The tag section 6 is composed of management information entries E1 to E3.
When reading data from the stack, the tag section 6 is searched by the stack number and block number in the stack pointer register 4, and the data section 5 is accessed by the intra-block address in the stack pointer register. For example, if the comparison circuit 8-1 indicates a match, the selector 7 selects the extracted data from the block BI. If any of the comparison circuits 8--8-3 indicates a match, the OR circuit outputs a FOUND signal of "1". When writing, the tag section 6 is first searched, and if there is a comparison circuit that shows a match, the data is stored in the block area Bi (i is either 1, 2, or 3) corresponding to the comparison circuit that shows a match. written. If the stack number and block number matching the stack pointer register 4 do not exist in the tag section 6, they are specified in an appropriate block area in the high-speed buffer memory, for example, in a paste-place circuit such as an LRU circuit. If the valid display flag V of the block area Bi to be replaced Bj (i is one of 1, 2, or 3) is logical "01," clear the block area to be replaced and then use the stack pointer register 4. The specified data block is successively extracted from the low-speed memory stack and stored in the replacement target block area Bi.In addition, if the valid display flag V of the replacement target block Bi is logical "1", the replacement target block area Bi is stored in the replacement target block area Bi. After moving the data block Bi to the low-speed memory stack and clearing the block area Bi, the data block specified by the stack pointer 4 is taken out from the low-speed memory stack and stored in the replacement target block Bj. Similar processing is performed in the case of bush down. In addition, block areas B1, B
When all the data of 2 or B3 are popped up and become empty, the corresponding valid display flag V is set to "0". FIG. 4 shows another embodiment of the high speed buffer memory used in the present invention.

In the embodiment of FIG. 4, stack pointer register 4
The block castles B1, B2, and B3 allocated to the block defined by the stack pointer register 4 are uniquely determined by the lower digits of the block number. When pop-up of data is performed, the tag part 6 is extracted by the lower digit of the block number in the stack pointer register 4, and the data extracted from the tag part 4 and the stack number of the stack pointer register 4,
If the block numbers match, the matching circuit 8
Outputs the OUND signal.

Block areas BI to B3 of the data section 5 are stack
Data accessed and retrieved using the intra-block address of the pointer register 4 is input to the selector 7. The selector 7 selects and outputs one piece of read data based on the lower digit of the block number of the stack pointer register 4. When the FOUND signal is "1", the proposal data output from the selector 7 is considered valid and is sent to the request source. When the FOUND signal is "0", the block castle Bi determined by the lower digits of the block number of stack pointer register 4 (i is either 1, 2, or 3)
Check the valid display flag V of , and find that the valid display flag V is "1"
When , the data block of the block Bi is moved to the low-speed memory stack, and after the transfer is completed, the data block specified by the stack pointer register 4 is taken out from the low-speed memory stack and stored in the block Bi. When the valid display flag V of the block area Bi is "0", the data block defined by the stack pointer register 4 is retrieved from the low-speed memory stack and stored in the block area Bi. In the case of push down, the tag section 6 is first searched, and if there is a tag in the tag section 6 that matches the stack number and block number of the stack pointer register 4, and the FOUND signal is "1". Data is written to the block location Bi determined by the lower digits of the block number of the stack pointer register 4.

When the FOUND signal is "0", check the valid display flag V of block castle Bi.The valid display flag V is "1".
When , data in block area Bi. After moving the block to the low-speed memory stack, clear the block Bi, store the data block read from the low-speed memory stack in the block Bi, and enter the management information entry E.
Register new management information in i and proceed with the process. When the valid display flag V of the block castle Bi is "0", the block castle Bi is cleared, the data block retrieved from the low-speed memory stack is stored in the block castle Bi, and a new management information entry Ei is written. Register your information and proceed with the process. In the control scheme described above, a fast buffer. If the desired block is not present in memory, the data block is removed from the slow memory stack. However, such a control method may wastefully store empty data blocks in the high speed buffer memory. For example, slow memory stack 3-
When a block area is allocated and push down processing is performed for the first block of 1, if the address in the stack crosses the block boundary, the above control method A block of data is read from the block castle and stored in a high speed buffer memory. Since the second block area of the slow memory stack 3-1 is empty, the data transfer from the slow memory stack 3-1 to the fast buffer memory 1 is completely wasteful. In order to eliminate such wasteful processing, the following control may be performed. Assume now that block area B2 has been allocated for the second block of the slow memory stack. After block area B2 is selected, check the valid display flag V of block area B2, and if this valid display flag V is "1", the data of block castle B2
The block is moved to the corresponding low-speed memory stack, the block castle B2 is cleared, and the management information of the second block of the low-speed memory stack 3-1 is then registered in the management information entry E2. If the valid display flag V of block castle B2 is "01," clear the block area B2,
The management information of the second block of the low-speed memory stack 3-1 is registered in the management information entry E2. Also, the third
In the embodiments shown in FIG. 4 and FIG. 4, the tag section 6 is referenced every time a push down or pop up is performed. The tag part may be referenced only occasionally.

As is clear from the above description, the stack memory device of the present invention is composed of one high-speed buffer memory and a plurality of low-speed stack memories, so that high-speed processing is possible and the cost is low. It has the advantage of being

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of a subordinate stack memory device;
FIG. 2 is a diagram showing an overview of the stacked memory device of the present invention, FIG. 3 is a block diagram of a first embodiment of the high-speed buffer memory used in the present invention, and FIG. 4 is a diagram showing the first embodiment of the high-speed buffer memory used in the present invention. FIG. 3 is a block diagram of a second embodiment of a high speed buffer memory. 3-1 to 31n...Internal address holding register, 4...Stack pointer register, BI to B3...Block area in high-speed buffer memory 1,
EI or E3... Management information entry, V...
...Valid display flag, STKN○...Stack identification number, BLKN○...Flock identification number, 5...Data section, 6...Tag section, 7...Selector section, 8-1 None, 8-3... Comparison circuit, 9...
...OR circuit. Next - ward a outside z figure'' o 3 figure next 4 figure

Claims (1)

[Claims] 1 each having a plurality of low-speed memory stacks and a plurality of block areas corresponding to each of the plurality of processes, and comprising a high-speed buffer memory shared by the plurality of processes, each of the above-mentioned low-speed memory stacks and the above-mentioned high-speed buffer memory A stack memory device in which data is transferred to and from a buffer memory in units of blocks, including a stack pointer register in which the number of the stack to be accessed and an address within the stack are stored, and a block area of the high-speed buffer memory. For each block area, a valid display flag indicating whether the data in the block area is valid or not, a stack number indicating which stack it is assigned to, and a block number indicating which block within the stack it is assigned to are stored. The tag mechanism and the above stack
and a detection mechanism for detecting whether or not the stack number in the pointer register and the block number specified by the upper digits of the stack address are registered in the tag mechanism, and the detection mechanism is not registered. If a signal indicating this is output, the block area to be replaced is selected, and the data in the selected block area is transferred to the corresponding low-speed memory stack, provided that the corresponding valid flag is on. , a stack memory device configured such that the content of the selected block area is equal to the content of the block area of the low-speed memory stack specified by the stack number of the stack pointer and the block number. .