JPS6012777B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing integrated circuits, and is particularly intended to improve various problems related to mask positional deviation and integration density caused by the application of photolithography. be.

[Technical background of the invention and its problems]

In general, compared to single-channel type insulated gate field-effect integrated circuits, complementary insulated gate field-effect integrated circuits require more photo-etching processes, so we will take this complementary type of integrated circuit as an example and discuss the problems brought about by applying the photo-etching process. Consider the following points.

Therefore, FIG. 1 shows a plan view configuring a complementary inverter circuit as a basic unit of the complementary integrated circuit, and a second
The conventional manufacturing method will be explained by showing the manufacturing process in a cross section taken along the line AA' in FIG. 1. First, as shown in FIG. 2A, an insulating layer 24 having barrier holes 23 is formed on the surface of an N-type semiconductor substrate 1 having an impurity concentration of 1, 5 to 1, and 6 arc-3 bases. Impurities are introduced into the surface of the substrate 1 through the hole 23 to form a P-type semiconductor region 2 having an impurity concentration of approximately 1-6 to 1-7 arc-3. This region 2 is commonly referred to as the P-well. Next, as shown in the opening of Figure 2, an insulating layer 24' is formed by oxidation treatment, and three barrier holes 25, 252, 253 are simultaneously formed in this insulating layer 24' by photolithography. Hole 25,,25
2,253 to form an N-type source region 3 and drain region 4 for an N-channel type insulated gate field effect transistor (hereinafter referred to as N-FET) in the P-well 2; An N-type semiconductor layer 21 for a channel stopper is formed on a part of the surface of the base 1 . After that, through an oxidation process, the dark hole 25 is formed as shown in FIG.
, ~253, the insulating layer 24
', there are three checkpoints 26, . 262 and 263 are simultaneously formed by photolithography, P-type impurities are diffused through these holes, and a P-type source for a P-channel type insulated gate field effect transistor (hereinafter referred to as P-FET) is formed in the substrate 1. A region 5 and a drain region 6 are formed, and a P-type semiconductor layer 22 for a channel stopper is formed at a position spanning the surfaces of the P-well 2 and the substrate 1. After an oxidation process, the insulating layer 24' is photo-etched as shown in FIG. The surface is exposed and oxidized again to form thin gate insulating films 9 and 10, respectively. Next, as shown in the tree in FIG. 2, photoetching is performed to form barrier holes 13 and 11 at positions corresponding to the source region 3 and drain region 4, respectively, for the N-FET.
At the same time, barrier holes 14 and 12 are formed at positions corresponding to the source region 5 and drain region 6 for the P-FET, respectively. Then, as shown in FIG. 2, a conductive material is applied to the entire surface and photo-etched to provide a wiring pattern, and the drain region 4 of the N-FET and the drain region of the P-FET are formed through the gate holes 11 and 12. 6 is formed. Also formed are conductive layers 16 and 17 for the solenoid, which are connected to the source regions 3 and 5 through the barrier holes 13 and 14, respectively, and are supplied with a low potential power source and a high potential power source, respectively. Furthermore, N-F is formed on the gate insulating films 9 and 10.
A gate electrode 7 for ET and a gate electrode 8 for P-FET are formed, respectively. Note that 18 in FIG. 1 is a conductor that connects the gate electrodes 7 and 8, and also communicates with a conductive path 19 that receives an input signal. Further, 20 is a conductive path connected to the conductive layer 15 for extracting an output signal. As mentioned above, complementary integrated circuits have a fairly complex shape on a plane pattern, and it is necessary to repeat the photo engraving process many times. ) problems are likely to occur, and the p-type drain region 6
and the N-type stopper 21, the overlap margin cA between the drain region 6 or source region 5 and the gate insulating film 10, and the margin Pp between the drain region 6 and the opening 12.
, drain region 6 or source region 5 and gate electrode 8
The masks must be matched with great care with respect to the overlap margin p between the N-type stopper 21 and the extension of the gate electrode 8, and the overlap margin fp between the N-type stopper 21 and the extension of the gate electrode 8, which is accompanied by manufacturing difficulties.

Therefore, if we focus on the above-mentioned minimum required spacing bp as one of the problems with such a follow-up method, we can see that the N-type stopper 21 and P
In forming the shaped drain region 6, separate photolithography and impurity diffusion processes are performed, so mask misalignment occurs between them.

These spaced grains p must be maintained at a predetermined size in order to maintain a high electrical withstand voltage between the drain region 6 and the substrate 1, but due to the mask misalignment, the bp becomes small and the withstand voltage is reduced. may decrease. In addition, if you try to avoid the drop in withstand voltage, the interval bp is increased in anticipation of mask shift.
This results in a large design, resulting in a reduction in integration density. On the other hand, in a complementary integrated circuit, a protective diode is connected to the substrate 1 or P in order to prevent electrical breakdown of the gate insulating film of the FET included therein.
- The conventional manufacturing method of this protective diode part, which is formed in the well 2, will be explained with reference to FIG.

First, as shown in FIG. 3A, an insulating layer 24' is formed on the N-type semiconductor substrate 1, and the insulating layer 24' is photo-etched to form the barrier holes 27. Then, a P-type impurity is diffused through the barrier hole 27 to form a P-type semiconductor layer 28 on the surface of the substrate 1, thereby forming a PN junction. Next, through an oxidation process and photolithography, another barrier hole 272 is formed in the insulating layer 24' as shown in the opening of the figure. Then, an N-type impurity is diffused through this opening 272 to form an N-type semiconductor layer 29. The width of the P-type semiconductor layer 28 in the lateral direction must be determined to a desired value by taking into consideration its resistance value and the like. The N-type semiconductor layer 29 is given a higher impurity concentration than the base 1 in order to adjust the breakdown voltage of the PN junction according to the withstand voltage of the gate insulating film, and is given an impurity concentration higher than that of the base 1. In contrast to the case where the distance between the P-type stopper 21 and the drain 6 is p, the P-type semiconductor layer 2 is
Must be adjacent to 8. However, even in the formation of such a diode, as in the case of forming the FET shown in FIGS. 1 and 2, separate photolithography steps and diffusion steps are performed, so mask misalignment is likely to occur. the result,
The P-type semiconductor layer 28 and the N-type semiconductor layer 29 may not be adjacent to each other and may be separated from each other, so that the desired breakdown voltage of the PN junction cannot be obtained and the function as a protection diode is often lost. In order to obtain this reliable adjacency, the openings 2 are made so that the semiconductor layers 28 and 29 overlap considerably, taking into account the mask shift during photolithography.
72 must be increased, which impedes improvement in the degree of integration.
In particular, when the semiconductor layer 28 is designed to have a small width in the lateral direction, such as when a high degree of integration is desired, the presence of the above-mentioned overlap makes it impossible to maintain the desired value in the lateral direction of the semiconductor layer 28 . In order to maintain this, it is necessary to minimize the overlap, but this causes many drawbacks, such as making mask alignment extremely difficult. As described above, in the conventional method, the problem of mask position shift and integration density caused by the application of photolithography differs in detail between the FET part and the protection diode part in a complementary integrated circuit. The problem-solving methods shown in FIGS. 1 and 2 and those shown in FIG. 3 are naturally different. [Object of the Invention] The present invention provides an improved method for manufacturing an integrated circuit having a plurality of circuit elements so as to eliminate the drawbacks such as those in the manufacturing of the secondary protection diode portion. The present invention provides a method.

[Summary of the invention]

The present invention focuses on a protection diode part in an integrated circuit, and when forming this diode part, an opening is formed in an insulating film on a semiconductor substrate that does not transmit impurities, and a part of the substrate surface within this hole is formed. A low-temperature oxide film containing impurities of one conductivity type is deposited on the area.

Then, using the barrier hole as a common mask hole, impurities of one conductivity type are diffused from the low-temperature oxide film into a part of the substrate surface, and impurities of the other conductivity type are diffused into other parts of the substrate surface. The method is characterized in that diffusion semiconductor layers of different waveguide types can be simply and precisely formed side by side in a predetermined area by diffusing the semiconductor layers. [Embodiment of the Invention] Next, an embodiment of the present invention will be described with reference to FIG.

3A and 3B show the manufacturing process of a portion corresponding to the protection diode Di in the gate protection circuit of the MOSFET shown in FIG. First, as shown in FIG. , a photographic engraving is applied to form an opening 32 . At this point, impurity diffusion is not yet performed, and as shown in FIG. ．． A protective oxide film 332 containing no impurities, such as a CVD oxide film, is further deposited on the low-temperature oxide film 33. Depending on the conductivity type of the diffusion region to be formed, the low-temperature oxide film may be a low-temperature oxide film containing P-type impurities (for example, shelf oxide), such as a shelf oxide glass film. Further, the low temperature oxide film and the protective oxide film must be made of substantially the same material.

Considering that one of the major features of the present invention is to maintain the dimensional accuracy of the exposed surface formed on the insulating film by photolithography, the low-temperature oxide film and the protective oxide film are suitable for photographic engraving. This is because they are apparently the same film and must be able to be photo-etched in a consistent process. In this example, a phosphorus glass coating or a shelf glass coating was used as the low-temperature oxide film. These have silicon dioxide (Si02) as a main component. For this reason, the CVD oxide film and the Si02 film used as the protective oxide film must be films that can be regarded as the same film during photolithography. Next, both oxide films 33 and 332 are etched to form a barrier hole 322 by leaving a portion of the oxide films 33 and 332 in the barrier hole 32 and removing the other portion. Thereafter, the semiconductor substrate 30 is housed in a diffusion furnace having an atmosphere containing P-type impurities such as boron and heated, thereby using the barrier holes 32 of the insulating film 31 as common mask holes. Diffusion of phosphorus from the oxide film 33 into the surface portion of the substrate 30 in contact with the oxide film 33 in a direct solid state;
Further, boron is vapor-phase diffused from the exposed surface portion of the substrate 30. As a result, the P-type semiconductor layer 28 and the N-type semiconductor layer 29, which form a PN junction with the substrate 30, are formed side by side in a common barrier hole 32 as a predetermined area. In the above diffusion, the impurities phosphorus and boron are made to have different concentrations in advance, so that a difference is given to the concentrations of the P-type semiconductor layer 28 and the N-type semiconductor layer 29, and the P-type semiconductor layer 28 forms a PN junction diode. Furthermore, the N-type semiconductor layer 29 is given a higher impurity concentration than the N-type substrate 30 so as to adjust the breakdown voltage of its PN junction to a desired low value. Next, FIG. 5 shows another embodiment of the present invention, which will be explained.

First, as shown in FIG. 1A, an insulating film 31 impermeable to diffusion conductive impurities is deposited on the surface of an N-type semiconductor substrate 30, and photolithography is performed to form openings 32. Next, as shown in the opening of the same figure, a low-temperature oxide film 33 containing phosphorus, for example, a phosphorous glass coating, is directly deposited over the exposed surface of the substrate in the insulating film 31 and the barrier hole 32, and then A protective oxidized pus 332 containing no impurities, such as a CVD oxide film, is applied to the surface. Further, the low-temperature oxide film and the protective oxide film must be made of substantially the same material as in the first embodiment described above.
Both oxide films 33 and 332 are then photo-etched, leaving a portion of the oxide films 33 and 332 in the opening 32 and removing the other portion to form a barrier hole 322. After that, as shown in FIG.
A low-temperature oxide film 34 containing a P-type impurity, such as boron, is directly deposited on the surface of the substrate 30 in the portion exposed from 2, and an oxide film 342 containing no impurities is formed on the low-temperature oxide film 34.
be coated with. Next, by heating the entire semiconductor substrate 30, the barrier holes 32 are used as common mask holes to remove phosphorus from the oxide film 33, as shown in FIG.
Boron is transferred from the oxide film 34 to the oxide films 33 and 34.
, is directly solid-phase diffused onto the surface portion of the substrate 30 that is in contact with the substrate 30 . As a result, the P-type semiconductor layer 28 and the N-type semiconductor layer 29, which form a PN junction with the substrate 30, share a common barrier hole 32. formed in juxtaposition within. The concentration of each of the semiconductor layers 28 and 29 is adjusted by appropriately predetermining the amount of impurity to be included in each of the oxide films 33 and 34. In the embodiment shown in FIG. 5, a low-temperature oxide film 33 containing phosphorus,
The etching speed for specific etching agents is extremely high, several times to more than ten times higher than that of normal thermal oxide films.
There is a relationship in that the etching rate of the low-temperature oxide film 34 containing boron is 4.0 mm compared to 3.3.

Therefore, as described above, the semiconductor layer 28 of different conductivity type
and 29 are formed in parallel, a low-temperature oxide film 3 containing phosphorus is formed.
3, is applied first. That is, even though the insulating film 31 formed in the substrate 30 must be precisely defined by the openings 32 in the juxtaposition area of the semiconductor layers 28 and 29, the low-temperature oxide film 33 is photo-etched. However, since the etching rate of the oxide film 33 is high, the process can be completed in a short time.
The influence of the etching agent on the material is small, and its shape and size accuracy can be maintained. If the low temperature oxide film 34. If the insulating film 31 is formed first, the etching time becomes longer and the action of the etching agent on the insulating film 31 increases, which reduces the precision of the shape and dimensions, which is not preferable. The two embodiments described above are examples of gate protection diodes for P-FETs of complementary integrated circuits, and the diodes are obtained by forming a P-type semiconductor layer 28 on an N-type substrate 30. However, in the case of N-FET protection, there is P in the substrate 30.
Since a P-well is formed and a protection diode is provided in this P-well, the layer corresponding to the semiconductor layer 28 may be of N type.

〔Effect of the invention〕

In such a method of the present invention, when semiconductor layers of different conductivity types are formed side by side in a predetermined area as in the above embodiment, a common opening 32 provided in an insulating film 31 that does not transmit impurities is used to A planned area is determined, and a low-temperature oxide film containing impurities of one conductivity type is immediately deposited on a part of the semiconductor substrate surface exposed in this planned area, and the contained impurities are removed from the oxide film on the above-mentioned part of the substrate surface. Since the impurities of different conductivity types are diffused into other surface portions, these two semiconductor layers of different conductivity types can be reliably formed adjacent to each other regardless of mask misalignment.

Therefore, when considering the function as a protection diode, one semiconductor layer forms a PN junction, and the other semiconductor layer plays the role of adjusting the breakdown of the PN junction to a desired value. You can be sure that you will get the correct function. Since the adjoining state of the two semiconductor layers is automatically obtained as a small overlap with diffusion accuracy, there is no need to make the mask hole by photolithography as large as in the conventional method, and the degree of integration can be improved accordingly. . Since the overlap between the two semiconductor layers is minimized, the semiconductor layers can be maintained at approximately the desired size in the lateral direction. As described above, since there is almost no effect of mask displacement, there are various effects such as mask alignment in photoetching does not require as much difficulty as in the past. In addition, in complementary integrated circuits, protection diodes for N-FETs and protection diodes for P-FETs are used.
protection diodes for the same semiconductor substrate (of course N-
In the case of a FET, a P-well is interposed), but in such a case, according to the method of the present invention, an insulating film that does not transmit impurities is formed on the semiconductor substrate, and the regions where each of the diodes are to be formed are formed. Another advantage is that a plurality of barrier holes can be formed in the insulating film by one photolithography process, each corresponding to a predetermined area.

This is because a low-temperature oxide film containing impurities of one conductivity type is directly applied to a portion of the substrate surface within each of the plurality of holes, and the other portions of the substrate surface within each hole are coated directly. This is because a state in which impurities of the other conductivity type can be diffused can be provided all at once. In the method of the present invention, an insulating film that does not act as a diffusion source and does not transmit conductivity type impurities for diffusion is formed on the surface of the semiconductor substrate other than the area where semiconductor layers of different conductivity types are to be formed side by side. By forming this, the surface concentration of the semiconductor substrate under the insulating film can always be kept at the relatively low value that the substrate has.

As a result, there is an advantage that the withstand voltage of circuit elements provided in the integrated circuit can be maintained at a high level. As described above, by applying the above-described method of the present invention to a desired circuit element in a method of manufacturing an integrated circuit incorporating a plurality of circuit elements, various effects as described above can be obtained and the manufacturing process can be significantly simplified. improves.

[Brief explanation of the drawing]

1 and 2 show an example of a method for manufacturing a subordinate integrated circuit. FIG. 1 is a plan view of the integrated circuit, and FIG. Figure 3 is a process cross-sectional view showing another example of the conventional method, Figure 4 A is a process cross-sectional view showing an embodiment of the method of the present invention, 5 is a circuit diagram showing circuit elements in an integrated circuit to which this embodiment is applied, and FIG. 5 is a process sectional view showing another embodiment of the method of the present invention. 28... Semiconductor layer (P type), 29... Semiconductor layer (N type), 30... Semiconductor substrate (N type),
31...Insulating film, 32.・・・・・・Common hole, 33.・・・・・・Low-temperature oxide film containing impurities. Departure diagram *2 diagram 2 diagrams 3 diagrams younger brother 4 diagrams *tako younger brother; diagram

Claims (1)

[Claims] 1. A process of forming an insulating film on the surface of a semiconductor substrate that does not allow diffusion conductivity type impurities to pass through, a process of removing the insulating film on areas where diffusion semiconductor layers of different conductivity types are to be formed side by side, and the resulting exposure. Directly depositing a low temperature oxide film containing impurities of one conductivity type on the surface and the insulating film, and forming a protective oxide film made of substantially the same material as the low temperature oxide film on the low temperature oxide film. After removing the protective oxide film and the low-temperature oxide film on the area where the diffusion semiconductor layer of the other conductivity type is to be formed, the semiconductor substrate is heated, and the diffusion semiconductor layer of the one conductivity type is removed from the low-temperature oxide film. A method for manufacturing an integrated circuit comprising the steps of directly diffusing impurities into the semiconductor substrate and directly diffusing impurities of the other conductivity type into the exposed surface of the predetermined area from which the protective oxide film and the low-temperature oxide film have been removed.