JPS6013310B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a semiconductor device in which a structure having a field effect transistor effect is applied to a thyristor structure.

FIG. 1 is a cross-sectional view showing the general structure of a conventional thyristor. In the figure, 1 is a P-type anode layer with a relatively high impurity concentration, 2 is an n-type base layer with a low impurity concentration, and 3 is a P-type anode layer. a base layer, 4 an n+ type emitter region, 5 an anode electrode,
6 is a cathode electrode, and 7 is a base electrode or gate electrode.

A first junction J, is formed between the P+ type anode layer 1 and the n-type base layer 2, and a second junction J2 is formed between the n-type base layer 2 and the P-type base layer 3. A third junction J3 is formed between the layer 3 and the n+ emitter layer 4, respectively. This structure is widely used, and a detailed explanation of its operation will be omitted. By the way, the thyristor shown in FIG. 1 has an n+ type emitter region and a P
The main current is controlled by forward biasing the third junction J3 with the shaped base layer 3. Therefore, since it has a positive temperature coefficient such that the main current increases as the junction temperature rises, current concentration occurs and there is a risk that the thyristor may be destroyed due to thermal runaway. In addition, there is a drawback that the operating speed of the conventional silis is extremely slow, and the main reason for this is that the blocking voltage (forward blocking voltage) is increased when a forward voltage is applied between the front electrode 6 and the cathode electrode 6. In order to increase the thickness of the P-type base layer 3 or increase the impurity concentration of the P-type base layer 3, "the depletion layer extending from the junction J2 into the P-type base layer 3 due to the forward voltage becomes the junction J3. This is because the depletion layer reaches the junction J3 and contacts the n-type emitter region 4, the anode electrode 5 and the cathode electrode 6 are connected by a low resistance layer. As a result, a large current will flow and the voltage blocking ability will be compromised.In this way, the P type base
Increasing the thickness of the carrier layer 3 or increasing its impurity concentration is achieved by applying a bottle bias voltage between the cathode electrode 6 and the gate electrode 7 so that the carrier injected into the junction J
2, or the arrival efficiency decreases, effectively reducing the arrival carrier density. This injected carrier reaches junction J2 and n
Holes are injected from the anode layer 1 into the n-type base layer 2 by entering the n-type base layer 2, and the holes pass through the n-type base layer 2 and through the junction J2, The process in which electrons are absorbed into the p-type base layer 3 and then injected from the nx-type emitter region 4 into the p-type base layer 3 is described as a junction J2.
Excess carriers are accumulated at both ends of the line, and the forward voltage blocking ability is lost. In this way, the P-type base layer 3 is made thicker or its impurity concentration is increased in order to make it conductive only after a gate current is passed through the gate electrode 7. Conventional thyristors have the drawback of extremely low operating speed, and applications such as high-speed inverters and regulators have been dominated by transistors.The object of the present invention is to eliminate the above-mentioned drawbacks of conventional thyristors. The purpose is to provide a thyristor that is thermally stable and capable of high-speed operation.

In order to achieve this object, the present invention is characterized in that a structure having a field effect transistor effect is applied to the thyristor structure.

The present invention will be described below with reference to the drawings. Figure 2 shows
FIG. 1 is a sectional view showing one embodiment of the present invention.

In FIG. 2, a P-type semiconductor region 8 is provided in a portion of the n-type base region 2 that is in contact with the P-type base layer 3 and does not face the ~nx-type emitter region 4, and this P-type semiconductor region 8 and h A junction J4 is formed between the semiconductor layer 2 and the semiconductor layer 2.
Here, the n+ type emitter region 4, the P type base layer 3, and the n type base layer 2 constitute the bipolar type transistor 100, and the portion of the n type base layer 2 in contact with the P type base layer 3 and the P type semiconductor The region 8 and the region of the n-type base layer 2 that is close to the P-type anode layer 1 refer to the field-effect transistor 101.
It consists of Therefore, the portion of the transistor shown in FIG. 2 excluding the P-type anode layer 1 is equivalent to a series connection of the bipolar transistor 100 and the field effect transistor 101, and the equivalent circuit shown in FIG. becomes.

FIG. 4 is a diagram showing the voltage/current characteristics of the region shown in this equivalent circuit. As can be seen from Figure 4, the voltage/current characteristics in the region corresponding to the equivalent circuit shown in Figure 3 are similar to those of a bipolar transistor, but the main current has a negative temperature characteristic. This characteristic differs from that of a simple bipolar transistor. Region 1 shown in FIG. 4 is a saturated region, where both the emitter-base junction J3 and the base-collector junction J2 are sufficiently biased, so the portion of the n-type base layer 2 sandwiched between the P-type semiconductor regions 8 The conductivity is modulated up to and therefore it can be considered that there is almost no control effect on the junction field effect transistor 101.

Therefore, the operation in this case is similar to that of a bipolar transistor, and the on-state voltage is also low. Next, in the active region region 0' in FIG. 4, the second junction J2 is sufficiently reverse biased, so the portion of the n-type base layer 2 sandwiched between the P-type semiconductor regions 8 becomes a depletion layer. There is.

In this state, in terms of the equivalent circuit shown in FIG. 3, the gate-source bias of the junction field effect transistor 101 is bipolar. It is controlled by the base-collector voltage of the transistor 100, and is driven in the same manner as a bipolar transistor, and its characteristics are those of a junction field effect transistor. In this case, the purpose of biasing the third junction J3 in the node direction is to change the base-collector voltage of the bipolar transistor 100, and not to directly control the main current. That is,
The main current is the base of this bipolar transistor 100.
It is controlled by the junction field effect transistor 101 which uses the collector voltage as a gate-source bias, and therefore exhibits a negative temperature coefficient in which the main current decreases as the junction temperature increases. Next, the area m in Fig. 4
In the cross-cut region, the bipolar transistor 10 is in an off state, and if the voltage increase rate of the junction field effect transistor 101 is r (10.mu.), it exhibits a withstand voltage of Vc8o.

Therefore, the collector emitter dusk breakdown voltage Vc8o of the nipolar transistor can be 1/(10 μm) of the required breakdown voltage, making it easy to improve the frequency characteristics of the bipolar transistor. The new structure described above is described below as “
It will be referred to as a gated transistor.

By adding a P+ type anode layer 1 to the surface of the n-type base layer 2, which corresponds to the collector layer of this gated transistor, opposite to the P-type base layer 3, negative temperature characteristics similar to those of the gated transistor described above can be achieved. You can get a thyristor that shows. Now, referring back to FIG. 2, the operation and characteristics of the semiconductor device according to the present invention will be described.

As mentioned above, the structure of FIG.
The equivalent circuit except for the part shown in FIG. 3 is as shown in FIG. Assuming that the voltage increase rate of the field effect transistor 101 is the peak, the breakdown voltage between the m-type base layer 2 and the barb-shaped emitter region 4 is given by (10r)VcEo. In this way, the breakdown voltage can be increased by (10 μm) times due to the field effect transistor action, so that even if the P-type base layer 3 is thin, a sufficiently high breakdown voltage can be obtained. This means that the P-type base layer 3 can be made sufficiently thinner than conventional thyristors, and therefore the moving speed of carriers passing through the P-type base layer 3 can be increased. Since the factors that limit the operating speed of the thyristor are removed, it becomes possible to obtain a thyristor that operates at high speed and has a high breakdown voltage. Furthermore, since the P-type semiconductor region 8 is connected to the gate electrode 7 with a low resistance, the propagation time constant CR of the input signal R can be made small, making it suitable for high-speed operation.

The P-type semiconductor region 8 can be formed in order to achieve a high breakdown voltage by selecting a region that satisfies the following equation, when the spacing is a secret.

Here, No is the impurity concentration in the n-type base layer 2, N^ is the impurity concentration in the p-type base layer 3, s is the dielectric constant of the semiconductor, q is the unit charge, and WB is the impurity concentration in the p-type base layer 3. It's the thickness. In this way, the thyristor having the gated transistor structure according to the present invention shown in FIG. 2 takes advantage of the thyristor's advantage of high voltage resistance while also having the advantages of the high-speed transistor. be.

Next, FIGS. 5 and 6 respectively show the second embodiment of this invention.
and FIG. 7 is a cross-sectional view showing the structure of a third embodiment.

Both embodiments are essentially the same as the first embodiment shown in FIG. 2, with the only difference being the shape of the portion of the P-type semiconductor region 8 existing within the P-type base layer 3. FIG. 7 is a cross-sectional view showing the structure of a fourth embodiment of the invention. In this embodiment, the P-type semiconductor layer 8 is embedded in the N-type base layer 2, and A lead electrode 9 of this P-type semiconductor layer 8 is provided, and this electrode 9 is electrically connected to the base electrode 7 through a connecting body 101. In terms of operation, this embodiment also has the same structure as that shown in FIG. There is no difference from the first embodiment shown.

Incidentally, in each of the embodiments, the n+ type emitter region 4 and the P type semiconductor region 8 are formed into stripes and are arranged at positions corresponding to the gaps so as not to overlap with each other, so that the current path is not obstructed. Control efficiency is also good.

Note that the P-type semiconductor region 8 may also be formed into a mesh shape. FIG. 8 is a diagram showing the voltage-current characteristics of a thyristor. In the figure, 1go, 1g, and 1 represent gate currents, IH represents a holding current, and region 1 represents a blocking state (region low represents a conductive state).

The device of the present invention has similar characteristics, but the only difference is that its temperature characteristics are negative. Furthermore, a fifth embodiment of the present invention will be described with reference to FIG.

FIG. 9a is a plan view, and FIG. 9b is a sectional view taken along the line b-IXb. This embodiment has "n-type emitter region heat in one connected structure without being divided,"
In addition, it has a structure having a region blade plate called a short-circuit emitter. It goes without saying that this embodiment also produces the same effects as the above-described apparatus of the present invention. Although each of the above embodiments describes a specific conductivity type configuration, it is obvious that the present invention can also be implemented in a configuration in which the P-type region is replaced with an n-type region, or the n-type region is replaced with a P-type region. be.

As detailed above, "According to the present invention, since a portion having a gated transistor structure is provided in the thyristor structure, a semiconductor device with good thermal stability and high speed and high breakdown voltage can be obtained." .

[Brief explanation of the drawing]

Fig. 2 is a sectional view showing a conventional thyristor, Fig. 2 is a sectional view showing the first embodiment of the present invention, Fig. 3 is an equivalent circuit diagram of a gated transistor, and Fig. 4 is an equivalent circuit diagram of a gated transistor. 6 is a sectional view showing the second embodiment of the present invention, FIG. 6 is a sectional view showing the third embodiment of the present invention, and FIG. 6 is a sectional view showing the fourth embodiment of the present invention. 8 are diagrams showing the voltage-current characteristics of the thyristor, and FIG. 9 is a sectional view showing the fifth embodiment of the present invention, and FIG.
Figure b is a sectional view. In the figure, 1 is the first semiconductor layer, 2 is the second semiconductor layer, 3 is the third semiconductor layer L, 4 is the fourth semiconductor region, 5
is one main electrode, 6 is the other main electrode, 7 is the control electrode, 8
is a fifth semiconductor region, and 10 is a conductive path. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2 Figure 3 Figure 8 Figure 4 Figure 5 Figure 6 Figure 7 Figure 9

Claims (1)

[Claims] 1. A first semiconductor layer having a first conductivity type and having a relatively high impurity concentration; a second semiconductor layer provided adjacent to the first semiconductor layer;
a second semiconductor layer with a low impurity concentration and having a conductivity type; a third semiconductor layer provided adjacent to the second semiconductor layer and having a first conductivity type; a fourth semiconductor region having a second conductivity type and having a high impurity concentration;
a fifth semiconductor region provided discretely at equal intervals in a direction parallel to the main surface of the semiconductor substrate to form a junction and connected to the third semiconductor layer directly or via a conductive path; one main electrode provided in the first semiconductor layer, the other main electrode provided in the fourth semiconductor region,
and a control electrode provided on the third semiconductor layer,
The gap between the two adjacent fifth semiconductor regions is 2a,
When the impurity concentration of the second semiconductor layer is No, the impurity concentration of the third semiconductor layer is N_A, and its thickness is W_B, the relationship between the interval, concentration, and thickness is N_D・a^2<N_A
- A semiconductor device characterized by satisfying W_B^2. 2. The semiconductor device according to claim 1, wherein the fifth semiconductor region is formed in a plurality of stripes. 3. The semiconductor device according to claim 2, wherein the fourth semiconductor region is provided at a position corresponding to a gap between each striped fifth semiconductor region. 4. The semiconductor device according to claim 1, wherein the fifth semiconductor region is formed in a mesh shape.