JPS6013376B2 - Grid stabilizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system stabilizing device, and more particularly to a system stabilizing device (hereinafter referred to as a PSS device) added to an automatic voltage regulator (hereinafter referred to as an AVR) of a synchronous machine.

The PSS device uses AVR to control the excitation of a synchronous machine that is operated in parallel to the power system so that its terminal voltage remains at a constant value, which reduces the braking force against electromechanical power fluctuations in the power system, including the synchronous machine. is not obtained and the stability deteriorates, so the AVR should be used with the rotor speed of the synchronous machine (hereinafter referred to as △), the frequency of the synchronous machine state voltage (hereinafter referred to as △F), and the input or output power of the synchronous machine ( (Hereafter referred to as △P) etc. are added as auxiliary signals, thereby increasing the braking force against power fluctuations and improving stability. In recent years, this system has attracted attention as one of the measures to improve the stability of large-capacity, long-distance power transmission. I've started to feel that way.

FIG. 1 shows a block diagram of such a conventional PSS device, in which 2 is a signal reset circuit, 4 is a phase compensation circuit, 6 is an amplifier circuit, and 8 is a limiter circuit.

In such a configuration, first, stabilizing signals such as △, △
When signals such as F and △P are detected by a detector (not shown), they are passed through a signal reset circuit 2 consisting of an incomplete differentiation circuit called a signal reset.The transfer function Gs of the signal reset circuit 2 is Gs. =TsR・S/(1
10TsT・S)...It can be expressed in the form (1).

However, TsR is a time constant and S is a Laplace operator. The role of the signal set circuit 2 is to transmit the frequency component (usually around 0.5 to 2 Hz) of the power fluctuation between the grid and the synchronous machine, but remove the slower frequency component below that and approximate it. This is to ensure that the stabilizing signal output is not biased in one direction in response to relatively slow changes, while at the same time making it a signal corresponding to the change from the steady value. This is followed by a phase compensation circuit 4 and an amplifier circuit 6, which serve to apply a stabilizing signal to the AVR at a phase effective against said power fluctuations. Finally, limiter circuit 8
This works to limit the output of the S device within a certain value and to suppress excessive changes in the terminal voltage of the synchronous machine. In the configuration as described above, let us now consider the case where the stabilization signal changes much more slowly than the frequency peak of normal power fluctuations.

Examples of such cases include cases where the grid frequency slowly decreases due to an imbalance in power supply and demand due to generator load shedding or grid failure, or cases where the output of generators is controlled in response to demand due to grid unloading. This can happen when water is injected into a pump-turbine that has started up at a pumped-storage power plant to start pumping water. When the signal used as a stabilizing signal changes continuously in one direction in this way, the output of the amplifier circuit 6 is biased in one direction, and the output of the limiter circuit 8 is continuously applied to the limiter. Become. Therefore, the synchronous machine terminal voltage is also biased in one direction from the reference value set by the AVR,
In the end, the voltage remains increased or decreased by the same amount as the set limit value of the limiter circuit 8. the result,
The field current and armature current of the synchronous machine may also exceed the rated values, and it is undesirable for this to continue for a long time. Furthermore, in this state where the PSS output is at its limit, the frequency components that dampen the power fluctuation are not transmitted, so the effect of the PSS is almost eliminated, and the stability of the system is therefore threatened. Second
The figure is an explanatory diagram showing, as an example, the response of a synchronous machine equipped with a ΔP signal only S device. In particular, during power generation operation of a generator motor in a pumped storage power plant, the generator output is increased far to the maximum, and approximately 1 It is an example of the state of response of the PSS device when the output is increased from no load to 90% load in minutes.

In other words, discarding the output change of the △P signal, the PSS output is caught by the limiter setting value VL, and this value is held while the output increases, and as a result, the synchronous machine terminal voltage drops by VL from the ASR setting value. His eyes widen in a state of confusion. In the conventional circuit configuration shown in FIG. 1, the following two methods can be considered to eliminate this problem.

That is, one is to shorten the signal reset time constant TsR and reduce the output of the MS device for slowly changing components, and the other is to narrow the limiter width of the PSS device to reduce the bias of the voltage. The key is to keep it small.

However, if TsR is selected to be small in order to have a sufficient effect of signal resetting as in the former method, it will also affect the phase characteristics of the frequency domain of fin dynamic spreading, which is expected to have a damping effect, and the stability under normal conditions will be affected. On the other hand, in the latter case, even if the voltage bias can be reduced, it does not contribute at all to stability when slow unidirectional changes continue, and even under normal conditions. A small disturbance causes new problems such as the sheath S output exceeding the limit and reducing its contribution to stability.

Figure 3 is a characteristic diagram showing an example of calculating the dynamic stability limit for a certain system and synchronous machine, where A is the stability limit in the case of constant excitation, B is the stability limit in the case of AVR only, and C is the stability limit for AVR.
When signal system stabilization is added, the stability limit when the signal reset time constant TsR is set to 3 seconds, D is the same as in case C, and T8R is set to 0. These indicate the stability limits when the muscle steps are set, and in both cases, the inside of the curve is the stable area.

Incidentally, P stands for electric power, Q stands for reactive power, and et stands for terminal voltage. As is clear from Figure 3,
With AVR alone, the braking effect is reduced and the stable region becomes narrower than in the case of constant excitation.Adding an appropriate spot S widens the stable region, and decreasing the signal reset time constant TsR makes the stable region narrower than in the case of constant excitation. The effect decreases and the stable region does not expand much.

On the other hand, if the load increases continuously and uniformly from ambient to about the rated load in about 1 minute, the above example will be used to suppress the voltage deviation due to the deviation of the PSS output to about 3%. In this case, the signal reset time constant TsR is set to 0.
It is necessary to set it to the level of mirror sand, and from the viewpoint of stability under normal conditions, it is necessary to set it at a considerable sacrifice of stability.

Therefore, the object of the present invention is to eliminate the drawbacks of the above-mentioned prior art and
An object of the present invention is to provide a system stabilization (PSS) device that can enhance the stabilizing effect even under special disturbances and realize a more stable control system.

More specifically, the present invention provides a state in which when the stabilization signal continuously changes slowly in one direction, the PSS output is biased in one direction and remains biased for a long time from the set value by the synchronous machine terminal voltage AVR. PS due to the limiter on the output of
This invention provides a new system stabilization (S) device that prevents the S effect from being weakened and enhances the PSS effect.

FIG. 4 shows a block diagram of a PSS device according to an embodiment of the present invention, in which 2-1 and 2-2 are the first
, the second signal set circuit 10 is a bell detection circuit, and 12 is a bias circuit that adds a bias to the first signal set circuit 2-1. In this configuration, the input signal is now constant. When the voltage changes continuously in the direction, a steady voltage corresponding to the speed of change appears at the outputs of the first and second signal set circuits 2-1 and 2-2.

The level detection circuit 10 is connected to this second signal set circuit 2.
-2 exceeds a predetermined constant value for a certain period of time or more, the bias input is added from the bias circuit 12 to the first signal set circuit 2-1 at a constant speed. Change in the opposite direction to the stabilization signal input.
With such a configuration, even if the stabilizing signal input changes continuously in one direction and a steady output appears in the signal set circuit, this is suppressed by the change in bias and the first signal set circuit 2' The output of PS is suppressed and
The S output is suppressed, and therefore the inconvenience that the PSS output is biased towards the set limit value of the limiter circuit 8 is eliminated.
Furthermore, even when the input changes continuously in one direction, the system fluctuation components contained therein are transmitted to the subsequent circuits with almost no influence because the bias change selection is kept constant. Therefore, the original operation of the Kamo S device is not adversely affected. Of course, even in the configuration shown in FIG. 4, if the bias change speed from the bias circuit 12 is large, there will be an adverse effect, but this is not a particular problem because an appropriate value can be selected as the actual bias change speed. .

In other words, when the stabilizing signal input is a △P signal, the signal change speed when it changes continuously in a certain direction is a maximum of 90%/min (however, 100% is the synchronous machine rated load), that is, about 1 cent/sec. It is.

On the other hand, the power fluctuation that occurs between the grid and the synchronous machine is usually 0.5
Since it is from Hz to 2Hz, considering the case of 0.5Hz, this can be expressed as t (where A is the amplitude of the oscillation, and the time to t' is in seconds), and the rate of change is Awcos t/
seconds, and the maximum rate of change is A/second. Therefore, if there is a fluctuation of 1' cents of the rated power of the synchronous machine, the signal change rate of that component is equal to percent/second, which is greater than the change rate of 1.5 percent/second in a constant direction, and the signal remains constant. Even if the bias change of 1.5 cent/second, which is necessary to cancel out all the continuous change in direction by bias change, is actually performed when there is no continuous change in a certain direction, it will not have a large effect on the oscillation component. In the block diagram of FIG. 4, FIG. 5 shows a bell detection circuit 10, a bias circuit 12, and a signal set circuit 2-1 which can receive both a normal signal and a bias, which are not particularly important in terms of the circuit configuration of the present invention. This is a circuit configuration diagram showing the specific configuration of OAI to OA6.
is an operational amplifier, RI~R13 is a resistor, DI~D2 is a diode, ZDI~■2 is a Jenner diode, RYI
~RY2 is a relay, RHI~RH4 is a variable resistor, QI
~Q2 is a transistor, CI~C4 is a capacitor, Vp
is a positive power supply and VN is a negative power supply.

Note that illustration of the power supply circuits of the operational amplifiers OAI to OA6 is omitted. In this configuration, the operational amplifiers OAI to OA3 and their peripheral circuits constitute a signal reset circuit 2-1, and V, is the input of the signal reset circuit 2-1, and V is the input of the signal reset circuit 2-1.
4 is a bias that can be changed at a constant speed, and V2 is the output of the signal reset circuit 2-1.

Paying attention to the configuration of the signal reset circuit 2-1, the relationships among the signals V, , V2, and V4 are as follows.

V3 is the output of the second signal set circuit 2-1;
If V3 is negative, if V3 is smaller than the value set by variable resistor RHI, that is, if its absolute value is large, operational amplifier O
As the output of A4 increases, the Jenner diode ZDI
When the voltage exceeds , transistor QI becomes conductive and relay R
YI is excited.

On the other hand, when the value of V3 becomes larger than the set value, the output of A4 to the operational amplifier decreases, and when the value becomes less than the voltage of the Zener diode ZDI, the transistor QI becomes non-conductive and the relay RYI is restored. When V3 is positive, operational amplifier OA is activated based on the value set by variable resistor RH2.
5. Relay RY2 operates in the same way. That is, the circuits of operational amplifiers OA4 and OA5 and relays RY1 and RY2 are
3. The alarm is detected within a time limit. On the other hand, operational amplifier OA6 and capacitor C4 constitute an integrating circuit,
When the relay RYI operates, the bias V4 which is the output of the bias circuit 12 increases at a constant speed, and when the relay RY2 operates, the bias V4 decreases at a constant speed.

That is, although the bias circuit 12 can change the bias V4 at a constant speed, the speed of change can be adjusted by the variable resistors RH3 and RH4. Next, the operation when the configuration shown in FIGS. 4 and 5 is applied to the example shown in FIG. 3 will be described.

Incidentally, the time constant of the first signal reset circuit 2-1 is 3 seconds, and the total gain as a PSS device is 3 times. On the other hand, the time constant of the second signal reset circuit 2-2 is also set to 3 seconds, and the level detector 10 receiving its output operates at a rate of 0.5%/second input to the signal reset circuit 2-2. When the level detector 10 operates, the input to the first signal reset circuit 2-1 becomes 1.
Set to change in percent/second. The third point is that this setting has sufficient effect for normal PSS operation.
This is as explained in the figure. On the other hand, to explain the case where the load changes continuously in one direction, the load is 1. Since the bell detector 10 is operated and the bias is changed by 1%/sec, the equivalent input to 2-1 in the first signal reset circuit is 0.0%/sec.
cent/second, and the steady output of the Ore S device is 4.5
percentage (0.5 percent/second x 3 seconds x 3 times). When the load change rate is 1%/second, it just cancels out the bias change, and the steady output of the S-device is 0.
” However, when the load change rate is slightly larger than 0.5 percent seconds, the level detector 10 operates, and the bias change is approximately 0.5 percent seconds too large, causing PSS to change in the direction of the bias change. The steady output of the device is 4
．． Free cent will appear. Also, the load change speed is 0
．． Since no bias change occurs when the time is smaller than Fugu centnoseconds, the steady output of the PSS device becomes a maximum of 4.6 centnoseconds. That is, when the load changes continuously in one direction at a rate of 1.5%/second or less, the steady output of the Kamo S device is 4.
．． It will be less than 5 cents. If it is desired to further reduce the MS steady output when the load changes continuously in one direction, it can be achieved by providing a plurality of level detectors and providing a plurality of bias change speeds corresponding to the levels.

For example, in the previous example, level detection is 0.3%/sec.
0. The bias is set to 0.0 cents/second when the level is detected to be 0.3 cents/second or more. &g cents/sec, 0.9f-
When the level is detected to be higher than cents/second, the bias is changed at a rate of 1.2%/second, thereby increasing the continuous change rate of the equivalent input to the signal reset circuit to a maximum of 0.1%/second. It is possible to suppress the steady output of the PSS device to a maximum of 2.7%. As described above, according to the present invention, it is possible to obtain a prison S device that can fully exhibit the effect of PSS in various operating conditions of a synchronous machine and can greatly contribute to improving stability. And its practical effects are great.

In the above embodiment, the signal flow in the circuit configuration of the PSS device is illustrated as a signal reset circuit, a phase compensation circuit, an amplifier circuit, and a limiter circuit.
Even if the H order of the signal reset circuit, phase compensation circuit, and amplifier circuit is replaced, the gist of the present invention does not change.

Furthermore, in the case of physical circuit wiring, it is often possible to omit a part of the circuit configuration, and for example, when using the ΔP signal, phase compensation is often not required. Furthermore, there are cases in which a part of the circuit configuration is constituted by one circuit and cannot be considered separately; for example, there are cases in which a thick circuit and a transmitter circuit are integrated. However, changes in the details of the circuit configuration do not particularly change the gist of the invention and do not impede the implementation of the invention.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional system stabilization device, Figure 2 is an explanatory diagram showing the response of a synchronous machine equipped with a system stabilization device for output power (△P) signal, and Figure 3 is synchronized with a certain system. 4 is a block diagram of a system stabilizing device according to an embodiment of the present invention, and FIG. 5 is a block diagram of the circuit of the present invention in the block diagram of FIG. 4. FIG. 2 is a circuit configuration diagram showing a specific configuration of an important circuit in the configuration. 2, 2-1, 2-2...Signal reset circuit, 4...
Phase compensation circuit, 6... amplifier circuit, 8... limiter circuit, 10... level detection circuit, 12... bias circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 The rotational speed of the synchronous machine, the frequency of the terminal voltage, electrical input/output, signals equivalent to these, or a combination thereof are used as stabilizing inputs, and are applied to the automatic voltage regulator of the synchronous machine connected to the power grid to control the grid. In a system stabilizing device that performs stabilization, first and second imperfect differentiating circuits that imperfectly differentiate the stabilizing input, and at least one setting of an output level of the second imperfect differentiating circuit. a level detection circuit that compares the values; a bias circuit that adds a bias signal that changes in the opposite direction to the input signal to the input of the first incomplete differentiation circuit based on the output of the level detection circuit; A system stabilizing device comprising: an output circuit that outputs the output signal of the incomplete differentiation circuit No. 1 to an automatic voltage regulator.