JPS6013497B2 - How to diagnose cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for diagnosing a cache memory that temporarily stores copy data in a main memory.

The main memory of a computer stores various instructions and data (hereinafter simply referred to as data), and a desired one is accessed and used by an address signal. Data that has been used is often used again immediately after it is used, but it is time consuming and uneconomical to read the data from a large-capacity, low-speed main storage memory each time it is used. Therefore, the retrieved data is stored in a high-speed memory called a cache memory, and if the data to be used next is the same as the stored data, it is immediately retrieved from the cache memory and used. To explain this with a drawing, 10 is a cache memory, and data section 1 stores data accessed by address information ADD and retrieved from main memory memory MM.
Written to 0b.

Assuming that the upper bit group of address ADD is A, and the lower bit group is A2, the cache memory 10 is stored at lower address A2.
accessed by In other words, the cache memory 10 has 2n addresses, where n is the number of bits of the lower address A2, and data retrieved from the main memory MM is sent to the storage area of the cache memory 10 specified by the lower address A2. It is written together with the upper address A.
The storage area is divided into an address section 10a and a data section 10b, and the upper bit AI is written to 10a. There are two types of cache memory, one in which one cache memory is provided, and two in the illustrated embodiment, with 20 being the other cache memory. The configuration is the same for both. When data is extracted, one of the data addresses A, A2 is led to one input terminal of the comparator 12, and the other A2
is guided to the cache memory 10 and accessed. Of the stored contents of the memo IJ10 read by this access, those in the address section 10a are guided to the other input terminal of the comparator 12, and those in the data section 10b are guided to the selector 16. The comparator 12 compares the upper address bits input to the re-input terminal, and if they match, a hit output t is generated. This output Hit is input to the selector 16, which switches the selector from the main memory MM to the cache memory 0 side, and sends the argument output of the data section 10b of the cache memory to the data bus DB. If the comparison result in the comparator 12 does not match, no hit output is generated, and the selector 16 is tilted toward the main memory MM and sends the read output of the MM to the data bus DB. In this way, if desired data is present in the cache memory, it is immediately retrieved and used; if not, it is retrieved from the main memory and used, thereby speeding up and improving access efficiency. If the latter is not present, the data is written via the selector 24 and the upper address is written via line 1 into the data section and address section of the cache memory in preparation for the next use. Even if the other cache memory 201 is used, the manner of use is the same.

There are various methods for operating the memories 0 and 20. Or, it is possible, but in any case, it is used by switching, and when writing, the same data is not written in both memo files. By the way, as is clear from the above description, such a cache memory cannot be accessed by itself to read its stored contents.

In other words, the lower address alone is not enough to access this memory (this is sufficient for accessing ordinary memory),
It also uses the upper address A, which is written in the address section of the cache memory (this is generally written randomly to the address of memory 10, and which address is written to each address). (I don't know if A is written like this). Therefore, if you try to read the contents of an address in memory 0,
The upper address A, (this is A,
(2m bits, where m is the number of bits), and accesses must be made 2m times. Memory diagnosis involves writing predetermined data to an arbitrary address and trying to submit it, but the method described above is extremely troublesome.
Furthermore, it is impossible to write desired data to the address section Ioa. The present invention aims to improve this problem and facilitate the diagnosis of the cache memory by making it possible to arbitrarily read and write to the cache memory in the same way as normal memory.

In the present invention, the data extracted from the main memory is written into the address section and the data section of the storage area selected by the lower bits of the address of the data, together with the upper bits of the address. is accessed with the lower bits of the address output for discussion, and when the upper bits of the output storage area match the upper bits of the address, the data in the storage area is derived from the hit output generated at that time. In the cache memory diagnosis method,
In the diagnostic mode, a signal equivalent to the bit output and a switching signal between the address section and the data section are generated, and the address section and data section of the cache memory can be selected using only the lower bits, and the desired write data can be written. The present invention is characterized in that it is possible to selectively write into the address field and the data field, and this will be explained next with reference to an embodiment. As shown in the drawings, the present invention provides a control register 18, which outputs bits CACC, SELT and ADR.

Bit CACC is input to an OR gate 14 which passes the hit outputs of comparators 12 and 22, so that this bit is "1".
When this happens, it is equivalent to a hit. The read outputs of the address and data sections of the cache memories 10 and 20 are each led to a selector 16, and one of these four blocks of data (usually one word) is sent to the bit ADR.
and SELT. In other words, ADR selects the address part or the data part (for example, "1" selects the former, "0"
(to select the latter), SELT selects memory 10 or 20. 24 is a write data WD selector, CA
When CC becomes “1”, diagnostic mode is turned off and AD
The 2 bits R and SELT switch the transfer destination of the data WD to the address section or data section of the memory 10 or 20.

This device uses bit C when diagnosing cache memory.
Set MCC to “1”, in other words, C of control register 18
Write "1" to the ACC bit position, and set bits SELT and ADR to "1" or "0" depending on which part of the cache memory is to be diagnosed.

In this example, both SELT and ADR are set to “0” and memory 1
Assume that the address section 10a of 0 is selected. In this state, the memories 10 and 20 can be accessed using the lower address, and the selected output that was in 10a can be taken out through the selector 16. In this way, the contents stored in the address section 10a can be checked. Data section 10b
If you want to diagnose the storage contents of , you can set bit ADR to "1" in this example. The others are also on the same plane. For writing, send a write signal (write enable) to the memories 10 and 201 to set them to write mode, and set the write data WD to selector 2.
4 to select and send to a desired memory portion, and select a storage area with lower address A2 and write to that area.

In this way, according to this circuit, data can be written to and discussed in the cache memory in the same way as normal memory, and diagnosis can be performed quickly.
It can be done efficiently. Note that the write data used at this time is so-called data and not a command. If you make it a command, it will cause the CP to pile up and malfunction. In the diagnostic mode, the information written to the address section of the cache memory is generally not an upper address but predetermined data given through the selector 24, so in this case path 1 is turned off.

The switch 26 performs this control and is turned on and off by an appropriate signal S. Note that this switch 26 also turns off the paths of the upper and lower addresses A leading to the comparators 12 and 22, but this does not pose any particular problem since the upper and lower addresses are unnecessary in the diagnostic mode. As explained above, according to the present invention, data can be written to and discussed in a cache memory in the same manner as a normal memory, and is extremely effective in diagnosing the cache memory.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of the invention. In the figure, 101 is the cache memory, 10a is its address section, 10b is the data section, Hit is the hit output, and CACC
is a signal equivalent to Hit; "ADR is an address section/data section separation signal.

Claims (1)

[Claims] 1 Data read from the main memory is written to the address and data parts of the storage area selected by the lower bits of the address of the data, together with the higher bits of the address, and when read, is output for the reading. In a diagnostic method for a cache memory, data in the storage area is derived from a hit output generated at that time when the storage area is accessed using the lower bits of the address and the upper bits of the read storage area match the upper bits of the address. Then, a signal equivalent to the hit output and a switching signal between the address section and the data section are generated, and the address section and data section of the cache memory can be selectively read using only the lower bits, and the desired write data can be transferred to the address. A method for diagnosing a cache memory characterized by enabling selective writing to a data part and a data part.