JPS6013568B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFT circuit for a television receiver having a digital electronic channel selection device.

If the video intermediate frequency and audio intermediate frequency of the video intermediate frequency amplifier of a television receiver are fp and fs, the frequency characteristics of the video intermediate frequency amplifier are shown as shown in FIG. 1A.

Further, the AFT voltage is obtained by frequency discriminating the video intermediate frequency signal, and the discrimination characteristic of the frequency discrimination circuit is as shown in FIG. 1B. In other words, this discrimination characteristic is centered around the frequency fp, the upper side is a band up to the frequency (fp 11.8 MHz) due to the adjacent trap, and the lower side is the band for the audio intermediate frequency signal of the adjacent channel. Preventing AFT voltage from forming and
For balance with the upper side, the frequency (fp-1.9M
Hz). Therefore, the band (fp±
1.8MHz) is the AFT pull-in range. However, the AFT frequency discrimination circuit responds not only to the video intermediate frequency signal but also to the audio intermediate frequency signal of the same channel, so it is necessary to change the local oscillation frequency (receiving frequency) of the tuner. In this case, an AFT voltage Vs is obtained as shown in FIG.

Here, the voltage VSp is the AFT voltage obtained by the video intermediate frequency signal, the voltage Vss is the AFT voltage obtained by the audio intermediate frequency signal, and Fp and Fs are the intermediate frequencies (carrier frequencies) of the video and audio intermediate frequency signals. It is. In this way, even with the audio intermediate frequency signal, A
When the FT voltage Vs (Vss) is obtained, this A
The AFT circuit may also operate due to the FT voltage Vs, and the AFT may become locked to the audio intermediate frequency signal. This invention attempts to solve these problems.

Now, considering the output of the synchronization separation circuit, it changes as shown in FIG. 3 in response to changes in the local oscillation frequency.

That is, when the local oscillation frequency is the normal frequency or lower than this (normally tuned or detuned to the lower side), the normal horizontal synchronizing pulse (complex A synchronizing pulse) Ph is obtained, but its average voltage Va (shown by a chain line) is Va:Vpx, which is a small value.

However, when the local oscillation frequency is high (when the frequency is tuned higher), as shown in FIG. 3B, the pulse Ph comes to include noise Nn, and its average voltage Va becomes large.

When the local oscillation frequency is higher, as shown in FIG. 3C, there is almost only noise Nn, and the average voltage Va becomes even larger.

The present invention utilizes this change in the average voltage Va to prevent the AFT from malfunctioning with respect to the audio intermediate frequency signal.

An example of this will be explained below.

In the example below, the AFT pull-in range is widened because the AFT does not malfunction with respect to the audio intermediate frequency signal. In FIG. 5, reference numeral 1 indicates an electronically tuned tuner, which has a variable capacitance diode, for example, as a resonant element in each tuning circuit, and when a tuning voltage Vc, which will be described later, is supplied to this, the level of the voltage Vc is changed. channels that are compatible with this.

In addition, 2 is a video intermediate frequency amplifier, 3 is a video detection circuit, and 4 is a video intermediate frequency amplifier.
is a video amplifier, and 5 is a picture tube. Furthermore, 10 indicates a tuning control circuit that forms a tuning voltage Vc, in which the tuning voltage Vc corresponding to the broadcast channel is preset in the state of a digital code, and when receiving, the preset tuning voltage Vc is preset in the state of a digital code. The desired channel is selected from the voltages Vc.

That is, 11 is a channel memory, which has, for example, lq-specific addresses corresponding to the number of receivable channels, and each address can store the tuning voltage Vc corresponding to that channel in the state of a digital code Ai. , and can also be read out. Note that this memory 11 is a nonvolatile memory that retains its contents even if the power is turned off. Further, 12 is an addressing circuit, which includes channel selection switches S, -S,. are connected, and switches S, ~S,. When you operate one of the
A corresponding address in memory 11 is designated. moreover,
13 is a reversible counter that forms a channel selection code Ai at the time of presetting, 14 is an oscillation circuit that generates a pulse Po that is input to the counter, 15 is a memory control circuit, and a mode switch Sm'. 11 is switched between a write mode (preset mode) and a read mode (channel selection mode). Further, 16 is a write pulse forming circuit, 17 is a reset circuit, and 18 is a D-A that converts the channel selection code ~ into the channel selection voltage Vc.
Converter, Su is F.

A switch Sd is a switch that sweeps the reception frequency in the upward direction when setting the IJ, and a switch Sd similarly sweeps the reception frequency in the downward direction. Further, the circuits 21 to 23 form an AFT command voltage VreVd.

That is, a video intermediate frequency signal is taken out from the intermediate frequency amplifier 2 and falsely fed to the frequency discrimination circuit 22 through the bandpass amplifier 21. In this case, this discrimination circuit 2
For example, as shown in FIG. 1C, the discrimination characteristic of No. 2 is a band from about frequency (fp - 3 MHz) to about frequency (fp - 11.9M ratio). Therefore, from the discrimination scheme 22,
An AFT voltage ys that changes as shown in FIG. 4A with respect to a change in the local oscillation frequency is extracted. Then, this voltage Vs is supplied to the shaping circuit 23, and AFT command voltages yu, Vd as shown in FIGS. 4B and 4C, for example, are formed using the levels V, , V2 as threshold levels. In other words, with respect to the normal tuning point fp, the voltage Vu' becomes "1" in the frequency range from (approximately fp - Hiyaz) to (fp - 5 Hz), and becomes "0" in the other frequency ranges. And, the voltage Vd changes from (fp about 150k) to almost (
It becomes "1" in the frequency range of fp+1.8M), and becomes "0" in the frequency range other than this. Note that this (fp±
50kHz) is the normal tuning range. The command voltage Vd is used as is, but the command voltage Vu is corrected in order to eliminate malfunction of the AFT due to the audio intermediate frequency signal.

That is, the video signal from the detection circuit 3 is transmitted to the synchronous separation circuit 2.
5 and the horizontal tuning pulse (composite synchronization pulse) Ph
is taken out, and this pulse Ph is supplied to the integrating circuit 26 and made into an average voltage Va. In this case, the pulse Ph and the voltage Va change as explained in FIG. 3 with respect to the change in the local oscillation frequency, so if the change in the voltage Va is shown in FIG. 4, it will be as shown in FIG. 4D. Become. This voltage Va is then supplied to the transistor 27 to level V3.
is inverted with the threshold level as a signal Q7 as shown in FIG. 4E, and this signal Q7 and the command voltage V
u is supplied to an AND circuit 501 to obtain a corrected command voltage Vv as shown in FIG. 4F, that is, an AFT command voltage Vv obtained only for the video intermediate frequency signal.

Further, 31 to 37 are logic circuits, which supply the pulse Po from the oscillation circuit 14 to the counter 13 as an addition input or a subtraction input when the switch Su or Sd is turned on at the time of presetting.

Further, 41 to 43 are rising trigger type RS flip-flop circuits, 45 to 47 are pulse forming circuits (delay circuits) that form an output pulse after a specified time when there is an input, and 49 is a detection circuit. In the example, switches S, ~S, are connected to the addressing circuit 12.

It is designed to detect when any of these are manipulated. Further, 51 to 59 are logic circuits. Then, the channel selection operation is performed by these circuits 41 to 59. That is, first, when presetting a broadcast channel, the mode switch Sm is switched to the preset side contact P. Then, the counter 13 is reset by the reset circuit 17, and the memory 11 is placed in the write mode by the control circuit 15. Therefore, switch S, is turned on, and then switch Su is turned on.

Then, by turning on the switch S, the designated circuit 1
2, the corresponding address of the memory 11 is designated. Furthermore, by turning on the switch Su, the output of the inverter 31 becomes "1", and therefore, the pulse Po from the oscillation circuit 14 is supplied as an addition input to the counter 13 through the AND circuit 32 and the OR circuit 33.
The contents of counter 3 start from [00...0] and increase sequentially. Since the contents of this counter 13 are supplied to the DA converter 18, a channel selection voltage Vc corresponding to the code needle of the counter 13 is formed, and this voltage Vc is caused by the contents of the counter 13 being [1]. )
Each time it increases, it increases by ΔV, so the reception frequency of the tuner 1 gradually increases, and the reception frequency is reduced. Therefore, in the Kanto region, when the broadcast of the first channel can be received, the switch Su is turned off.

At this time, if the switch Sd is turned on as necessary, the pulse P from the oscillation circuit 14 is generated by the output of the inverter 34.
o is connected to the memory 1 through an AND circuit 35 and an OR circuit 36.
1 as a subtractive input, and therefore the tuning voltage V
Since c decreases, fine tuning of the receiving frequency can be achieved. Then, when the switch Su (or Sd) is turned off, the output of the AND circuit 37 becomes "1", so a write pulse is formed in the forming circuit 16, and this pulse is passed through the control circuit 15 to the memory 1. 1
The address of the memory 11 specified by the switch S is erased, and the contents of the counter 13 at the time when this switch Su (or Sd) is turned off are changed to the address specified by the memory 11. will be written to.

Therefore, the tuning code A corresponding to the tuning voltage Vc of the first channel is written to the address of the memory 11 specified by the switch S. Next, switch S2
, and then turn on the switch Su.

Then, another corresponding address in the memory 11 is specified by the switch S2, and the contents of the power counter 13 are further increased by turning on the switch Su. Accordingly, the channel selection voltage Vc is further increased and the reception is stopped. The frequency sweep continues. Therefore, when the third channel can be received, by turning off the switch Su, the third channel selection voltage Vc is written in the address corresponding to the switch S2 in the memory 11 in the state of the selection code N. Thereafter, the channel selection voltage Vc of the broadcast channel can be preset in the memory 11 in the same manner.

On the other hand, when receiving a broadcast, the switch Sm is switched to the reception side contact R, and among the switches S, -S, and o, the one of the desired channel, for example, the switch S, is turned on. Then, the control circuit 15 sets the memory 11 to read mode, and the memory 11 corresponding to the switch S,
address is specified. Further, the detection circuit 49 detects that the switch S is turned on, and as shown in FIG. Pulse P
9 is supplied to the memory 11 as a read pulse through the OR circuit 58 and further through the control circuit 15. Therefore, the tuning code A at the address specified by the switch S is read out, and this code A is supplied to the counter 13 and its contents are set to A. The signal is converted into a channel selection voltage Vc. , Therefore, from time t2, which is slightly delayed from time t,
It becomes the state where the first channel is selected. And in this case,
Strictly speaking, the intermediate frequency Fp of the video intermediate frequency signal for the tuning state of the first channel is (i) frequency (fp+
1.9M ratio) or more (ii} From frequency fp to (f
p+1.9M ratio) (iii) Frequency (fp
- ice elbow z) to fp is one of the cases below the GW frequency (fp - Obata z), and these (i} ~ 0
The following AFT is performed depending on the case.

(i} When the threshold voltage is higher than the frequency (fp 11.8M), when the threshold detection pulse P9 is obtained, this pulse P9 is supplied to the set terminal S of the flip-flop circuit 41, so its output Q, is as shown in FIG. As shown in B, from time t, “
Since the pulse P9 is supplied to the reset terminal R of the flip-flop circuit 42 through the OR circuit 59, its output 2 becomes ``0'' as shown in FIG. 6C. Furthermore, since the pulse P9 is supplied to the set terminal S of the flip-flop circuit 43, its output Q3 becomes "1" from the time point t, as shown in FIG. Also, Q,,Q
2=“0” and Q=“1”).

Then, when the time comes, the first channel is selected.

In the case of this river, the AFT voltage Vs cannot be obtained, so
As shown in FIGS. 6E and F, Vv and Vd="0". Since the pulse P8 at the time point P8 is also selected to the forming circuit 45, at the time point t3 when a predetermined period of time 5 has elapsed from the time point t, the forming circuit 45 outputs a signal as shown in FIG. 6G. Pulse P5 is extracted.

Then, since the moment Q is "1", this pulse P
5 is connected to the flip-flop circuit 4 through an AND circuit 52.
2 set terminal S, Q2; “1
”. Therefore, after time t3, Q2, Q = “1”
Therefore, the output pulse Po of the oscillation circuit 14 is supplied to the counter 13 as a subtraction input through the AND circuit 55 and the OR circuits 56 and 36 as shown in FIG.
be provided.

Therefore, from this point onwards, the local oscillation frequency for the first channel gradually decreases. Then, as the local oscillation frequency decreases, the video intermediate frequency Fp also decreases, and when the current video intermediate frequency Fp decreases to the frequency (fp + 11.9M ratio), a negative AFT voltage Vs is obtained, and Vd = "1".
” becomes.

Then, this voltage Vd is supplied to the reset state R of the flip-flop circuit 41 through the OR circuit 51, and is further supplied to the reset terminal R of the flip-flop circuit 42 through the OR circuit 59, so that from time t4, Q, . Q23 becomes “1”. Therefore, oscillation circuit 1 4
The output pulse Po is no longer supplied to the counter 13 through the AND circuit 55 from time t4. However, at this point, as Vd=“1”, Q3=“
1'', the pulse Po is output from the AND circuit 54 at the time.
counter 1 through OR circuits 56 and 36.
3 as a subtraction input. Therefore, even after time t4, the video intermediate frequency Fp continues to decrease. Then, at time t5, the video intermediate frequency Fp becomes the frequency (fp15
0kHz), Vd becomes "0".

Therefore, the pulse Po that had been supplied to the counter 13 through the AND circuit 54 is no longer supplied after time t5. In this state, the video intermediate frequency F is within the band from frequency (fp - about 50k) to (fp +50 kHz), and therefore it is correctly tuned to the first channel. 'ii) Between frequencies fp and (fp 11.8M) In this case, the first
When a channel is selected, Vd becomes "1" immediately, so that the operation after the point in time (i) is performed as shown in FIG.

That is, at this point, Vd=“1”, so Q,=“0”, and the pulse Po is supplied as a subtraction input to the counter 13 through the AND circuit 54.
The video intermediate frequency Fp is decreasing. And time t5
When the video intermediate frequency Fp drops to the frequency (fp + 50 kHz), Vd becomes "0" and the pulse Po is no longer supplied to the counter 13.

Therefore, after time t5, it is correctly tuned to the first channel. Incidentally, after a period ↑5 from the time point et al., a pulse P5 is obtained from the forming circuit 45, but at this time, Q,
Since Q2="0", Q2="0" continues.

(iii) Case between frequency (fp - Obata z) and fp In this case, when the first channel is selected at time t2, contrary to case (ii), as shown in FIG. To,
Vv=“1”. Therefore, the pulse Po is supplied as an addition input to the counter 13 through the AND circuit 53,
The video intermediate frequency Fp increases. And time t6
When the video intermediate frequency Fp reaches the frequency (fp-50kHz), Vv becomes "1" and the pulse Po becomes the counter 1.
3, so that from now on it is correctly tuned to the first channel. And these (i) ~
In the case of the video intermediate frequency F at time t5 or tG.
When p falls within the frequency band (FP master 50k generation), from then on, Q3 = "1", so Vv or Vd =
If it becomes "1", the pulse Po is supplied to the counter 13 through the AND circuit 53 or 54 as an addition input or a subtraction input. Therefore, the video intermediate frequency Fp is the frequency (
fp±50k), i.e., A
FT is performed. OW If the frequency is below (fp-autumn mz) In this case, it is outside the AFT pull-in range, so A
FT is not performed.

That is, although the first channel is received at time t2,
As shown in FIG. 9, since Vv, Vd="0", [i
}, a pitch pulse P5 is obtained at the moment, and the video intermediate frequency Fp decreases and becomes vertically tuned. Then, at time t7 (that is, before the AFT voltage Vs can be obtained by the audio intermediate frequency signal of the adjacent broadcast channel), as shown in FIG.
Since the pulse A is taken out from 6 and supplied to the reset state R of the flip-flop circuit 43 through the AND circuit 57, Q3 becomes "0" from time t7, and the counter 13 stops counting.

At the same time, the pulse P6 passes from the AND circuit 57 to the OR circuit 58, and further passes through the control circuit 15 to the memory 1.
1 as a read pulse.

Therefore, at some point, the contents of memory 11 are again stored in counter 1.
Since the content of the counter 13 is made equal to the content at time t, the state of receiving the first channel is resumed from time b. However, even in this case, the video intermediate frequency Fp is lower than the frequency (fp - insect M). Further, the pulse P6 is transmitted to the forming circuit 4 through the AND output 57.
As shown in FIG. 9J, the reset pulse P7 is taken out a little later than the time t7, and this pulse P7 is passed to the OR circuit 59 and reset to the reset terminal R of the flip-flop circuit 42. and at time t8
After that, Q2: becomes ``0''. In other words, in the case of 0M, when the first channel is selected, the downward sweep is performed only once, but it returns to the video intermediate frequency Fp at the time of channel selection, and Thereafter, the operation stops in that state and AFT is not performed.

Tuning and AFT are performed as described above, but in this case, according to the present invention, the output Ph of the synchronization separation circuit 25
By using the changes in the average voltage ya of Nn and Nn, as shown in FIG.
Since the FT command voltage Vv is obtained, the AFT does not lock to the audio intermediate frequency signal. In addition, for the audio intermediate frequency signal, the AFT command voltage yv for upward sweep is
is not formed, the discrimination characteristic of the discrimination circuit 22 can be expanded downward as shown in FIG.
The pull-in range of T can be extended to the frequency (fp-$5) on the lower side.

In this way, the discrimination characteristic is spread downward, and the AFT voltage Vs is positive in the lower band, so when the AFT voltage Vs is zero (and negative) at the time of channel selection,
On the contrary, it can be considered that this is due to the fact that the upper obi castle has a hina style.

Therefore, when tuning, if the AFT voltage Vs is zero, normal tuning can be achieved by lowering the local oscillation frequency as in case (i) above, so the AFT pull-in range is on the upper side. It can be extended up to the frequency (fp 14.$kawaz). In this way, the range of AFT pull-in during channel selection can be expanded both upward and downward.

Moreover, in that case, it is possible to quickly lock to the normal tuning point without requiring a special signal detection circuit.

In addition, as shown in the GW, even if the channel is tuned outside the lower band of AFT, the black and white image in the Hina-style state will be immediately played back, making it easy for viewers to watch again. Can be adjusted. Furthermore, this operation does not cause channel skipping when the broadcast ends. Moreover, not only a signal detection circuit is not required, but also adjustment and assembly are not required.

Furthermore, it is easy to integrate into an LSI, and it is possible to realize a television receiver with low cost increase and high marketability. In the above example, AFT is not performed during presetting, but it is also possible to prevent AFT from locking to the audio intermediate frequency signal during presetting.

FIG. 10 shows an example thereof, in which 61 and 62 are rising trigger type RS flip-flop circuits, 63 to 65 are logic circuits, and 66 is a defeat circuit. Based on the pulse P9, an output of "1" is always output during presetting, but during broadcast reception, the switches S, .

After the operation, its output becomes “0” for a predetermined period of time,
Thereafter, the value is set to ``1''.The discrimination circuit 22 has, for example, the discrimination characteristic shown in FIG. 1B.

Therefore, when presetting a broadcast channel, first the mode switch Sm is switched to the preset side contact P'.

Then, the counter 13 is reset by the reset circuit 17, and the memory 11 is placed in the write mode by the control circuit 15. Therefore, switch S, is turned on, and then switch Su is turned on for a short time.

Then, by turning on the switch S, the corresponding address in the memory 11 is designated through the designation circuit 12. In addition, by turning on the switch Su, the 11th
As shown in Figure A, the time t when the switch Su is turned on,
．． Inverter 31 starts the rising start pulse Pu.
is obtained, and this pulse Pu is sent to the flip-flop circuit 6
1, the Q terminal and the output of the Q terminal, . and Q
、． are points t, . becomes “1” and “0”. Therefore, the output pulse Po of the oscillation circuit 14 passes through the AND circuit 32 and further through the OR circuit 33 at time t, . is supplied to the counter 13 as an addition input, and the receiving frequency increases. Then, when it becomes possible to receive the first channel and the video intermediate frequency Fp rises to the frequency (fp-1.ball cape z) at time t,2, the AFT command voltage V
v is obtained.

However, since Q="0" at time t,2, the output of the AND circuit 63 is "0", and therefore the output of the AND circuit 53 is also "0". Therefore, the video intermediate frequency Fp increases significantly. Then, at time 3, F
p=fp-50kHz and Vv=“0”, but
The video intermediate frequency Fp further increases, and when it reaches Fp (fp+50kHz) at time L4, Vd becomes "1" as shown in FIG. 11. Then, this voltage Vd is supplied to the reset terminal R of the flip-flop circuit 61, so that from time t, 4 to Q, . = “0”, Q, . = “1”
Therefore, the pulse Po passing through the AND circuit 32 is no longer supplied to the counter 13. Then, at time t, 4, the outputs of the Q terminal and the Q terminal of the flip-flop circuit 62, 2 and Q. 2 is “0” as shown in Figure 11 D and E.
and "1", the voltage Vd is supplied to the AND circuit 54 through the AND circuit 64 by this output Q peak, and the output of the deficit circuit 66 is always "1" during presetting.

Therefore, at time t,4, the pulse Po is output from the AND circuit 54.
, and is further supplied to the counter 13 as a subtraction input through the OR circuit 36, so that the video intermediate frequency Fp decreases from time L4. Then, Fp=(fp150
(k-th generation), Vd becomes “0”, so the pulse Po
is no longer supplied to the counter 13, and the operation stops in this state.

In this state, (fp - 50kHz) SFp≦
(fp+50kHz), it means that it is correctly tuned to the first channel. In this case, among the pulses Po supplied as addition inputs to the counter 13 during the periods t, to t4, the last pulse causes F at time t, 4.
Since p≧(fp+50k ratio) and Vd=“1”, at time t, . After that, pulse Po becomes counter 1.
3, the pulse Po is 1
Just by supplying a bit, Vd becomes "0" and the operation stops.

Then, at time t,4,Q,. ="0", this is detected by the forming circuit 16 through the OR circuit 65, and after a predetermined time from the time 4, that is, after being correctly tuned to the first channel, a write pulse is formed, and this pulse is sent to the control circuit 15. The address of the memory 11 specified by the switch S is erased, and the contents of the counter 13 at this point in time are written to the specified address of the memory 11.

Therefore, the tuning code A corresponding to the tuning voltage Vc of the first channel is written to the address of the memory 11 specified by the switch S. Thereafter, the channel selection voltage Vc of the broadcast channel can be preset in the memory 11 in the same manner.

Further, when the switch Sd is operated during presetting, the start pulse Pd for the down-pulling is restricted from the inverter 32 as shown in FIG. 12A. In this case, the operations of the circuits 61 to 64 may be replaced by corresponding circuits, resulting in the signal changes shown in FIG. 12. On the other hand, when receiving broadcasting, switch Sm is connected to the receiving side contact R.
, and turn on the desired channel among switches S, -S, and o.

Then, the control circuit 15 sets the memory 11 to read mode, and if the switch S is turned on, the corresponding address in the memory 11 is designated and the first channel corresponding to the switch S2 is selected. The code A is read out and supplied to the counter 13, and the contents of the counter 13 are set to the code A. The contents of this counter 13 are then supplied to a converter 18, converted into a tuning voltage Vc, and supplied to the tuner 1. Therefore, the first channel can be received. Furthermore, in this case, since the broadcast is being received, the output of the defeat circuit 66 is "0" for a predetermined period after the switch S is operated, that is, until the first channel is selected. , after tuning, its output becomes "1".

Therefore, if the AFT command voltage Vv or Vd is obtained after tuning, the counter 13 adds or subtracts accordingly, and the tuning code A, which is fed from the counter 13 to the converter 18, is corrected. , therefore AFT is performed. Thus, in this example, upon preset, an automatic sweep is performed to the broadcast channel, and the AFT
The tuning voltage Vc when tuned correctly is memory 1.
Preset to 1.

In this case, since the AFT command voltage Vv is obtained only for the video intermediate frequency signal using the average voltage Va of the output of the synchronization separation circuit 25, the AFT is prevented from locking for the audio intermediate frequency signal. do not have. By the way, in the channel selection control circuit 10 shown in FIG. 10, when the receiving frequency is selected, if there is a band with a strong electric field and no AGC is applied, the AFT will malfunction.

That is, the frequency characteristics of the intermediate frequency amplifier 2 are shown as shown in FIG. 13A, whereas the characteristics of the discrimination circuit 23 are shown as shown in FIG. 13B (same as FIGS. 1A and B). .

For such characteristics, for the sake of simplicity, the AGC voltage Vg of the tuner 1 is set to the intermediate frequency (carrier frequency) of the audio intermediate frequency signal or the video intermediate frequency signal of the received signal, as shown in FIG. 13C. But 54.29MHz~60.
When it is within the 28M ratio band, it is “1” and when it is outside the band, it is “0”. Therefore, when Vg = “1”, AGC is applied and tuner 1 has an appropriate gain, and Vg = “0”. ”, it is assumed that tuner 1, which is not subjected to AGC, is at full gain. In these characteristics, consider the case where the receiving frequency is swept up during presetting.

Then, in the normal reception state, as shown in FIG. 13D, the audio and video intermediate frequency signals Fs, .
Fp, is located at frequencies fs and fp (indicated by carrier position). Also, in regular television broadcasting, the broadcast is 1
Since this is done for every channel, the signals FS,,Fp
, the audio and video intermediate frequency signals Fs2 and Fp2 of the adjacent broadcast come at a frequency position about lam lower than .
In the case of a strong electric field, a pseudo signal (beat signal) Fu,, Fd is generated at a frequency position 4.9 MHz away from the signal Fs,, Fp, due to intermodulation between the signals Fs,, Fp,
, and the signals Fs2 and Fp2 also generate pseudo signals Fu2 and Fd2 on the aircraft.

However, in this tuned state, since AGC is applied with Vg = "1" and the gain of tuner 1 is small, the level of the pseudo signals Fu, , Fd2 is extremely low at 4.0, and it is considered that they are not actually occurring. be able to. Therefore, under normal reception conditions, the signal shown by the solid line in FIG. 13D is obtained from tuner 1, and the signal shown by the broken line is not obtained (
In the explanations that follow in FIG. 13E, the solid line indicates that the signal is obtained, and the broken line indicates that the signal is not obtained).

Then, in a state where the tone is slightly higher than this state, the first
As shown in Figure 3E, the signals Fs・, Fp2 are Vg=
It is in the “0” band.

Therefore, since AGC is not applied to the tuner and the tuner is at full gain, pseudo signals Fd, , Fu2 are obtained. Thereafter, the signal changes as shown in FIG. 13 F-1 as the signal is tuned higher in the same way. The state shown in FIG. 13 is a state in which the adjacent broadcast channel is normally received. Among the states shown in FIGS. 13D to 1, in the states shown in FIGS. 13E and F', the AFT voltage Vs
Since the pseudo signal Fu2 is obtained within the positive band of , at this time, a false AFT command voltage Vu is obtained by this signal F. Therefore, when the receiving frequency is continuously increased, as shown in FIGS. 14A to 14C,
The false AFT voltage Vs and the command voltage Vv are generated in the period t2 to t8 corresponding to E and F in FIG. 3, and then the original AFT voltage Vs and the AFT command voltage are generated in the period t5 to t8 corresponding to FIG. Pressures Vv and Vd are obtained.

Furthermore, when the reception frequency is continuously swept downward, the signal changes to the states shown in FIGS. 1 to 13D.
As shown in Figures A to C, AFT voltage Vs and command voltage Vv
, Vd.

Then, when a false AFT command voltage Vv is obtained in addition to the original AFT command voltages Vv and Vd, the above-mentioned channel selection control circuit 10 determines that this false AFT command voltage Vv is "
Sweeping stops when the frequency level becomes 0''.

Therefore, the receiver is in a state where it receives and reproduces the pseudo signal Fu2, so the reproduced screen may be out of synchronization, become a smeared screen with dropped Takagi, or lack color, or in any case. The image quality will be worse than under normal reception conditions. In the example of FIG. 16, in consideration of these points, the AFT is prevented from malfunctioning with respect to the pseudo signal Fu2.

Now, according to Figures 13 to 15, when the reception frequency is continuously changed, the original AFT due to the broadcast channel
If it is a command voltage, this is obtained as a pair of voltages Vv and Vd, but if it is a fake AFT command voltage based on the pseudo signal Fu2, it is only the voltage Vv.

In this example, this difference in AFT command voltage is used to perform AFT operation only with the original AFT command voltages Vv and Vd. In other words, during sweeping, AFT command pressure Vv or Vd is not obtained. The striping is continued at a constant speed, and if the opposite APT command voltage Vd or Vv is obtained within a specified time, the sweeping is stopped only at this time.

In FIG. 16, 71 to 74 are rising trigger type RS flip-flops. 75 is a delay circuit that delays the input by the specified time, and 81 to 88 are logic circuits. In addition, the output of the defeat circuit 66 is "0" during presetting, and only for a predetermined period during broadcast reception.
0" and thereafter becomes "1". Therefore, during presetting, for example, if the switch Su is turned on for a short time at time t2, the inverter 31 outputs the signal D shown in FIG.
As shown in FIG. 2, the start pulse Pu of the upward sweep is obtained at time t2. Since this pulse Pu is supplied to the reset terminal R of the flip-flop circuit 72 through the OR circuit 82, the output Q,2 of the flip-flop circuit 82 changes from time t to phantom as shown in FIG. “
0''. Furthermore, since the pulse Pu is supplied to the reset terminals V of the flip-flop circuits 73 and 74 through the OR circuit 88, the outputs of the flip-flop circuits 73 and 74 as shown in FIG. Q, 3, Q, 4 are
It becomes "0" from time t2. Furthermore, the pulse Pu is
Since it is supplied to the set terminal S of the flip-flop circuit 71, the outputs Q, . becomes "1" from the time point et al. And this output... is supplied to the AND circuit 32, so the output Po of the oscillation circuit 14 is fed through the AND circuit 32 and further through the OR circuit 33 as shown in FIG. be done.

Therefore, the reception frequency increases from the point onwards. Then, at time 2, the pseudo signal Fu2 causes the AFT
A voltage Vs is generated, which results in a false AFN command voltage Vv.

This voltage Vv and the output Q of the flip-flop circuit 71, . is supplied to the AND circuit 83, and
Since the output of the AND circuit 83 is supplied to the set terminal S of the flip-flop circuit 73, Q,3=“1” from the point in time.
”. In this case, the voltage Vv is
However, since the output of the defective circuit 66 is "0", no output is obtained from the AND circuits 53, 54, and since Q,4: "0", the AND circuit 86
I can't get any output either.

Since this output ``N,3'' is supplied to the delay circuit 75 through the OR circuit 87, the 14th output from the delay circuit 75 is
As shown in FIG. 1, pulses P and 5 are taken out at time 4 after a specified time 7 and 5 from time t2, and these pulses P and
s passes through the OR circuit 88 to the flip-flop circuit 73,
74, and therefore, from time point 4, Q,3 becomes "0". Further, prior to this, at time t23, Vs=0 and Vv=“0”.

However, since the AFT command voltage Vv obtained during the period t22 to t23 is a false AFT command voltage, the AFT command voltage yd is not obtained following this AFT command voltage Vv, and therefore, Vd: "0" continues, QQ becomes "1" during the period, and even if this is supplied to the asode circuit 85, the output Q,5 of the AND circuit 85 is "0" as shown in FIG. 17J. Then, when the broadcast channel can be received at time t25, the AFT voltage Vs is obtained and the AF
Since the T command voltage Vv is obtained, Q,3 becomes "1" in the same manner as at time t2.

In this case, the broadcast channel is being received, and the reception frequency is increasing at a rate determined by the frequency of the oscillation pulse Po, so the time t is a certain period of time after the time t, 5.
, 6, the AFT command voltage Vd is obtained instead of the AFT command voltage Vv. Therefore, at time t26, the input of the AND circuit 85 is Q. 3="1" and Vd="1", so Q,5="1". Then, this V is supplied to the reset terminal R of the flip-flop circuit 71 through the OR circuit 81, so that from time 6 to Q, . = “0”. Therefore, the oscillation pulse Po that had been supplied to the counter 13 through the AND circuit 32 is no longer supplied to the counter 13 from time t, so the addition count of the counter 13 stops from time t to 8, and the reception status of this broadcast is become.
Also, the output Q, . = “0”, this is OR circuit 6
5 to the write pulse forming circuit 16 to form a write pulse, and therefore the contents of the counter 13 are written into the memory 11 as the channel selection code Ai. In this case, since the addition count of the counter 13 is stopped at the time point t when the AFT command voltage Vd is obtained, the contents of the counter 13 written in the memory 11 are as follows.
Strictly speaking, (f.

This means that it does not correspond to the frequency range (50 kHz). However, the pulse P supplied as an addition input to the counter 13
o (Fig. 14K), the last pulse causes Vd=
Since it became “1”, this (f. Saturday 50k criticism)
The tuning error for the signal is only one bit of the pulse P0, and AFT is performed during normal reception. Therefore, there is no problem even if the contents of the counter 13 at time t26 are stored in the memory 11 as the channel selection code Ai. Then, at time t27, which is a time 7,5 after time 5, pulse P,5 is obtained from the delay circuit 75, and this is supplied to the reset terminal R of the flip-flop circuit 73 through the OR circuit 88, so that at time t27 to Q, 3: “0
'' becomes.

(Note that at time t26, the ridge pulling has stopped, so in reality, the voltages Vs and Vd in FIGS. 14A and C are 8.
From now on, it will remain “1” and if you operate switch Su again,
At time t, the state of pine tree is reached.

FIGS. 14A to 14C show changes when the sweep is continuous. This also applies to FIGS. 15A to 15C. ) Thereafter, by operating the switch Su, the same operation as described above is repeated, and the selection code pile of each broadcast channel can be written into the memory 11.

Further, when the switch Sd is operated during presetting, a downward sweep start pulse Pd is obtained from the inverter 34 as shown in FIG. 15D.

In this case, the operations of the circuits 71 to 74 and 81 to 86 may be interchanged between corresponding circuits.
The operation is exactly the same, and the signal changes as shown in FIG. 15. However, Q,6 is the output of the AND circuit 86. On the other hand, when receiving broadcasts, switch S. The desired channel is selected by ~S, o, and the output of the day-to-day circuit 66 is "1" during normal operation, so the AFT command voltages Vv, V
d, the oscillation pulse Po is obtained from the AND circuits 53 and 54, and AFT is performed.

As described above, in this example, the difference between the original AFT command voltages Vv, Vd and the false AF command command voltage Vv caused by the pseudo signal F is used, and the sweep and Since the signal passes through the AFT, the clearest reception can be achieved quickly.

The present invention can also be applied to a case where the memory 11 and the designation circuit 12 are not provided, and the sweep selection is performed using the output of the counter 13.

[Brief explanation of the drawing]

Figures 1 to 4 are waveform diagrams for explaining this invention, Figure 5 is a system diagram of an example of this invention, Figures 6 to 9 are waveform diagrams for explaining its operation, and Figure 10 is a waveform diagram for explaining its operation. The figure is another system diagram of the present invention, Figures 11 and 12 are waveform diagrams for explaining its operation, and Figures 13 to 15 are waveform diagrams for explaining still other examples of the present invention. , FIG. 16 is a system diagram of still another example of the present invention. 1 is an electronically tuned tuner, 11 is a memory, 12 is an addressing circuit, 13 is a counter, 14 is an oscillation circuit, and 18 is a DA converter. Figure 1 Figure 2 Figure 3 Figure 4 Figure 11 Figure 2 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 13 Figure 14 Figure 15 Figure 16

Claims (1)

[Claims] 1 Based on the reception operation, the contents of the counter are set to a value corresponding to the reception frequency, this value is converted from D to A to form a tuning voltage, and this tuning voltage is supplied to the electronically tuned tuner. In the receiver that receives the frequency specified in the above reception operation, the output of the video intermediate frequency amplifier is supplied to the frequency discriminator circuit, and the output of the video intermediate frequency amplifier is supplied to the frequency discriminator circuit for up-sweeping and down-sweeping for the video intermediate frequency and the audio intermediate frequency, respectively. AF
While obtaining the T voltage, detect the average level of the output of the synchronization separation circuit, and use this detection output to erase the AFT voltage for upward sweep with respect to the audio intermediate frequency to obtain a corrected AFT voltage, and obtain the corrected AFT voltage. A television receiver that performs AFT by correcting the value of the counter based on the AFT voltage.