JPS6013615B2 - Analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to gain drift compensation of a voltage-to-frequency conversion type analog-to-digital converter (A/○ converter).

There are two types of A/D converters: comparison type (parallel comparison type A/D converter, cascade type A/D converter) and counting type (voltage-frequency conversion type A).
/D converter, integral type A/D converter, voltage one-time conversion type A
/D converter) and feedback type (successive approximation type A/D converter, tracking comparison type A/○ converter, circular comparison type A/○ converter), but for applications where conversion speed is not important. A counting type is suitable for this.

Here, FIG. 1 shows a conventional voltage-to-frequency converter (V/F
The configuration of a voltage-to-frequency conversion type A/D converter using a converter) is shown below. In FIG. 1, an input analog voltage Vi is applied to the input terminal of a V/F converter 11, and the V/F converter 11 has a frequency f proportional to this analog input voltage.
Outputs the signal of i. The output of the V/F converter 11 is supplied to a counter 13 through an AND gate 12. Reference numeral 14 designates a clock pulse generator which outputs a signal at a precise frequency fc, the output of which is supplied to a counter 15 for determining the time at which the AND gate 12 is opened. FIGS. 2A and 2B are timing diagrams for explaining the operation of this A/D converter, in which the counter 15
counts precisely timed clock pulses generated by the clock pulse generator 14 and generates the output signal TM for a predetermined time TN, during which time the AND gate 12 is opened. While the AND gate 12 is open, the V/F converter 1
A counter 13 counts a signal having a frequency fi corresponding to the input voltage Vi from the counter 1 . Therefore, if the time TN is kept constant, the value counted by the counter 13 will be the analog input voltage Vi converted into a digital value. At this time, if the time TN is related to the power supply frequency fp, that is, if the time TN is selected to be an integral multiple of 1/fp,
It is known that it is less susceptible to the effects of noise of the power supply frequency and its harmonic components, and that A/○ conversion errors can be reduced. However, the voltage-to-frequency conversion type A/D converter using the conventional V/F converter as described above has a drawback that its accuracy is directly affected by the accuracy of the V/F converter 11.

In particular, the initial gain error of the V/F converter 11 and the gain drift due to temperature changes are a big problem.
I had gotten a converter. However, an increase in price due to the use of such a V/F converter is unavoidable, and even with this method, gain drift cannot be reduced to zero, and V/F converters are often
There are drawbacks such as the need to perform precise gain adjustment of the /F converter. In order to eliminate such drawbacks of conventional A/D converters, Tokubatsu Publication No. 102452/1987 incorporates a reference voltage, which measures the gain drift of the V/F converter and uses this as a reference voltage. A method has been proposed in which the time TN is changed depending on the result to compensate for the gain drift of the V/F converter. However, in this method, the time TN changes, so as mentioned above, it is possible to always set the time TN to an integral multiple of the power supply cycle 1/fp to avoid the effects of noise from the power supply frequency and its harmonic components. The advantages of the voltage-frequency conversion type A/D converter are lost. The purpose of the present invention is to perform high-precision A/D conversion without being affected by the drift of the V/F converter without using a low-drift V/F converter using particularly high-precision parts. It is an object of the present invention to provide a voltage-frequency conversion type A/○ converter that can be realized at a lower cost and is less susceptible to the noise of the power supply frequency and its harmonic components. A frequency conversion type analog-to-digital converter that includes a voltage-to-frequency converter that converts voltage to a frequency corresponding to the voltage value, and a counter that counts this frequency over a certain period of time, and outputs the count value of this counter as a digital signal. a reference voltage source that generates a stable reference voltage; a selection means for selectively supplying the analog input voltage and the reference voltage to the voltage-to-frequency converter; and an output of the voltage-to-frequency converter. a variable frequency divider that divides the frequency by a set frequency division ratio and supplies the frequency to the counter; a setting means for setting the frequency division ratio of the variable frequency divider; and a reference voltage selected by the selection means. In this case, a counting means for counting clock pulses generated during a period until the output frequency of the voltage-to-frequency converter or the variable frequency divider reaches a predetermined count value, and the setting means for setting the count value of the counting means. The invention is characterized by comprising means for causing the selection means to select the analog input voltage after setting the setting brain.The present invention will be described in detail below with reference to the drawings.

The configuration of one embodiment of the A/D converter according to the present invention is shown in FIG.

Here, also in the present invention, the basic configuration is that the analog input voltage Vi supplied to the input terminal 21 is converted by the V/F converter 22 into a signal with a frequency fi proportional to the voltage value, and this is counted by the counter 23. There is no change in this, and the time for the counter 23 to count the output of the V/F converter 22 is obtained by a combination of the clock pulse generator 24 and the counter 25, which is also similar to the conventional example. However, in the present invention, in order to compensate for the gain drift of the V/F converter 22, the reference voltage generator 26 and the variable division divider 2 are provided.
7, and a register 28 for setting the division ratio of the variable frequency divider 27.
and has. Input analog voltage Vi and reference voltage generator 2
The reference voltage VN generated by 6 can be supplied to the V/F converter 22 by selecting one of the switches 29 and 301, and the output of the variable frequency divider 2'. (frequency f.) and the output of the clock pulse generator 24 (frequency fc), one of which is distributed to the counter 23 and the other to the counter 25 by a gate circuit 31. These operations will be explained in detail later. The variable frequency divider 27 can change its frequency division ratio according to digital information set at the minute ratio setting terminal 32. For example, the frequency division ratio is set at the setting terminal 32 according to n-bit digital information. In this case, the input frequency f; and the output frequency f. There is f between.

There is a relationship of band f: ...-----4'1'.

Here, Mf=2n......■, M is a digital quantity set to the terminal 32, and the values set to the n bits of the terminal 32 are sequentially transferred from the upper bit to A,... ......, An-, (Ao~
An-, = 1 or 0), then M = to 2n-10A
．．・2n-20......10An-.・Zo
......[Given in 31.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to timing diagrams shown in FIGS. First, the overall operation of the A/○ converter of the present invention shown in FIG. 3 will be briefly described.The counter 25 functions as a timing pulse generator and controls the operation of each part. First, the reference voltage VN of the reference voltage generator 26 is supplied to the V/F converter 22, whereby the V/F converter 22 is supplied with the reference voltage VN of the reference voltage generator 26.
By changing the frequency division ratio of the variable frequency divider 27 according to the frequency fi obtained at the output terminal of the F converter 22, the V/F
Compensate for gain drift in converter 22. That is, for the same reference voltage VN, the output frequency f of the variable frequency divider 27. The minute-to-minute ratio of the variable frequency divider 27 is set so that the frequency is always constant. As a result, the gain drift of the V/F converter 22 has been compensated for at the output terminal of the frequency divider 27, so next, the analog input voltage is applied to the V/F converter 22 instead of the reference voltage generator 26. If supplied, divider 2
The frequency corresponding to the input voltage should have been correctly obtained in the output of 7. The detailed operation of the A/D converter of the present invention will be explained below.

The timing signal generator 25 generates various timing signals as described above, and hereinafter these timing signals will be represented by symbols TM to TM7. These timing signals can be formed based on a suitable clock signal, provided that the duration of the signal controlling the gate circuit 31 (T and TN, which will be described later) is determined by the variable frequency divider 27.
It must have a certain relationship with the output frequency of the clock pulse generator 24 and the accurate clock frequency of the clock pulse generator 24, and should be determined based on these factors. First, the timing signal generator 25 generates an initial value setting signal TM, and an initial value M is set in the counter 23 by an initial value setting means (not shown).

Next, a register set signal TM2 is generated, and the above initial value M is set.
, is set in the register 28, so that the frequency division ratio of the variable frequency divider 27 becomes M. /Mr is set. Next, a timing signal TM4 for supplying the reference voltage VN to the V/F converter 22 is generated over a predetermined period, and only during this period, the switch 29 is opened and the switch 30 is closed to convert the reference voltage VN to V/F. A groove is provided in the container 22. As mentioned above, the digital value set at the dividing/total ratio setting terminal of the variable splitter 27 is M, that is, the minute ratio is M,/Mf, so the output frequency of the splitter 27 is set to f. And then. = Kasa f
'・・．．・-・----[4'.

Here fi, of course, the reference voltage VN is V/F converter 2
This is the value converted into a frequency by 2. Next, a counter clear signal TM3 is generated to clear the counter 23. At the same time, a first gate signal T is generated to control the gate circuit 31. The gate circuit 31 consists of four AND gates 32 to 35 and two OR gates 36 and 37, as shown in FIG. As is clear from FIG. 3, when the first gate signal TM5 is generated, the gates 32, 3
5 is opened, the output of the clock pulse generator 24 is sent to the counter 23, and the output of the frequency divider 27 is sent to the timing pulse generator 2.
5 respectively. Timing pulse generator 25
counts the output pulses of the frequency f of the variable frequency divider 27,
At the time when the number of these is counted up to a preset K number, the first gate signal T is caused to fall. That is, the duration time T, of the first gate signal TM5 is T. = odd ‐‐‐‐...
--'5}.

Since the AND gate 32 is open only during this period T, the counter 23 uses the clock pulse generator 24 during this period.
The pulses of frequency fc generated by is counted. Therefore, during this period, the count location of Karinyu 23 is Ike=fC
・T. =Ki●K=Kasa・Nozomi-K ・-・[It becomes 61. Next, the register set signal TM2 is output again and the above count value M2 is output.
is set in register 28. Therefore, the branch 27
The frequency division ratio is now ground/Mf. Next, a timing signal TM6 for supplying the analog input signal Vi of the input terminal 21 to the V/F converter 22 is generated to close the switch 29 and open the switch 30. This allows the analog input signal V
i is supplied to the V/F converter 22, which converts it into frequencies f,
Convert to 2. At this time, the previous V/F converter 22 converts the reference voltage VN to the frequency f, . Since only a short time has passed since the conversion to V/F converter 22, the gain drift of the V/F converter 22 during this time can be almost ignored.
i2.

However, in order to maintain this relationship, the linearity of the V/F converter 22, that is, the proportional relationship between the input voltage and the output frequency must be established with sufficient accuracy. In any case, if the output frequency of the V/F converter 22 is fi2, the variable frequency divider 27
Since the frequency division ratio of the frequency divider 27 is M2/Mf, the output frequency of the frequency divider 27 is given by Orikasa・fi2=Kasa・Toku・K・Kasa・K. fi2-.・・・・・・
・[8)-M, f.

is given by

Here, if we use formula '7), Orikasa stock...・・・．
- [9', and it can be seen that the output frequency f of the variable frequency divider 27 is exactly proportional to the analog input voltage Vi.

Therefore, at this point, the counter clear signal TM3 is generated again to clear the contents of the counter 23, and at the same time, the second gate signal TM7 is generated. This opens gates 33 and 34 so that the output of clock pulse generator 24 is fed to timing pulse generator 25, and a signal with a frequency V, exactly proportional to the analog input voltage V, of variable divider 27 is sent to the counter. 23. The timing pulse generator 25 counts accurate clock pulses from the generator 24 and causes the second gate signal TM7 to fall after a predetermined gate time, that is, the integration time TN, to close the gates 33 and 34. , therefore, the counter 23 stops counting. The operation during this time, that is, the operation after the second gate signal TM7 is generated, is the same as that of the conventional A/○ converter explained with reference to FIG. It has become. Of course, the time TN is preferably selected at an appropriate value so as to be less susceptible to the influence of the power supply frequency, as in the conventional example shown in FIG.
The final count counted by the counter 23, that is, the digital conversion value D, is D=TN● et al. 2=f Nagamine floor NV'
…….

It becomes Q. For example, if the standard voltage VN is equal to the input voltage that gives the full scale of this A/D converter, then Vi=
When VN, the digital conversion value D given by the 00 formula needs to be full scale. That is, D=ra-K-TN
......(11) Value D given by M
should be full scale.

Now, if we change the expression (11), we get D−f2
......(12)TN-M, In other words, the frequency required to obtain a full-scale digital output by counting with the counter 23 during the time TN is D/TN=
If fN is used, then from equation (12), fN=crocodile .・・・
…． (13) The initial value M and the clock frequency fc may be set so as to satisfy the following.

It goes without saying that the initial value M is set to be 4 times smaller than the maximum value Mr that can be set in the frequency divider 27.

Similarly, when converting the analog voltage V' into digital, the value NZ set in the variable frequency divider 27 is also
Since only the range (14) can be taken, it is necessary to change the ground within this range to compensate for the gain drift of the V/F converter 22.

For example, as described above, set each value so that a full-scale output can be obtained with the reference voltage VN, set the output frequency of the divider 27 to obtain the full-scale output as fN, and set the reference voltage VN as an input voltage. The output frequency of the /F converter 22 is changed to a minimum value f, . From min to maximum value f,
．． Suppose that it changes up to max. When the minimum value f skin, n is obtained as the output frequency, the frequency division ratio M2/Mr of the frequency divider 27
Therefore, even if this is set to the maximum value, that is, M2/Mf = 1 as seen from equation (14), if the output frequency of the frequency divider 27 does not reach fN, the purpose of the present invention will be defeated. cannot be reached. So at least fNmif skin;n......(15)
It is necessary to do so.

Conversely, when fi and max are obtained as the output frequency for the input string pressure VN, the frequency division ratio M2/Mf is reduced to compensate. As can be seen from equation (14), even if the frequency is 1, the purpose of the present invention cannot be achieved if the output frequency f of the frequency divider 27 becomes larger than the frequency fN that gives the full scale. When the ship was on board 1. =
Since Migishi San ‐‐‐‐…‐‐(16),
It is necessary to make it so that fN no coldness (17).

In this way, if formulas (15) and (17) are satisfied, V/F
The drift of the transducer 22 is compensated for so no precise adjustment is required. FIG. 5 is a line showing the structure of another embodiment of the A/D converter according to the present invention. Since this embodiment has substantially the same structure as that shown in FIG. 3, corresponding parts are designated by the same reference numerals. The difference from the embodiment shown in FIG. 3 is that the pulses counted by the timing pulse generator 25 are not supplied from the output of the variable frequency divider 27 through the AND gate 35, but are supplied from the output of the V/F converter 22. It is a point. The operation is also almost the same as the embodiment shown in FIG.
The first pulse of the signal TM and the counterset signal TM2 shown in the timing diagram of FIG.
The pulse (indicated by the hatched area) is no longer generated. Therefore, the operation begins with generation of the timing signal TM4 for supplying the reference voltage VN to the V/F converter 22. After this, the counter clear signal TM3 and the first gate signal T
The occurrence of M5 opens the AND gates 32 and 35, and the timing pulse generator 25 and counter 23 start counting, but in this embodiment, the pulses counted by the pulse generator 25 at this time are V/V as described above. This is the output of the F converter 22, and its frequency is the same as the reference voltage VN' of the converter 22.
The value when converted by f, . ′. On the other hand, in the embodiment shown in FIG. 3, the frequency supplied to the pulse generator 22 through the AND gate 35 is {fo, shown in equation 41. In formula '4', the frequency fi is a value obtained by converting the reference voltage VN by the V/F converter 22. Therefore, VN・VN′……(18) ball・
1f, 1' holds true.

By the way, by setting fi,'=fo, the embodiment shown in FIG. 3 and the embodiment shown in FIG. ．． ′
=Kasa-fi. ‐‐‐‐‐‐‐‐‐(19), and (1
From equations 9) and (18), VN': Kasa-VN small--
(2o) The reference voltage VN' may be set so as to satisfy the following equation.

The timing pulse generator 25 outputs the frequencies f, . The operation after starting counting of the signals of ' is the third
Since it is exactly the same as the embodiment shown in the figure, its explanation will be omitted here. In the embodiment of FIG. 5, the setting terminal 3 of the counter 27
Since there is no need to determine the initial value M, the configuration becomes simple. The embodiment shown in FIG. 6 is a modification of the embodiment shown in FIG. Components corresponding to those in the embodiment shown in FIG. 5 are designated by the same reference numerals. This embodiment differs from the above-mentioned embodiments in that the value M for setting the frequency division ratio in the variable frequency divider 27 is
A counter 41 that counts 2 is provided separately. Because of this, the register 28 is invalid.
As is clear, the operation is almost the same as the embodiment shown in FIG. 5, and the difference is that when the first gate signal TM5 is generated and the AND gates 32 and 35 are opened,
The signal passing through the AND gate 32 is counted not by the counter 23 but by the count 41, the result of which becomes the division ratio setting value of the variable frequency divider 27. Therefore, among the timing signals, the counter clear signal TM3, which is generated at the same time as the gate signal TM5, is the counter clear signal TM3.
1 and the second gate signal TM7 generated simultaneously with the second gate signal TM7 are respectively supplied to the counter 23. Of course, the register set signal TM2 and the initial value setting signal TM are unnecessary. Note that the present invention is not limited to the above-described embodiments, and various modifications and changes are possible.

For example, the configuration of the gate circuit 31 is such that the outputs of the V/F converter 22, the variable frequency divider 27, and the clock pulse generator 24 are selectively transferred to the timing pulse generator 2 according to the timing signal.
5. Any other suitable configuration can be used as long as it can be supplied to the counter 23 or the counter 41. According to the present invention, it is possible to convert an analog input voltage into a digital value with sufficient conversion accuracy without using a particularly highly stable V/F converter, and the stability is substantially determined by the reference voltage.

In addition, the overall configuration is relatively simple, and the time required to count the frequency according to the input voltage is always constant regardless of the gain drift of the V/F converter, making it less susceptible to the effects of the power supply frequency and its harmonic components. You can set the thin integration time.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a conventional fly pressure-frequency conversion type A/○ converter, Fig. 2 A and B are timing diagrams explaining the operation of this A/D converter, and Fig. 3 is a A block diagram showing the configuration of one embodiment of the voltage-to-frequency conversion type A/D converter according to the present invention, a timing chart for explaining the operation of the embodiment shown in FIGS. 4A to 3, FIG. 5 is a block diagram showing another embodiment of the invention, and FIG. 6 is a block diagram showing still another embodiment of the invention. 21...Analog fin pressure input terminal, 22...
V/F converter, 23... Counter, 24...
・Clock pulse generator, 25... Timing pulse generator, 26... Reference voltage generator, 27...
...Variable frequency divider, 28...Register, 29, 30...Switch, 31...Gate circuit, 41...
・Kausota. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 Frequency conversion type analog that includes a voltage-frequency converter that converts an analog input voltage to a frequency corresponding to the voltage value, and a counter that counts this frequency over a certain period of time, and outputs the count value of this counter as a digital signal. - In the digital converter, a reference voltage source that generates a stable reference voltage, a selection means for selectively supplying the analog input voltage and the reference voltage to the voltage-frequency converter, and a selection means for selectively supplying the analog input voltage and the reference voltage to the voltage-frequency converter; a variable frequency divider that divides the output frequency by a set frequency division ratio and supplies the divided frequency to the counter; a setting means for setting the frequency division ratio of the variable frequency divider;
counting means for counting clock pulses generated during a period until the output frequency of the voltage-frequency converter or variable frequency divider reaches a predetermined count value when the reference voltage is selected by the selection means; An analog-to-digital converter comprising: means for setting the count value of the counting means as a set value of the setting means, and then causing the selection means to select the analog input voltage.