JPS6014368B2 - Arbitrary waveform generation circuit - Google Patents

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a digitally controlled arbitrary waveform generation circuit.

[Prior art]

Conventionally, there are many dedicated circuits that can generate only specific waveforms.
However, it is clear that it would be very convenient if arbitrary different output waveforms could be obtained with the same circuit configuration.

For example, in video game machines, it is required to generate a special sound for each model, so conventionally, a special sound generating circuit is designed and added to each model.

However, it is very uneconomical to design and add a waveform generation circuit according to a dedicated sound generation circuit for each type of equipment that is produced in a wide variety of small quantities. It has been desired to be able to produce multiple sounds simultaneously, and it has been desired to provide an arbitrary waveform generation circuit for this purpose. On the other hand, a function generator is conventionally known as a waveform generating circuit with this kind of degree of freedom, but the waveforms that can be extracted as its output are triangular waves, square waves, sine waves, or a sawtooth waveform obtained by a combination of these. They are waves, ramp waves, exponential waves, and are limited to certain waveforms.

Therefore, in order to generate arbitrary waveforms other than these in a function generator, a separate dedicated circuit must be set and added each time. [Object of the Invention] The object of the present invention is to generate a waveform of any frequency and shape by extracting a plurality of desired types of waveforms at a desired period from waveform data stored in advance in a waveform memory. The purpose of this invention is to provide a generating circuit.

In the present invention, a plurality of different waveforms for creating suspicious sounds or images are provided, and the waveforms are stored and held in a waveform memory in advance as corresponding waveform data.

As is well known, a general waveform has three elements: waveform (shape), repetition frequency (period), and amplitude, and if any one of these is different, it will be a different waveform. It appears as a difference in pressure, and in the case of images,
This appears as a difference in image shape.

Note that the frequency also includes the initial phase, which determines the coordinate position of the image, especially in the case of an image. Corresponding to the above three elements, each element is arbitrarily designated in the waveform generation circuit of the present invention, and the waveform is determined by the selection of the waveform data type stored in the waveform memo. The frequency (period and initial phase) is determined by setting the data readout frequency division ratio.

After the waveform and frequency are set digitally, the amplitude is set. [Structure of the Invention] The characteristic feature of the invention is that the selection of waveform data and the setting of the readout frequency division ratio are processed separately, and in particular, the frequency division ratio of the output is processed separately. It has the advantage that any frequency can be set simply by inputting it from the outside, and that a large number of waveforms can be generated even though the amount of data stored in the waveform memory is limited.

That is, according to the present invention, by changing the extraction cycle (the extraction address interval) for each waveform data, the outside of the data can be appropriately thinned out or appropriately multiplexed and read. The repetition frequency can be set.

Further, in the present invention, it is preferable that the setting of the discussion frequency is performed by digitally adding the input frequency data every fixed cycle, and specifying the address of the waveform data based on the addition result.

Further, in order to determine the initial phase of the readout frequency described above, it is preferable to input initial phase data separately from the frequency data and read this initial phase data at the time of the first addition.

[Embodiment] A specific example of the arbitrary waveform generation circuit of the present invention will be described below with reference to the accompanying drawings, with reference to FIGS. 1 to 4.

The circuit in this specific example operates in a time-division manner so that three waveforms are obtained. Therefore, three predetermined waveforms are apparently superimposed and output. For example, three different types of sounds can be simultaneously output to a suspicious sound generation circuit, and different waveforms can be displayed on a display to a video generation circuit. Alternatively, it is possible to depict color images.

However, since the present invention is based on processing only a single waveform, hereinafter, only one waveform processing will be mainly explained, and other explanations will often be omitted. 1st
In the embodiment, a waveform selection and division ratio setting circuit for selecting a desired waveform from a waveform memory and digitally setting its repetition frequency includes multiplexers 1 and 2, a data register 3, an accumulator 4, an adder 5, and It consists of a latch 6.

In Figure 1, 1 indicates that the input terminal A is the central processing unit CP.
multiplexer connected to address bus AB of U, 2
is a multiplexer whose input terminal A is connected to the data bus DB of the CPU.

The output terminal Y of multiplexer 1 is connected to both address input terminals A of data register 3 and accumulator 4, and the output terminal Y of multiplexer 2 is connected to both address input terminals A of data register 3 and accumulator 4.
is connected to both data input terminals D of. That is, when the CPU writes data to the data register 3 and accumulator 4, the multiplexer 2 connects the address bus AB and data bus DB of the CPU to the data register 3 and accumulator 4.
Serves as a connection to address and data inputs. In this embodiment, as shown in the upper part of FIG. 2, the data register 3 stores two sets of data consisting of 16-bit frequency data D and 4-bit amplitude data A, and further 20-bit frequency data. A total of three sets of D and 4-bit amplitude data A are held, and three different waveforms are processed in a time-division manner.

However, the frequency data D is divided into four digits each having four bits, and the 20-bit frequency data is divided into five digits each having four bits. Partial frequency data obtained by division is expressed as Dmm. In this case, the subscript n represents the group to which the partial frequency data belongs, and m represents the weight of the digit.
Frequency data D is the frequency of the output signal finally obtained (
The address designation cycle of the waveform memory 7) is designated, and the amplitude data An (n represents the group to which the data belongs) designates the amplitude of the output signal. On the other hand, the accumulator 4 is
A type of register, it is a device in which input values are sequentially added to the initial setting value (including zero), and the result of this operation is replaced with the original value. 2 sets of data consisting of 16-bit augend data C and 4-bit waveform selection data W for setting the initial phase of the waveform, and further 20-bit augend data C for initial phase setting and 4 bits. A total of three sets of data each containing waveform data W as a group are held.

Here, the data initially set in the accumulator 4 sets the initial phase of the waveform. The augend data C is similarly divided into 4 or 5 digits of 4 bits each, and is represented by partial augend data Cnm for one digit. As described above, the subscript n added to the partial addend data Cnm and the waveform selection data Wn represents the group to which these data belong, and the subscript m digit position. Of the three groups of data above, each group has one group (for example, D, o to D, 3, A,, C, 3,
C,o~C,3,W,) is data regarding one waveform (
It handles frequency data, amplitude data, initial phase data, waveform selection data).

The symbols above each block in the upper and lower rows of FIG. 2 represent the addresses of each data section in 16 units.

This address is designated by a synchronization signal SS from the control signal generator 11, which will be described below. - The control signal generator 11 generates a synchronization signal SS and a control signal CS as shown in FIG.

The synchronization signal SS is 4th (750KHZ), Hoso (37roHZ)
), Group 1 (187.Hz) and Group 3 (93.7Hz)
) is a 4-bit binary signal. Control signal C
S is a multiplexer operation signal M, an accumulator write signal WR, a data register write signal WR, a first latch signal PCK, a first latch clear signal CLR, and a second latch signal TCK. However, WR○, WR, is the CPU
The control signal generator 11 receives the write control signal WRC from
This is a signal synthesized within. As can be seen from FIGS. 2 and 3, the switching signal MPX applied to the control input terminal S of the multiplexer 1 is at logic "1" in the latter half of each address section of the synchronizing signal SS. Therefore, the multiplexer 1 is switched to the input terminal B side each time. Therefore, the synchronization signal S applied to the same input terminal
S passes through multiplexer 1 and is input to data register 3 and accumulator 4 to specify the address. Therefore, the data register 3 and accumulator 4 sequentially output data from designated addresses "0" to "F". The adder 5 receives the frequency data D output from the data register 3 and the augend (initial phase) output from the accumulator 4.
Data C is added in a bit-parallel digit-series format.

That is, for addresses "0" to "F" of the synchronization signal SS, the addition result of the partial data Dmm and Cnm of the same digit, that is, the sum (4 bits) and carry data (1 bit) is output. However, this carry is the actual value of the data Dnm and Cmm, and may or may not occur depending on the nature of the carry. The sum and carry data from adder 5 are each sent to latch 6 and latched therein.

This latte signal PCK is the multiplexer switching signal M
This is done by being generated in about the first half of the logic "1" section of the circle X and being input to the latch 6.
The sum latched in latch 6 is sent from the output terminal of latch 6 through line 12 to input terminal B of multiplexer 2, through which it is input to accumulator 41. In this case, since the accumulator write signal WR is a pulse generated in the latter half 1'2 of the logical "1" interval of the multiplexer switching signal M, the sum data from the latch 6 is used to create the sum. is written to the address location of the added data and the augend data. For example, data D. The sum of C and o is written to the address of data C and o. On the other hand, when a carry occurs in the addition result, the carry data is passed from the output terminal of the latch 6 to the input terminal C of the adder 5 through the line 13.
sent to. Therefore, for example, data D,. and C,. If a carry occurs in the addition of data D.1 and CI., as a result, the next data D.1 and CI. are added by taking this carry data into consideration. In the invention, the accumulator 4, the adder 5 and the latch 6 form the adding means. Reference numeral 7 denotes a waveform memory in which a plurality of waveform data are stored, and the address input terminal of the lower 5 bits of this waveform memory 7 is connected to the output of the latch 6 so that the upper 5 bits of the augend data C are input as frequency division ratio data. connected to the terminal.

The address input terminals of the remaining three upper bits are connected to the output terminal of the accumulator 4 so that the waveform selection data Wn is input. A latch 8 is connected to the 4-bit output terminal of the waveform memory 7, and a latch 9 forming an amplitude setting circuit is connected to the output terminal of the data register 3.

Both latches 8 and 9 perform a latching operation in response to the second latch signal TCK. This second latch signal TCK is
As can be seen from the figure, amplitude data Ah and waveform selection data W
The period in which the synchronization signal SS specifies the address of n (t=
4, 9, F). At this point, the accumulator 4 outputs waveform selection data Wn, and the data register 3 outputs amplitude data An. Therefore, the data latched in the latch 8 is data from the waveform memory 7 whose upper address is specified by the waveform selection data Wn, and whose lower address is specified as frequency division ratio data by the addition result latched in the latch 6. Also, what is latched in latch 9 is amplitude data M. In the latch 6, immediately after the data from the waveform memory 7 and the amplitude data An are latched into the latches 8 and 9, the immediately preceding carry data is cleared by the clear signal CLR. The reason for this is that after the addition processing of the first group of frequency data D and the augend data C is completed, in the simultaneous addition processing of the next group for time-sharing processing, the carryover data generated during the previous addition processing is This is to prevent the influence of

If this is not done, the carry data in the addition process of one group of data will affect the addition of the next group, and the frequency of the output waveform obtained by the addition process of that group will be slightly different. Of course, it does not affect anything other than the frequency, so if it is used for purposes where some fluctuations in frequency' can be tolerated, there is no need to clear the carry data in latch 6 every time the addition of each group is completed. . 10 is a D/ that converts the digital signal from latch 8 into a corresponding analog voltage signal.
A converter, the gain of the converter is latch 9
(amplitude setting circuit).

A desired output waveform can be obtained from this D/A converter 10. FIG. 4 shows an example of the actual circuit shown in FIG. 1, and the same components are given the same reference numerals as in FIG. 1.

Multiplexer 2 uses Texas Instruments' ICs SN74SI57 and SN74SI58, and data register 3 and accumulator 4 use Texas Instruments' ICSN7.
489, adder 5 uses the company's ICSN74S283, latch 6 uses the company's SN74SI74, and latches 8 and 9 use the company's ICSN74S273.
Further, ICM5623A manufactured by Intersil Corporation is used for the waveform memory 7 and the partial component 11' of the control signal generator 11.

An example of the operation of the arbitrary waveform generating circuit of the present invention will be explained with reference to FIGS. 1 to 4.

For convenience of explanation, let's consider a case where an arbitrary question sound is generated. As is well known, the type of sound is determined by the three elements of the signal applied to a speaker etc.: its frequency, amplitude, and waveform.Therefore, in order to obtain any sound, these three elements must be freely and accurately controlled. Referring again to FIGS. 2 and 3, the synchronization signal address t=0
When , frequency data D, is sent from data register 3.

is the initial phase data C, from the accumulator 4. are output, the adder 5 adds them, the sum and carry outputs are latched by the catch 6, and this sum is written to the original address of C, o. When the address is t=1, “Similarly, D, .
and C,. is output, latch 6 latches the sum and carry output, and the sum becomes the original C, . is written to the address of When the address is t=2, the same process is performed for D,2 and C,2, and when the address is t=3, the same process is performed for ○,3 and C,3. During this time, if adder 5
If a carry output occurs in the adder 5, the carry data is added to the adder 5. This means that the timing when the output of logic "1" actually appears in the upper 5 bits (dividing ratio data) of the augend data C, that is, the 4 bits of C,3 and the 1 bit of C,2, is
This means that the larger the actual values of the frequency data D and the augend (initial phase) data C are, the earlier they arrive.
Next, when the address is t=4, the amplitude data A from the data register 3 is also transferred from the accumulator 4 to waveform selection data W,
is output. The latter waveform selection data W and t=3
The sums latched by the latch 6 are separately added to the upper 3-bit address (waveform selection data) and the lower 5-bit address (frequency division ratio data) of the waveform memory 7, respectively. Therefore, waveform data corresponding to these addresses are read from the waveform memory 7. The read waveform data and the amplitude data A are the latch signal TCK.
latches 8 and 9, respectively. The above operation is performed sequentially for three data groups of n=1, 2, and 3, and three different types of waveform processing are performed in a time-division manner.

Here, one process performed on each set of data is 1
Define it as a cycle. Since the augend data C and the frequency data D are each 4-bit partial data serialized for 4 digits, the 16-bit frequency data is added to the augend data C only once every cycle. Data D will be added. Table 2 shows the accumulated augend data C for each cycle for one type of waveform.
That is, the state of frequency division ratio data and an example of waveform data output from the waveform memory 7 are shown.

Sn (n=0, 1, 2, 3, 4...) represents the number of cycles, and WD-0 in the waveform data column is the waveform selection data W,
= 0, the output waveform data based on Table 1 is converted to WD-
7 shows waveform selection data W, output waveform data based on Table 1 in this case. Table 1 shows an example of the contents of the waveform memory 7.

Assuming that the frequency data D in the initial state is D=080 blood,
Let us assume that the augend data C is C=0000 days.
The last day represents La Hayabusa. In cycle S〇, the waveform selection data is Cape, so the upper 3 bits of the waveform memory address are 000, and since C=000, the upper 5 bits of the waveform memory address output from latch 6 are ooooo. Therefore, the address of the waveform memo 00000000, ie, day 00, is specified, and waveform data "7" is read from the waveform memory.
Similarly, in cycle S, W=OH, C=080
Since it is a plate, the upper 3 bits and lower 5 bits of the address of the waveform memory are 000 and 00001, respectively, and waveform data ``9'' on day 01 is read out. In this way, since the frequency data D is added to the augend data C every cycle, the content of the augend data C changes as shown in Table 2 every time one cycle is completed. Since the waveform memory 7 stores seven different types of waveform data from "0" to "7" as shown in Table 1, if the waveform selection data W, is 0, the waveform data shown in Table 1 is From 2
The number of stages is taken out, and changes as shown in the WD-0 column of Table 2 at the end of each cycle. Figure 5 shows
The output waveform obtained from this waveform data is expressed by taking the number of cycles 6n on the axis and the analog amount corresponding to the waveform data on the vertical axis. It can be seen from this that a sine waveform is obtained when W,=0. On the other hand, if the waveform selection data W, is 7, the waveform data changes as shown in the column WD-7 of Table 2. If this situation is represented in the same manner as in FIG. 5, it will be seen that a sawtooth wave as shown in FIG. 6 is obtained. In this way, depending on the value of the waveform selection data W, it is possible to select the waveform data in the waveform memory 7 and therefore the output waveform. Therefore, by simply storing appropriate waveform data in the waveform memory 7, any waveform can be output. Next, let's consider frequency, one of the three elements of sound.

Paying attention to the value of the augend data C in Table 2, the initial state shark o
The value of C at the time of S fox is equal to the value of C at the time of S fox.
This means that after 20 cycles since the value of C is S, the address of the waveform memory 7 returns to the initial state, which is the same as the initial state, so one wavelength is output during these 20 cycles. It turns out. Therefore, the section corresponding to this one wavelength is defined as "one period". In this embodiment, one cycle is the period during which the value of the augend data C increases by 1000 capes.
However, the number of cycles required to obtain one cycle of the waveform varies depending on the value of the frequency data D. That is, if the waveform data addressing period is short, a large number of cycles are required to obtain one period of the waveform, and if it is long, one period of the waveform can be obtained with a small number of cycles. Let Ns be the number of cycles that occur during one cycle, and if the value of the frequency data is equal, then NS = 3-digit 4 (4-digit example) NS = 4-digit 5-digit example) The time required for 1 cycle is P. , the time taken for one cycle is T
Then, Ts=Ns・tS Since one wavelength is output in one period, the frequency of the output waveform is F
If o is F.

= Mini N; tStS consideration. Sails ・----[1'Here, ts is a constant determined by the synchronization signal SS, so
The frequency Fo is determined by the value 〇 of the frequency data.
This shows that the frequency of the output waveform is the value of the frequency data ○, and can be set arbitrarily. In Table 2, the waveform data changes every cycle, so Table 2 is an example of the case where the above-mentioned output frequency is the highest.

However, if at the end of one cycle, the content of the augend data C is small and therefore the content of the upper 5 bits of the augend data C does not change, the waveform data output from the waveform memory 7 also does not change. Therefore, until the contents of the upper five bits of the augend data C change, a number of cycles pass (multiple reading is performed), and the output frequency becomes lower accordingly. By the way, if the time ts required for one cycle is similarly expressed as a frequency and expressed as FT, then the above formula m becomes as follows.

F.

= FT-Ichirento...■Therefore, D'/1000
If we look at the 0th day as the frequency division ratio of FT and Fo, this circuit is FT
It can be seen that the frequency dividing device functions as a frequency dividing device with a variable frequency dividing ratio.

As is clear from the above explanation, ``In this embodiment, in order to generate three different waveforms, calculation processing is performed sequentially on three data groups during one cycle. The first group at address t=0 to 4 of signal SS,
The processing of the second group at t=5 to 9 and the processing of the third group at t=A to F are performed by operating the same circuit in a time-sharing manner.

Therefore, as for the output waveforms, analog outputs based on address waveform data corresponding to the calculation processing of the first, second, and third groups are respectively output in a time-division manner. Therefore, for example, the sine waveform 21 in FIG. 6 in the first group processing is the same sine waveform as in FIG. 5 in the second group processing, but the waveform 22 with a frequency of 1/2 is
If the sawtooth waveform 23 shown in FIG. 6 is obtained by the processing of the third group, the output waveform obtained as a whole is a combination of these waveforms as shown in FIG. In this case, as shown in FIG. 7, when switching from one group to another, a switching signal component appears on the waveform. However, as shown in FIG. 3, the time required for one cycle is 10.67 seconds, and the frequency Fs of the switching signal is much higher than the highest human audible frequency. Therefore, when listening to the waveform in Fig. 7 as sound, the switching signal component is not audible, and it is heard as the average value of the waveform, that is, the same as the analog summation of the output waveforms based on the processing of each group, for example. It becomes possible to superimpose game play sound on background sound in video games and the like. The manner in which the frequency, shape, and amplitude of the output waveform are set in the embodiments shown in FIGS. 1 and 4 has been described above.

However, the present invention is not limited thereto, and various changes and modifications can be made within the spirit of the present invention. For example, the data configuration shown in FIG. 2 is an example, and by changing the timing of generation of the control signal CS from the control signal generation circuit 11, the number of bits of each data ○, C, A, and W can be arbitrarily changed. be able to.

Also, the reason why one digit was set to 4 bits was done simply because of the IC used. That is, the data configuration can be arbitrarily changed according to the required accuracy and resolution in each set value of frequency, waveform shape, and amplitude. For example, data ○,
Increasing the number of bits of data C increases the frequency resolution, and increasing the number of bits of data A increases the amplitude resolution. Furthermore, by increasing the number of bits of the data extracted from the augend data C and added to the address of the waveform memory 7 and the number of bits of the output of the waveform memory 7, the accuracy of waveform approximation is improved. Since one sound can be produced by one data group, the number of sounds produced at the same time changes depending on the number of data groups.

It is sufficient to prepare as many data groups as the number of sounds required.
The arbitrary waveform generation circuit of the present invention can generate arbitrary waveforms with different frequencies, waveform shapes, and amplitudes using the same circuit when only one data group is provided, and therefore can generate various different sounds. Alternatively, as already mentioned, it can be used as a frequency divider.

Furthermore, when a plurality of data groups are provided, a plurality of the waveforms, etc. can be combined using the same circuit, and therefore more complex sounds can be output simultaneously.

For example, while generating the driving sound of a moving object displayed on the screen of a video game machine, it is easily possible to generate score sounds as needed. Moreover, regardless of whether the data group is configured as one set or multiple sets,
What they have in common is that there is no increase in the number of parts even if different sounds or multiple sounds can be produced simultaneously, and that the circuits can be mass-produced or integrated into ICs.

The part of the frequency divider with variable frequency division ratio in the above embodiment is as follows:
It can also be realized by a circuit as shown in FIG. 8 or 9. FIG. 8 shows a circuit used as a root multiplier frequency divider.

In FIG. 8, the latch 30 holds the rate input data DR of the seat Z multiplier 31. latch 32
holds the waveform selection data and supplies the upper address of the waveform memory 33. Latch 34 holds amplitude data. The waveform memory 33 stores waveform data.
The counter 35 counts the output signal of the root multiplier and supplies the lower address of the waveform memory 33. D
/A converter 36 converts the digital signal into an analog signal. Now, set the number of bits of rate multiplier 31 to 1.
The number of bits, latch 30 and data DR is 11 bits, the number of bits of counter CT is 5 bits, the frequency of the clock signal of the rate multiplier is FT, and the frequency of the output signal of the rate multiplier 31 is FR. , if the frequency of the analog output signal is Fo, the rate multiplier 31 is 11 bits and the DRFR=FT/monitoring counter 35 is 5 bits.

Red/FR Yotsute DR. ...[31Fo=F
From this formula [3}, the frequency division ratio FR is determined as DR.・・・・・・
[41FR·=loooOH] It works as a frequency divider, and it can be seen that any frequency can be set.

FIG. 9 is an example of a circuit using a programmable divider.

If this circuit is the same as that in FIG. 8 except that the rate multiplier 31 in FIG. 8 is replaced by a programmable divider 37, FR and Fo are similarly set.

= Red/FR.

Therefore, 1 1. ．． ．． ．． ．．・[5
)F.

=FT kite/kite ears Calculate the frequency division ratio FR2 from this formula (5): 1 1 ......Fence FR2
=Works as a frequency divider for kite-style tiles.

This has a different form from formula '4}, but if we compare the ranges of the division ratio values, we get the following. Since the data DR of the latch 30 is 11 bits, female ≦ DR ≦ 7 FFH. Accordingly, according to the formula 4', Makiarashi ≦ FR, ≦ 2 benefits, and from the formula ``6'', it becomes Sister Arashi ≦ FR2 ≦ , and the frequency division ratio. The value range is the same.

In other words, it is possible to set frequencies in the same range in the circuit shown in FIG. 9 as in the circuit shown in FIG. As described above, the frequency dividing device having a variable frequency division ratio can be formed by a rate multiplier or a programmable divider.

However, to output a time-division waveform using a programmable divider or rate multiplier, use multiple programmable dividers or rate multipliers to operate in parallel, switch the output of each to time-division through a multiplexer, and output the waveform memo. It is necessary to supply river water. In the above embodiments, a circuit configuration that can also perform amplitude control was exemplified, but in reality, control of the frequency and waveform shape is almost sufficient for a waveform generation circuit, and therefore amplitude control is not necessarily necessary.

0 The above-mentioned circuits of the present invention can be used not only as sound effect generating circuits, but also as signal generators or function generators, and by incorporating audio waveforms or similar waveforms into waveform data. ,
It can be used as a pseudo-speech generation circuit, and by inserting audio waveforms or similar waveforms into the waveform data, it can be used as a pseudo-sound generation circuit, and it can also be used as an X-Y two-dimensional display by adding multiple waveforms to the x and y axes. Various applications are possible, such as graphic generation circuits.

Table 1 Table 2

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the arbitrary waveform generating circuit of the present invention, FIG. 2 is a diagram showing an example of the data structure of the data register and accumulator, and FIG. The illustrated diagrams, FIG. 4, are diagrams showing a specific circuit of the embodiment of FIG. 1, FIGS. 5 and 6 are diagrams illustrating the output waves obtained, respectively, and FIG. 7 is a diagram showing the output waves obtained by time division. FIGS. 8 and 9, which show the synthesis of three types of waveforms, are diagrams each showing a modification of the frequency dividing device portion of FIG. 1 with a variable frequency division ratio. 1, 2...Multiplexer, 3...Data register, 4
...Accumulator, 5...Adder, 6...
・Latch, 7... Waveform memory, 8, 9...
...Latch, 10...D/A converter, 11
...Control signal generator, D...Frequency data, C...Augend data, A...
Amplitude data, W...Waveform selection data. Figure 1 Figure 2 Figure 3 Figure 5 Figure 4 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. A waveform memory that stores and holds multiple types of different waveform data, waveform selection data that selects waveform data in the waveform memory, and frequency division ratio data that sets the read frequency of each selected waveform data. The frequency division ratio data includes a waveform selection and frequency division ratio setting circuit that supplies the input frequency data to the input frequency data, a circuit that converts the output of the waveform memory into an analog signal, and a control signal generation circuit that controls each part. and initial phase data to determine a read addressing cycle within the selected waveform data of the waveform memory, and the data read cycle of the waveform memory is time-divided to output a plurality of different waveforms. Arbitrary waveform generation circuit.