JPS6014370B2 - text processing device - Google Patents

Description

[Detailed Description of the Invention] Table of Contents Technical Field Prior Art ■ Purpose of the Invention ■ Summary of the Invention 'E' Summary of the Embodiment 'F' Description of the Embodiment (i) Preface (il) Central Unit (iii) Instructions Execution {i' First group of instructions 1 Transfer (TRA) 2 Exchange (SCA) 3 Compare (CFR) 4 Logical product (AND) 5 Exclusive OR (ORE) 6 Free transfer (TRL) 'o} 2nd 1. Transfer of constants (TRC) 2. Free transfer of constants (TLC) 3. Comparison of constants (CDC) Command to send characters to (CAP) 3 Sardine ship (hada) 〇 Fourth group of commands GWL Interrupt M Typewriter control device M Command keyboard control device WiD Magnetic tape storage device control device MiD Introducing commands to the central unit q Recording of text M Correction of text (xi) Correction of words (xii) Printing of corrected text) Examples of modifications of the invention Technical field The present invention relates to a manual input device for inputting characters to be printed, a memory. Regarding a text processing device equipped with a printer, a printing device, and a control device that controls these, in particular, text alignment, typified by right margin alignment,
tion) function.

{B} Prior Art As this type of text processing device,
etin Vol. 12, No. 12197th King May
The one described on pages 2254 to 2255 is known.

Accordingly, the character signals and space signals constituting the text line information stored on the tape are sent line by line to the line alignment logic section via the buffer. The line alignment logic unit compares the length of one input line sent to it with the line length set internally, and adjusts each base included in the input line so that the printed line has the set line length. Expand length. Under the control of the line alignment logic section, character signals and space signals are sent from the buffer to the printing device, and aligned text information is printed on the printing book. However, the conventional technology represented by the above example has a drawback in that it is not possible to justify each printed line according to different line lengths.

This is because, in the conventional example described above, the line length internally set in the line alignment logic section is not determined for each line, but is common to all lines. ■ Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to make it possible to set different line lengths for each line, so that when printing, the printing operation is interrupted by an operation for changing the line length. To provide a text processing device having a flexible line alignment function that can be executed continuously without any trouble.

■ Summary of the Invention In order to achieve the above objects, the present invention provides a means for inputting each line of text information including a character signal and a space signal, and a method for inputting each line of text information, the number of space units included in the printed line. a manual input device having means for inputting line length information defined as , and means for inputting text print alignment signals; and a manual input device having means for inputting line length information defined as a second storage device that receives information from the first storage device and stores one input line of text to be printed; and a character signal and a space signal from the second storage device. and a control device associated with the input device, the printing device, and the storage device and responsive to a print alignment signal, the control device being responsive to a print line alignment signal. a counting device for counting the number of space units for character signals and space signals actually included in an input line; a comparing device for comparing the number output from the counting device with a number determining the line length; responsive to the comparing device; When the number output from the counting device is 4 points smaller than the number that determines the line length, sometimes one space is added next to the one space signal included in the one input line to be printed stored in the second storage device. a device for storing one space unit signal giving a space unit width; a device for incrementing said counting device each time one space unit signal is stored by said device; and again after each increment of said counting layer; The comparison device compares the number output from the counting device with the number determining the line length, and the control device compares the number output from the counting device with the number determining the line length, and the controller compares the number output from the counting device with the number determining the line length. A text processing device is provided, comprising a device for activating the printing device to print a line according to a signal stored in a storage device.

The line length of each printing line is set for each line by means of inputting the line length information described above.

Summary of Embodiments In the embodiments to be described later, the manual input device comprises a typewriter 6, the first storage device comprises a magnetic tape storage device 7, and each data block stores one line of text information. is accommodated.

Further, the second storage device is composed of a core storage device 42,
The printing device is composed of a typewriter 6, and the control device is composed of a central device 5. By operating the BACKS BASE key and then the L key on the keyboard of the typewriter 6, the central unit counts the number of space key operations that are subsequently input, and prints a line defined as the number of space units. The length is determined and recorded in a predetermined element section of the second storage device.

The number that determines the line length temporarily stored in this element section will later be
It is transferred as one of the function characters to a predetermined (fourth) element portion of the data block of the tape storage device as the first storage device. After setting the line length in this way,
The worker uses the keyboard of the typewriter 6 to enter the characters of the line of text to be recorded.

As a result, one line of text information including character signals and space signals is temporarily stored in the register of the first storage device. Once the row is complete, the worker carries out the carriage return.

This is verified by the central unit decryption unit (CDC). In response to this confirmation, the counting device counts the number of characters actually entered via the keyboard. As a result, the line length of one input line is determined. At the same time, the central unit searches for a data block in the first storage device in which the text information of this one input line should be finally recorded. After the search is completed, the data block in the second storage device is searched. One line of text information temporarily stored in the device is transferred to this data block. By repeating the above operations, the text information of each input line is recorded in each data block of the first storage device. Ru.

Here, a character that determines the line length of the print line corresponding to the input line is recorded in the first predetermined (fourth) element part of each data block, and in the second predetermined (fifth) element part. A character representing the number of space units (input line length) actually included in the input line is recorded. After making the desired corrections, the text is printed, but before printing,
Line alignment processing is automatically performed for each line. First, the first
Text information is transferred line by line from each data block of the storage device to the first register of the second storage device. The one line of text information currently stored in the first register is
A Patentis mochi antedon comparison eprese
Assuming that the sentence starts with nt, and the space between each word is 1, the number NE of space units representing the input line length (transferred to a predetermined element section of the first register) is 45, representing the print line length. Assume that the number N1 of space units (transferred to another certain element section of the first register) is 50. The central unit uses a comparator to determine the number NI representing the print line length.
and a number NE representing the input line length.

If NI>NE, the contents of the first register are transferred character by character to the second register while determining whether each character is a one-space character.
transfer to the register. In this example, the first character A is first transferred to the corresponding Yasuko portion of the second register. The next character is a one-space character. In this case, the central unit transfers this one-space character to the element section next to the element section that stores A in the second register, and further transfers the one-space character to the element section next to this element section. This makes the space longer. Furthermore, characters of P and below are sequentially transferred from the first register to the subsequent element sections. As a result, the second register stores the following text information compared to the first register.

A Patentisganted on the pr.
esentA Patent is nail antedon
The upper part of the present is the head of the text information initially stored outside the first register, and the lower part is the head of the text information after being transferred to the second register.

In the transferred version, the space between characters A and P is longer by one space, and therefore the line length is also longer by one space unit. Therefore, the value of NE is incremented by 1. In this example, the updated NE value is 46. Then, repeat the above process again.

Since NI=50 and NE=46, NI>NE.
Therefore, while determining whether each character is a one-space character, the contents of the second register are transferred character by character to the outside of the first register. As a result, the following text information is stored in the first register. A Patent
ls anted on the present In this example, the initial NE value, that is, the input line length value, is 45, and the print line length NI value is 50, so the line length after transfer is equal to the print line length. Transfers have been made five times so far.

The text information after this fifth transfer is compared with the original text information as follows.

A Patent is baited on the
presentA Patent is 稗an
The line length NE of the text information under ted on the Present is equal to the print line length NI.

Therefore, by sending this text information to a typewriter, which is a printing device, and printing it, lines having the set print line length are printed. As is clear from the above description, according to the present invention, since the print line length is set for each line, the right margin can be adjusted to a desired position for each line.

The line length is defined as the number of space units, and the line alignment process can be executed at high speed because it is a method in which spaces are sequentially added one space unit at a time to each space between words. Therefore, there is an advantage that the printing operation can be performed continuously, and that line alignment can be performed in such a manner that a desired line length is given to each line. Embodiments of the present invention will be described in detail below with reference to the drawings.

(F} DESCRIPTION OF THE EMBODIMENTS (i) Introduction The automatic printing device according to the invention comprises a central unit 5 (FIG. 1) having a processing unit 39 and a core storage unit 42.

The central device 5 includes a typewriter 6, a magnetic tape storage device 7,
and a group of peripheral devices including an instruction keyboard 8. The typewriter 6 is connected to the central unit 5 through its own control unit 9, which is adapted to transmit the commands and data coming from the typewriter 6 in an appropriate form to the central unit 5 and vice versa. The typewriter 6 is of a known type and has an input/output device 12 for encoding and decoding characters coming from the central unit 5 and for sending associated instructions to the typewriter 6. The typewriter 6 is an input/output device of the central unit 5.

In fact, as will become clear from the following description, the typewriter 6 enters texts and sends them to the storage 42 of the central unit 5, selects the processing operations to be accomplished by the automatic printing device, and processes the It is possible to print the text in its final form. Magnetic tape writing device 7
is also connected to the central device 5 through its own control device 10.

The storage device 7 is adapted to contain all commands directed to the printing device, which commands are selected from time to time and transferred to the storage device 42 of the central unit 5. The storage device 7 is further adapted to contain a magnetic record of the text entered by the typewriter 6. These texts are retrieved from time to time by a worker and entered into the central unit 5 for the purpose of being printed by a typewriter 6.
The command keyboard 8 is connected to the central device 5 via a further control device 11 and has a plurality of keys, each associated with a command of a particular group of devices.

These keys therefore make it possible to select the corresponding group of commands without using the typewriter 6. During the first cycle, the text to be processed is entered in the typewriter 6, which simultaneously prints out the text itself and sends it to the storage device 4 of the central unit 5 via the input/output device 12 and the control device 9. transfer it to .

From there the text is transferred through the control unit 10 to the tape storage 7 to be recorded. The worker can now correct or change the text by adding or changing lines or clauses, changing line lengths, and correcting typographical confusion. To accomplish this task, the worker enters a set of commands on a typewriter or command keyboard 8 corresponding to the changes desired to be made.
Select by. Each group of instructions is identified by a label consisting of, for example, four symbols, so that it can be easily selected.

As a result of this operation, the selected group of instructions are transferred from the tape storage 7 to the storage disk 42 of the central unit 5 and put into operation. The central unit 5, which executes the selected instructions, therefore transfers it to the tape storage 7 after processing the text. In this way the text is recorded in the desired form and then printed by a typewriter. The operations described above are accomplished by central unit 5 executing a set of instructions recorded on tape storage 7.

Central Unit The central unit 5 includes a timing circuit or timer 20 (FIG. 2) adapted to provide the necessary timing signals for the flow of data within the central unit 5 itself.

Timer 20 essentially consists of an oscillator 21 (FIG. 3) which provides a signal C (FIG. 4) at a frequency of 6 megacycles. This signal acts on a shift register 22 (FIG. 3) formed by six flip-flops F, F6, which shifts its entire length during 12 periods each having a duration of 2 microseconds. carry out the cycle. The output signals of the six flip-flops F, F6 are shown in FIG. 4 and designated by the reference symbols T and T6, respectively.

In order to obtain the signals necessary for timing, the outputs of the six flip-flops F and F6 are coupled together via gate circuits, and the outputs of these gate circuits constitute the timing signal for the central unit 5. . For example, a flip-flop F, is coupled to a flip-flop F3 for the purpose of obtaining the signal TS.

More specifically, the direct output of the flip-flop F3 is supplied to one input of the AND gate circuit 24 via the inverter 23 (FIG. 3), and the output of the flip-flop F is supplied to the other input of the circuit 24. be done. Therefore, circuit 24
The output TS of is at level "1" when the outputs of flip-flops F and F3 are 1 and 0, respectively. On the other hand,
In other cases, the output TS is at level "0". It is therefore obvious that all other timing signals shown in FIG. 4 can be obtained by suitably combining the outputs of the other flip-flops F, F6. The central unit 5 further has a register 30 (FIG. 2) with a capacity of 3 bits and consisting of three flip-flops. register 30
One is provided with three inputs 30a, 30b and 30c, which are connected to a typewriter (FIG. 1), an external storage device 7 and an operating keyboard 8, respectively.
The register 30 (FIG. 2) has three further outputs 31a, 3
1b and 31c are provided for feeding a code of one 8-bit type letter indicating the peripheral device which has energized the corresponding input 30a, 30b or 30c of register 30 into register 32 having an 8-bit capacity. The same number of inputs to the logic circuit 31 are configured. More specifically, during the execution of an instruction by the central unit 5, the peripheral devices 6,
7 or 8 can interrupt this execution in order to send data or instructions to the central unit 5.

For this purpose, at this time the peripheral device 6, 7 or 8
Corresponding input 30a, 30b or 3 of ladder register 30
0c and thus the input 31a, 31b or 31c of the logic circuit which supplies the corresponding 8-bit type character. Furthermore, the respective inputs 31a, 31b and 31
In the case of two peripheral devices that simultaneously activate c, the logic circuit 31 selects the one of these two peripheral devices that is superior to the other and responds to this device according to the priority order given as an output. Eight bit shapes are provided. For this purpose, the logic circuit 31
consists essentially of a coupling circuit with three inputs and eight outputs. The voltage values of these eight outputs selectively configure the shapes of eight bits corresponding to each of inputs 30a, 30b and 30c. three inputs 31a,
31b and 31c are further configured in a well-known manner such that each of these inputs 31a, 31b and 31c conditions a corresponding combination of eight bits only when the force with higher priority is at the 0 level. It is connected to the logic circuit 31 in a similar manner.

For example, input 31b can provide a combination of eight bits associated therewith as output from logic circuit 31 only when input 31a is at level "0". This clearly requires input 31a to be in a lower position than input 31b. The same is true when comparing input 31c with input 31b. As previously mentioned, the outputs of logic circuit 31 constitute the same number of inputs to resistor 32.

The output of register 32 is connected via channel 33 to reset logic 34. Reset logic circuit 34
has three outputs 34a, 34b, 34c, each of these outputs relates to a combination of eight bits sent to this circuit from register 32 through channel 33; therefore, reset logic circuit 34 Outputs corresponding to combinations of eight bits present in channel 33 are energized from time to time. Each of the outputs 34a, 34b and 34c is connected to a corresponding reset circuit for the three flip-flops forming the resistor 30, so that when one of these outputs is energized, the output of the resistor 30 is The corresponding flip-flop is cleared.

In this way, when two signals are simultaneously present as inputs to register 30, for example inputs 30a and 30b, logic circuit 31 inputs into register 32 the higher priority peripheral associated with input 31a. Device,
That is, an 8-bit type character corresponding to the typewriter 6 is sent. As a result, this character is sent through the channel 33 to the logic circuit 34, which energizes only the output 34a corresponding to the typewriter 6. Therefore, the flip-flop of register 30 corresponding to the higher priority peripheral, ie, the flip-flop connected to input 30a, is cleared. In this way, after the operation associated with the higher priority peripheral has been performed, the register 30 corresponding to the lower priority peripheral is
The flip-flop connected to input 30b remains activated. The register 32 is therefore filled with the corresponding 8-bit type character and the operations described above are then repeated, so that the central unit 5 always takes into account the peripheral devices according to a predetermined priority order. The output of register 32 is further output to channel 4.
0 to another register 41. This register 41 is completely identical to the register 32 and forms the input register of the core memory 42. The characters stored in register 41 are transferred through channel 43 to counting circuit 44. The operation of this counting circuit 44 is well known and is adapted to increment the characters introduced into it through channel 43 by one unit amount. The output of the counting circuit 44 is connected to the input of the resistor 32. In this way, the contents of register 41 are incremented by one unit amount whenever an eight bit shape is fed into it through channel 40. As will be explained in more detail below, this allows sequential recall of the elements of storage 42 containing the data or instructions of the program in progress. Input register 411
The included bits are used by the address decoding circuit 4 of the storage device 42.
It will also be forwarded to 5.

Based on the shape of the eight bits present in register 41, decoding circuit 45 is adapted to select one of the cores of storage device 42. Core storage 42 has a capacity of 1024 8-bit type characters and is divided into four areas, each called a page, each page having a capacity of 256 characters. Each page is identified by code numbers 0, 1, 2, and 3, respectively. Ten bits are therefore required to identify a component of the storage device 42, namely two bits to identify the page and eight bits to identify the component within the identified page. Two bits are required. The storage device 42 consists of eight identically configured core matrices arranged in eight planes.

Each core matrix is formed of 32 rows and 32 columns for a total of 1024 cores, so each matrix has a capacity of 1024 bits. As is known, each core of storage device 42 is traversed by four conductive wires. a write or inhibit conductor, an input or sense conductor, and two addressing conductors. More specifically, each inhibit or sense conductor passes in series through all cores on each side, thus creating eight sense isolines and eight sense isolines.
There is a ban on books. On the other hand, two addressing conductors are arranged at right angles and intersect each core. Each addressing conductor passes in series through all cores arranged in the same row and column of the eight matrices. More specifically, the addressing conductors associated with the first row and first column of the core matrix pass in series through all cores located in the first row and first column of each matrix. Therefore, there are a total of three addressing conductors. The decoding circuit 45 may be comprised of any known type of combinational circuit and will therefore not be described in detail. More specifically, the decoding circuit 45 has eight input conductors to which are fed the signals present in the register 41, and thirty-two outputs connected in sequence to thirty-two pairs of addressing conductors. . Each core is selected when the two addressing conductors that intersect it are energized simultaneously. Each pair of addressing conductors is energized according to the particular shape of the signals present on the eight input conductors of decoding circuit 45, thus selecting a corresponding group of eight cores placed in the zero state. In order to introduce the information coming into the core of the storage device 42 thus selected from one of the peripheral devices 6, 7, 8, these peripheral devices are connected through channels formed by eight conductors, as will be described below. Storage device input logic circuit 47
is connected to the input of The output of this logic circuit 47 is formed by eight conductors forming a transmission channel 48. These conductors are connected to the corresponding inhibit conductors of each of the eight matrices of storage device 42. A current is sent through the inhibit conductor corresponding to the core to which it is desired to write a 0 so as not to cause a switch or change in the state of the selected core, whereas it is desired to write a 1. When the conductor corresponding to the core is removed, the state is changed in a known manner.

Similarly, to read information stored in a core, logic circuit 47 sends currents opposite to those sent during writing to the addressing conductors of the pair, so that only those cores where zeros were recorded A switch occurs.

Therefore, a voltage is induced only in the sense conductor through the core where a zero is recorded. The eight sense leads are connected through output channels 49 of storage device 42 to output registers 5.

The information retrieved in storage 42 and recorded in output register 50 may have different meanings. In fact, this is the data to be sent to the peripheral device 6, 7, 8, or the storage address to be used subsequently, or later the storage device 4.
2, or data to be temporarily stored as being transferred to another address in storage 42, or during the execution of a set of instructions. This relates to the code of the instructions to be executed by the central unit 5. For this purpose, register 5
01 is connected to peripheral devices through channel 51 to transmit data read out in storage device 42 to them.

Register 5 Masakawa and register 4 through channel 55
1 to feed it the storage address to be used next. Register 50 is further connected through channel 56 to an 8-bit register 57 to feed data to be temporarily stored therein. Additionally, register 50 is connected to an 8-bit register 59 through channel 58.
is connected to and feeds the instruction code into it. The data to be temporarily stored in register 57 comes from register 32 apart from register 50 . For this purpose, the output of register 32 is passed through channel 66 to register 57.
is connected to the input of The register 59 is connected through an output channel 60 to a decoding circuit 62 which has as many instructions as the number of instructions used by the central unit 5.
3 outputs 62, or 62,3.

Decoder circuit 62 is a combinational circuit of the type described with respect to circuit 31. As will be explained in more detail below, each instruction is identified by an 8-bit type code.

The first four bits of this code distinguish one instruction from the remaining twelve, and the second four bits constitute the so-called "address change signal", the meaning of which will be explained below. Circuit 62 connects channel 60 of the 13 output conductors.
Activates one output lead corresponding to the instruction represented by the ``present 4-bit code''.

The outputs 62, 62, 3 of the decoding circuit 62 provide commands to a command logic bag layer 63, which device 63 is hereinafter designated COMO.
1... A series of commands instructed by the COM 27 are supplied in a manner to be described later, and these series of commands control data transfer within the central device 5. More specifically, these commands open the gate circuits shown as circles in Figure 2, thus transferring information from one register to the other along the transmission channel in which these circuits are inserted. or enable transfer from storage layer 42 (FIG. 2) to one of the registers 50, 57, 59 connected thereto to execute the respective instruction. In FIG. 2, near each gate circuit is shown its specific operating instructions.

For example, command COMOI opens gate circuit S4, which gate circuit 64 transfers the contents of register 32 to channel 40.
This makes it possible to transfer the data to the register 41 through the .
The register 59 is divided into two parts each formed by four flip-flops.

The first four flip-flops are sent the first four bits of the instruction code which define the type of instruction. The outputs of these flip-flops are collected in channel 60. The second four flip-flops of register 59 are sent the bits forming the change signal. The outputs of these flip-flops are collected in channel 61. The bits in the change signal have different meanings depending on the type of instruction.

More specifically, the bits of the change signal are
The page of the storage device to which the given address belongs is derived from the information or command expressed by the command.
One peripheral device can be identified. Further, a bit in the change signal can indicate that the address or data should be increased by one unit. In the first case, the bit of the modified signal is present in channel 64' and circuit 62
is used by a decoding circuit 65 of the same type as the three outputs S5. , 652, 653 based on the content of the change signal that energizes one of the peripherals.

Thus, through channel 51, the decoding circuit connects register 50 with the selected peripheral device to effect the transfer of data between central unit 5 and the selected peripheral device. If the bits of the change signal point to a page of storage, gate circuit 121 is opened by command logic 63 so that the first two bits of the change signal are passed through channel 70 to a register with a capacity of 2 bits. 71, and thus this register 71 stores the address of the page in storage 42.

The contents of register 71 and the contents of register 41 form one complete storage address, which is formed from the ten bits defining the 1024 element portions of storage 42, as described above. The contents of registers 71 and 41 are mutually modified or static, since the bits placed individually in the two registers 59 and 32 are fed into them through respective channels 70 and 40. This possibility exists, for example, by making it possible to specify data on the same page of the storage device 42 while keeping the contents of the register 71 constant. The page number may be introduced into decoding logic 45 through channel 71 as described below. Command logic 63 is also conditioned by the bits of the change signal stored in register 59 and transmitted thereto by channel 75. The conductor 76 further connects the logic circuit 31 to the command device 6.
Connect to 3. In this way, peripheral devices 6, 7, and 8 interrupt one of the flip-flops in register 30.
Logic circuit 31 emits a signal on conductor 76 in addition to energizing one. This signal is then used by the command logic to generate commands related to the interrupt itself. The operating state in which the central unit 5 is executing instructions is given the name "mechanical operating state".

Each machine operating state has a duration of 2 microseconds and is defined by a time signal TS, the process of which is illustrated in FIG. At each machine operating state thus defined, a series of commands are generated by the command logic device 63 (FIG. 2) as a function of the signals present at its inputs, and these represent the individual commands as described above. do. More specifically,
These commands are executed by the central unit 5 through a series of machine operating states. The operation to be performed by the central device 5 in each state is uniquely defined. For this purpose, the command logic device 63 has two blocks 63A and 63B. Block 63A, shown in detail in FIG.
2 determines a series of machine operating states to be performed based on the input signals sent by. Block 638 shown in FIGS. 6-12 for each machine operating state is a sequence of operating commands CO related to the selected command.
Generate MOI-COM27. Furthermore, block 63
A leads 62.A comes from the decoding circuit 62 as input. 162
, 3 (Fig. 2), and these conductors 62, - 62, 3
is associated with one of the 13 instructions.

Additionally, block 63A has as inputs another series of four flip-flops in register 59 and leads 75 and 76 respectively coming from register 31 and lead 100 coming from storage input logic 47. Each machine operating state is defined by the activation of the corresponding output MA-MG of a series of flip-flops FA-FG included in block 63A. Since each mechanical operating state has a duration of 2 microseconds, each of the flip-flops FA-FG must remain energized for a time interval equal to 2 microseconds. To achieve this, block 6
A timing signal TS is introduced at 3A, which activates the inputs of flip-flops FA-FG via AND circuits DA-DG. Output M of flip-flop FA-FG
A-MG conditions block 63B so that commands associated with individual commands are generated during each state. More specifically, each circuit shown in FIGS. 6 to 12 constituting block 63B receives a corresponding signal MA-
MG and conditioned by the same input signal to block 63A. Since it is necessary to time a number of commands COMO1-COM27 within a range of machine operating conditions, timing signals TR, TI and TM (
4) is also entered as an input into the circuitry of block 63B.

Command C generated by block 638 of logic unit 63
OMOI-COM 27 also acts on input logic circuit 47 (FIG. 2) of memory device 42.

This logic circuit 47 also has two channels 80 and 81 as inputs, each of these having a capacity of 8 bits. Channel 80 has a source from the resistor 50, and channel 81 has a source from the resistor 57. Logic circuit 47 further has a channel 82 as an input, which channel 82
has a capacity of 2 bits and is sourced from register 71.
Channels 80, 81 and 82 are connected to registers 50, 57
and 71 to the input logic circuit 47 so that they are processed there according to the corresponding command COMOI-COM 27 generated by the command logic circuit 63. The results of these processing operations, represented by eight bit combinations, are sent through output channel 84 to the element portion of storage device 42 identified by the address contained in addressing register 41.

More specifically, the logic circuit 47 receives commands COM03 and COM03.
14 and COM 17 simply transfers the data present at its input to output channel 48 when it is acted upon.

In fact, command COM03 acts on gate circuit 85 (FIG. 13), so that the bits present in channel 80 coming from register 50 are transferred to channel 48. COM14 and COM17, which act on the two gate circuits 86 and 87, respectively, are connected to the channel 81.
and the transfer of the bits present in 46 to output channel 48 .

In this way, characters existing in register 57 (FIG. 2) and characters coming from one of peripheral devices 6, 7, 8 are introduced into storage 42 without being processed. On the other hand, when command COM06 acts on logic circuit 47, the character present on input channel 80' is incremented by one unit amount from counting circuit 881 and then transferred to output channel 48 through gate circuit 89. When the command COMI9 is issued, the eight bits present on the input channel 81 are introduced into an exchange circuit 90, which exchanges the first four bits with the second four bits in a known manner. The new characters thus obtained are transferred to the output channel 48 through the gate circuit 91. Logic circuit 47 (FIG. 2) may also compare the contents of register 50 with the contents of register 57.

More specifically, when the command COM20 is present, a comparator circuit 98 of known construction is activated and the two registers 5
0 and 57 coming in through channels 80 and 81. The comparison performed by comparison circuit 98 means whether the characters present in the two registers 50 and 57 are the same or different. The result of this comparison is represented by bit E generated by comparator circuit 98 and sent on line 95. This bit is equal to one when the characters present in the two registers 50 and 57 are equal, and equal to zero when they are different. Bit E is sent through conductor 95 to a 1-bit capacity register 96 (FIG. 2).

The contents of register 96 are sent to register 97, which has the same configuration as register 96, when command COM26 is generated. Conversely, command COM13 causes a reverse transfer.
Bit E, suitable for conductor 100, can condition the operation of command logic 63 during the execution of a particular instruction. Furthermore,
When the command COM21 exists, the AND circuit 92 (
FIG. 13) generates an AND between the eight bits present in input channels 80 and 81, respectively.

The result of this operation consists of one 8-bit type character, which is passed through gate circuit 93 to output channel 48.
will be forwarded to. On the other hand, when command COM22 is present, circuit 94 generates an exclusive OR between the bits present in input channels 80 and 81, respectively. As is known, the result of this logical operation is equal to 1 when the two bits are different, and equal to 0' when the bits are equal. This result is then transferred to output channel 48 through gate circuit 99. As previously mentioned,
All groups of instructions that condition the operation of central unit 5 are recorded on magnetic tape storage 7 (FIG. 1) in the form described below.

In order for these groups of instructions to be executed by the central unit 5, they must be transferred from this storage 7 to the core storage 42 (FIG. 2) one at a time. , the instructions constituting the selected group are executed by the central unit 5 sequentially. In order to transfer the group of instructions from the tape storage 7 to the core storage 42, a particular group called the "initial group of instructions" is executed. A group of instructions is used. This group of instructions consists of 64 characters and is stored in external storage 7.
The information is recorded on two predetermined positions by magnetic tape within the computer. The control device 10 of the storage device 7 is configured to check the two storage device addresses in which the master of the first instruction is recorded, using a method that will be described later.

When these addresses are verified, it begins transferring the "first set of instructions" in the manner described below. During normal operation, the central unit 5 is inactive, so all its registers are cleared. When timer 20 (FIG. 2) generates signal TS, output MA of flip-flop FA is forced to level 1 via AND circuit DA (FIG. 5), so that central unit 5 is placed in state A. At this time, the AND circuit 112 (FIG. 6) of block 63B activated at time S generates a COMOI command to open gate circuit 64 (FIG. 2) and transfers the contents of register 32 to register 41, thus Transfer to the decoding circuit 45 occurs. Furthermore, output MA generates a direct command COM18 (FIG. 6) which opens gate circuit 113 (FIG. 2) and transfers the contents of register 71 to circuit 45. Since all the registers of the central unit 5 have been cleared, the address 00000000 of the memory device 42 is sent to the decoding circuit 45 at this time. The contents of the corresponding storage element portion are now transferred to the output register 50. Tape storage device 7
The control unit 10 has already selected the character to be sent to the central unit 5 during this time and sends this character to the input channel 64 in a manner described below.

The AND circuit 114 (FIG. 6) of block 63B
OM17 is generated, and this command is sent to the gate 87 of the circuit 47 (
13) to transfer the first character present in the channel 46 from the tape storage device 7 to the device section in the core storage device 42 designated by the decoding circuit 45.

At the instant TR (FIG. 4) following the time interval TS, the AND circuit 115 (FIG. 6) of block 63B
04, and this command is sent to the gate circuit 116 (Fig. 2).
, and transfers the contents of register 41 incremented by one unit amount from the counting circuit to register 32.

In this way, the bit shape 000 is stored in the register 32.
00001 is sent to increment the address of storage 42 by a unit amount. The central unit 5 then controls the operation of the controller 10 of the storage device 7 so that it selects the next instruction to be introduced into the storage device 42 and into the channel 46. Next, the same operation as described above is repeated, and successive pieces of information are stored in the element section 00000001 of the storage device 42.
is memorized. In this way, 64 of the first set of instructions
characters are recorded in the first 64 element portions of the storage device 42. Since each machine operating state has a duration of 2 microseconds, the transfer of the entire initial group of instructions has a duration of 128 microseconds. When the contents of register 32 reach the binary value 64, weighted value flip-flop 64 of register 32 takes on the value 1 and therefore generates signal R64, which opens AND circuit 120 (FIG. 6) of block 63B. .

AND circuit 120 is now connected to flip-flop 35 (second
A signal RBT is generated which de-energizes the flip-flop 35 (FIG.), so that the output BT of this flip-flop 35 takes the value 0. At the same time, the register 32 is connected to the AND circuit 121 (sixth
It is cleared by the signal R4 generated by the flip-flop 35, since the output signal BT of the flip-flop 35 is 0. Thus, at this moment the result is that all registers of the central unit 5 (FIG. 2) have been cleared and that the first set of instructions has been stored in the memory 42. This group includes instructions that send the next instruction to storage 42. All subsequent instructions begin in state A.

However, for these instructions flip-flop 35 is deenergized, in other words its output BT has the value 0. Directives COMO I and COM18 (6th
When the signal (FIG. 2) is generated again, the address of the element portion of the storage device 42 stored in the registers 32 and 71 is transferred to the decoding circuit 45 (FIG. 2). Therefore, the contents of this element section are read out and transferred to the output register 5. Therefore, when BT=0, storage device 42 is released. As is known, exposing the core memory 42 is destructive and requires rewriting the information read in the selected elements. For this purpose, the AND circuit 123 of block 63B is opened by the signal BT.
(FIG. 6) generates the command COM03, which closes the gate circuit 85 (FIG. 13) of the logic circuit 47 and closes the register 5.
The contents of 0 (FIG. 2) are transferred to the instantaneous TR in the storage device 42 to the same device in which they were stored. Command COM04 transfers the contents of register 41 incremented by one unit to register 32. The AND circuit of block 63B (FIG. 6) is controlled by the signal BT via an inverter to control the moment TR following the moment TS.
The command COM05 is generated. This command is gate circuit 1
24 (FIG. 2) and transfers the contents of register 50 representing the first character of the instruction to register 59, so that
During state A, the first character of the instruction is read. The AND circuit 124 of the block 63A, which is also controlled by the signal BT via the inverter (FIG. 5), energizes the flip-flop FB via the AND circuit DB at the instant TS;
Therefore, the output M old of this flip-flop becomes level 1.

At the same time, flip-flop FA is deenergized, so that central unit 5 moves from state A to state B'. During state B, all commands are given a common command COMO1, C.
OM18 and COM03 are generated, and these commands transfer the contents of the element section of storage device 42 identified by the contents of register 32 to output register 501 and then transfer these contents to the same storage device 42 as described above. Write to the element section.

These operations during state B cause the assertion of the second character of the instruction because the address stored in register 32 has been incremented by one unit amount during state A. be. During state B, commands relating to the individual commands are also generated from block 63B' based on the contents of register 59, which still contains the code of the command.

The first four bits of this code are sent via channel 60 to a decoding circuit 62 which activates an output corresponding to the instruction represented by the four bits entered as input. As will be known later, the world power remains energized for the entire time necessary for the execution of the command itself, thus preventing generation of the command by logic device 63 during the various machine operating states produced by block 63A. condition. (iii) Execution of Instructions Execution of individual instructions by the central unit 5 will be explained.

Thirteen instructions are given to execute any program,
And each of these has 2 letters consisting of 8 pits.
formed by one or a combination of three. The first letter of each command is used to characterize the command itself and has the following format: boblb203b4b5b
6b7 The first four bits bo-b3 represent the code of the instruction and the second four bits b4-b7 represent the change signal.

Instructions have essentially two types with respect to the number of characters forming them. The first type defines the instruction, and the second and third characters each define the address of the element portion of core memory 42 on which the instruction itself operates.

The contents of these element parts are hereinafter referred to as arithmetic numbers. More specifically, the operand whose address is defined by the second character of the instruction is called the first operand, and the operand whose address is defined by the third character of the instruction is called the second operand. . The second type of instruction consists of two characters, the first of which defines the instruction and the second of which defines the address of the element portion of the operand in memory 42.

The second type of instructions are called external instructions because, as explained below, they transfer instructions or information from the central device 5 to one of the peripheral devices 6, 7, 8 connected to it, or vice versa. This is because it makes it possible. The thirteen instructions are divided into four groups with respect to the machine operating conditions required for their execution, which are described in detail below.

{i} First group of instructions To the first group of instructions belong the instructions to be executed by the central unit 5 according to the order of the five states A, B, C, D, E.

The time required for their execution is therefore 10 microseconds. These instructions are transfer (TRA), exchange (S
CA), comparison (CFR), conjunction (AND), exclusive OR (EXOR), free transfer (TRL) and later individually with reference to Tables 1 and 2 shown below. Explained in detail.

1 Transfer (TRA) The transfer instruction identified by code 1000 performs the transfer of the first operand from the address defined by the second character of the instruction to the address defined by the third character.

As mentioned above, the addresses of the elements of the storage path 42 are such that each memory element is identified by the page number and the number of elements within that page. In fact, the instructions are arranged in such a way that the addresses of all the operands related to the instructions of one program are located on the same page of storage, precisely called the "current page". Furthermore, during the execution of one program, as described later,
An operand or instruction having an address belonging to page 0 is referenced. Therefore, the operand or instruction belongs to either the "current page" or "page 0". The code associated with the page of storage to which the instruction's operand belongs is supplied with bits b4 and b6 of the change signal in the following manner.

When bit b4il, the storage element defined by the second character of the instruction (the address of the first operand) belongs to the current page; when bit b4=0, it belongs to page 0. When bit b6=1, the storage element defined by the third character (the address of the second operand) belongs to the current page; when b6;0, it belongs to page 0. Furthermore, during the execution of one program, the storage device addresses of two operands are set to 1 after the execution of one instruction.
It is necessary to increase or not increase by the unit amount.

This conclusion is represented by the values taken by bits b5 and b7. When bit b5=1, the address of the first operand is increased by one unit amount after execution of the instruction; when b5=0, it remains unchanged. The same thing occurs for the address of the second operand when b7=1 or b7=0, respectively. As mentioned above, the instruction TR
The A code is read during state A and sent to decoder circuit 62 through register 59 (FIG. 2).

During state B, this decoding circuit decodes the code of the instructions, during which the commands COMO1, COM18 and C
OM03 is generated and these commands cause the second character of the instruction, ie, the decoupling of the address of the first operand. Corresponding to the code of this instruction, decoder circuit 62 energizes output 62, (FIGS. 2 and 7), and thus the output of OR circuit 130 (FIG. 7) of block 638. 2 of the instruction stored in register 50 (FIG. 2) when bit b5 of the instruction change signal has a value of 1.
The th character must be rewritten into storage 42 which has been increased by one unit amount.

In this case, the inputs of AND circuit 131 (FIG. 7) of block 638 are all at level 1, so circuit 131 generates command COM06. This command opens gate 89 (FIG. 13) of circuit 47, resulting in register 5
The characters containing 01 are sent to circuit 98 through channel 80.
, and this circuit 98 is incremented by one unit amount. This is then transferred to storage device 42 via channel 48. On the other hand, when bit b5 of the change signal is 0, the output of AND circuit 131 (FIG. 7) is at 0 level, and as a result, command COM06 is not generated.

During state B, AND circuit 300 of block 63B is now energized so that command COM04 is generated at instant TR to open gate circuit 116 (FIG. 2) and, as previously described, register 41. and causes transfer to register 32 of the address incremented by one unit amount by counting circuit 44. At the same moment TR (FIG. 4), another AND circuit 132 of block 63B (FIG. 7)
The output of is energized, resulting in the generation of command COM15. This command opens gate circuit 146 (FIG. 2), which causes the transfer of the contents of register 50 to register 57. During state B, therefore, a second read of the instruction representing the address of the first operand is executed and this is then transferred to register 57. When bit b5 is equal to 1, this address is further incremented by one unit amount and rewritten to the storage device. A transfer to state C of the central unit 5 now occurs.

For this purpose, during state B the output 6 of the decoding circuit 62
27,62,o,62,. and 62,3 (FIG. 5) are all at level 0 because the outputs 62.3 (FIG. 5) correspond to the instruction TRA. This is because only those are energized. These outputs, via inverter circuit 134, energize the corresponding inputs of AND circuit 133 of block 63A. Furthermore, since the output 626 of the circuit 62 is also at the 0 level, the inverter 1
35 to input 1 of the OR circuit 137 of block 63A.
36 is energized. In this way, the AND circuit 133 of block 63A is activated and this
The input 138 of another AND circuit 139 of A is energized. The other input of this AND circuit 139 is a flip-flop F
Since it is connected to the output MB of B, the AND circuit DC is momentarily energized to TS, and as a result, the flip-flop F
C puts the output MC at level 1. At the same time, AND circuit D
C resets the flip-flop FB, as a result of which the central unit 5 moves from state 8 to state C. State C is used to propose the first operation number.

In fact, the AND circuit 140 (FIG. 8) of block 63B generates the command COM]0 at instant TS. This command opens gate circuit 141 (FIG. 2) of channel 55 to cause the transfer of the first address from register 50 to addressing register 41. When the address of the first operand belongs to the current page, bit b4 of the change signal of instruction TRA has the value 1, so that input 142 of AND circuit 143 (FIG. 8) is activated.

Additionally, input 144 of circuit 143 is energized through the inverter because output 626 of decoding circuit 62 is at level 0. Therefore, the AND circuit 143 is the command COM
18, which, as mentioned above, is distributed to the tribute register 71 (
2) to the address decoding circuit 45. On the other hand, when bit b4 is at level 0, command COM18 is not generated and no bit is sent to address decoding circuit 45, so that the page of storage that is selected is page 0.

At the same time, the contents of the memory device element selected by the address of the first arithmetic operation are retrieved and transferred to the output register 50.

At the instant TR (FIG. 4), the AND circuit 145 (FIG. 8) is energized and the command COM15 is generated. This command opens gate circuit 146 (FIG. 2) and causes the transfer of the first operand from register 50 to register 57. Finally, the command COM03 is sent to another AND circuit 146 (Fig. 8).
, which instructs the writing of the same information that has been read into the element portion of storage device 42.
Thus, in state C a first logical logical operation is carried out, which is rewritten into the element section in which it was previously located, and which is then transferred to register 57. A transfer of central unit 5 to state D then takes place.

In fact, the output 62, of the decoding circuit 62 has the value 1, so that
OR circuit 147 (FIG. 5) of block 63A is energized, resulting in input 148 of AND circuit 149 being energized. Since the other input 150 of AND circuit 149 is activated by flip-flop FC, flip-flop FD is activated by AND circuit DD at instant TS. At the same time, the AND circuit DD resets the flip-flop FB, so that the central unit 5 moves from state C to state D. State D is used to determine the address of the element section to which the first arithmetic number is to be transferred. In fact, at time TS (4th
), AND circuit 155 (FIG. 9) of block 63B generates a command COMOI, which is in turn
) and transfer the contents of register 32 to register 41. Since the contents of the register 32 have been increased by one unit amount during the period of state C, the addressing register 41 is a storage device following the element section from which these contents were read during the period of state C. The address of the element section is sent. When bit b6 of the change signal is 1, the current page is selected by command COM18 by AND circuit 156 (FIG. 9).

In fact, in this case the outputs 62,2 and 62,3 of the decoding circuit 62 are at level 0 and activate the AND circuit 156 along with bit b6 through two inverters. Via circuit 113 (FIG. 2), command COM 18 now transfers the contents of page register 71 to addressing register 45. Since the contents of registers 71 have not been changed during previous states, they define the current page. When bit b6 is 0, command COM18 is not generated by AND circuit 156 (FIG. 9), so no bit is sent to addressing circuit 45, causing page 0 to be selected.

At the same time, the storage element selected by the third character of the instruction, ie the address of the element to which the first operand is to be transferred, is read.

These contents are then transferred to output register 50.
Furthermore, the command COM03 (Fig. 9) is sent to the flip-flop FD.
and this causes the retrieved address to be rewritten to the selected device portion. When bit b7 of the change signal is 1, it is the band circuit 157.
Energize the input (Figure 9).

Since the output 62,2 is at level 0, the other input is also energized, and as a result, the AND circuit 157 becomes the OR circuit 158.
Therefore, the AND circuit 159 is activated. At this time, the AND circuit 159 generates the command COM06, which, as previously described, instructs the memory device input circuit 47 to rewrite the selected memory element portion with the address extracted therein and incremented by one unit amount. (Figure 2). During state ○, AND circuit 160 generates command COM04 at instant TR, which, as previously described, registers 3
2 (Figure 2) is increased by one unit amount. lastly,
In instant mS (Fig. 2) AND circuit DE (Fig. 5)
is energized, which directly sets flip-flop FE, with the result that output Mold goes to level 1.

The AND circuit DE also resets the flip-flop FD, so that the central unit moves from state D to state E. State E is used to transfer the first arithmetic operation stored in register 57 during state C to the element portion of storage device 42 whose address was read during state D.

In fact, at instant TS the command COMIO is generated by the AND circuit 161 (FIG. 10) of block 63B and this acts on the gate circuit 141 (FIG. 2) to be read out during state O and sent to register 501. This causes a transfer of the address to the register 41. When bit b6 is 1, AND circuit 162 (FIG. 10) outputs command CO.
M18 is generated, which is the contribution register 71 as mentioned above.
(FIG. 2) is caused to be transferred to the addressing circuit 45. Output 62 of the circuit 62 corresponding to the transfer command
Since the edge is in Peru, the OR circuit 163 (FIG. 10) is activated, and therefore the AND circuit 164 is activated. In this way, a command COM14 is generated, which determines the memory element selected by the decoding circuit 45 of the first operand contained in the register 57 which acts on the memory input circuit 47 (FIG. 13) in the manner described above. causing a transfer to the Department. Therefore, the third character read during state ○ from the element whose first operand during state B is controlled by the second character of the instruction that was executed during state B. The data is transferred to the element section corresponding to the address identified by. At the instant TS following the operation described above (FIG. 4), the flip-flop FE (FIG. 5) is activated, unless an interrupt by one of the peripherals 6, 7, 8 intervenes.
energizes input 166 of AND circuit 167.

The other input 168 is activated via the inverter 169 by the signal mT' indicating an interrupt, since it has the value 0. The output 204' of the AND circuit 167 energizes the flip-flop FA via the AND circuit DA,
As a result, the central unit moves from state E to state A and execution of the next instruction can begin. 2 Exchange (SC
A) A swap instruction (SCA) is identified by code 1010 and performs a transfer of the first character expressed within the element defined by the second character to the element defined by the third character; Swap the first four bits of the first instruction with the second four bits.

This instruction change signal has the same meaning as the instruction TRA change signal. The instruction SCA is confirmed by the decoding circuit 62,
This circuit 62 produces a signal 622 as an output.

This instruction is executed in exactly the same way that instruction TRA, described above, was executed. The only difference is that during state E, fund circuit 175 (first
0) generates the command COMI 9. This command acts on storage input circuit 47 in the manner described above to cause the transfer of the contents of register 57 (FIG. 2) to the selected storage element to ``swap the two groups of bits.'' 3 Compare (CFR) The Compare Instruction (CFR) is identified by code 1001 and it performs a bit-wise comparison between the first operand and the second operand, the result being stored in register 96 of central unit 5 ( (FIG. 2).

This instruction change signal has the same meaning as the previous instruction change signal. Command CFR is verified by circuit 62, which now generates a signal at output 633. Instruction CFR is executed in a similar manner to instruction TRA. The only difference is that during state E commands COM03 and COM2
This means that 0 is generated. In fact, here command C
OM03 is generated by AND circuit 176 (FIG. 10) and causes the writing of the contents of register 50, ie, the writing of the second operand, to the selected storage element. Command COM20 is generated by AND circuit 177 (FIG. 10) at instant T1 (FIG. 4) and is generated by memory input circuit 47 (FIG. 2) to perform a comparison of the contents of registers 50 and 57 as described above. ) and bit E=1 is sent to register 96 when the two contents are the same. 4. AND The instruction AND is identified by code 1111 and provides a bitwise AND between the first operand and the second operand.

This instruction change signal has the same meaning as the previous instruction change signal. The instruction AND is verified by circuit 62, which now produces signal 624 as an output. This instruction is executed in exactly the same way as instruction CFR. The only difference is that during state E, output 624 energizes AND circuit 178 (FIG. 10) and that AND circuit 1
78 generates the command COM21. This acts on the storage input circuit 47 to provide an AND between the contents of registers 50 and 57 as described above. The result of this comparison, represented by eight characters, is
The th operation number is entered and transferred to the storage device element section.

This means that during state E, the second operand is in register 41.
This is made possible by the fact that it exists in 5 Exclusive OR (ORE) The instruction ORE is identified by code 1110 and provides a bitwise exclusive OR between the first operand and the second operand.

The result of this operation is stored in the second arithmetic element in memory 42. The change signal for this command also has the same meaning as the change signal for the previous command. The instruction ORE is identified by circuit 62, which now produces as output a signal 625 and acts similarly to the instruction AND.

The only difference is that during state E, the output 625 is AND circuit 1.
79 (FIG. 10) and this circuit 179 generates the command COM22. As previously discussed, this command acts on the storage input circuitry so that an exclusive OR function is achieved. 6 Free transfer (TRL)
) A free transfer instruction (TRL) is identified by the code 1011 and is different from the case of instruction TRA by the third character from the element section identified by the second character in any page of storage 42. The first operation number is transferred to the identified element section.

The page to be transferred is bits b6 and b7 of the change signal.
Identified by When b6=b7=0, the address defined by the third character belongs to page 0, and b6=
0 and b7=1, it belongs to page 1, and when b6=1 and b7=0, it belongs to page 2, b6=b7=1
When , it belongs to page 3. Bit b4 of change signal
and b5 have the same meaning as bits b4 and b5 of the change signal of instruction TRA. The command TRL is identified by a circuit 62 which now generates as an output a signal 62,2 and which during state D outputs 62,2.
, 2 energizes the OR circuit 180 (FIG. 9) and this circuit 180 generates the command COM27.

This command COM 27 acts on the gate circuit 185 (FIG. 2) to transfer to the decoding circuit 45 bits b6 and b7 of the change signal representing the address of the page in the memory device to which the first operand is to be transferred. {o} Second group of instructions For this group, represent the first operand and the second
Contains instructions regarding constants indicated by the th character.

These instructions are Transfer Constant (TRC), Transfer Constant Free (TLC), and Compare Constant (CDC). These commands are sent to states A, B, D, E by the central unit 5.
executed according to the order of The time required for these executions is therefore 8 microseconds. These instructions are output from the decoding circuit 62 at outputs 62, o, 62, 8, and 62, respectively.
、． It is related to These are instructions (TRA), (TRL) and (CFR) except that state C is not performed.
) is performed in virtually the same way as

In fact, the operations performed in states A and B are identical to those performed by the corresponding initial set of instructions. More specifically, during state A the code for this instruction is issued and during state B the second character, here representing a constant, is read. Since the constant is now decremented during state B, there is no need to perform state C, which is used to decrement the first operand in storage 42 by the corresponding instruction of the first group. Here output 62,
o,62,3,62,. Since one of them is always at level 11, the OR circuit 186 (FIG. 5) is energized.

This circuit energizes input 187 of AND circuit 188, and the other input 189 is energized by flip-flop FB, so that AND circuit 188 activates input 187 of AND circuit 188 via flip-flop DD at time TS (FIG. 4). FD
to support. The AND circuit DD is further a flip-flop F
B and acts on the corresponding reset circuit, resulting in a change from state B directly to state O. 1 Transfer Constant (TRC) The Transfer Constant instruction (TRC) is identified by code 1100 and it performs the transfer of the constant represented by the second character of the instruction to the element identified by the third character of the instruction.

This constant can be incremented or not incremented by one unit after execution of the instruction under the control of bit b5 of the change signal. When b5=0, the constant remains unchanged; when bit b5=1, the constant is increased by one unit amount. The storage address defined by the third character can be incremented or not incremented by one unit amount under the control of bit b7 of the change signal.

When b7=0, this address is left unchanged, and when b731, this address is incremented by one unit amount. It should be noted that bit b4 of the change signal is always 0 and is not used.

Bit b6 of the change signal is therefore used to define the page of storage to which the address belongs to be represented by the third character. When b6=0, this address belongs to page 0, and when b6=1, this address belongs to the current page. The command TRC is verified by circuit 62;
This circuit 62 then produces as output a signal 62,o.

As mentioned above, this signal moves the central unit 5 directly into state D. During this state, the same operation as described for instruction TRA takes place, ie, the presentation of the third character of the instruction. During state E, a constant is transferred to the address defined by the third character as for instruction TRA. 2 Free transfer of constants (TLC) The command (TLC) for free transfer of constants is code 01.
00 and this causes a transfer to the address defined by the third character of the constant defined by the second character.

This instruction change signal has the same meaning as the instruction TRL change signal. During states A and B, the same operations as described for instruction TRC are carried out, namely the invocation of instruction and constant code. This command is confirmed by circuit 62, which now produces as output signal 62,3.

This signal moves the central unit 5 from state B directly to D, as described above. During this state, the third character of the command is presented to the same aircraft as in the case of command TRL. Condition E
During this period, a constant is transferred to the address defined by the third character in the same way as for the instruction TRA. 3 Constant Comparison (CDC) The instruction for constant comparison (CDC) is identified by code 1101 and performs a bitwise comparison between the constant represented by the first operand and the second operand.

The result of this comparison is represented by bit E=1 when these two operands are the same, and by bit E=0 when they are different. This bit is placed in register 96 of central unit 5 (FIG. 2). instruction CD
The change signal of C has the same meaning as the change signal of command TRC.

The command CDC is confirmed by a circuit 62, which now generates as output a signal 62, so that the central unit 5 moves from state B to state D. During this state, the second arithmetic number is proposed as in the case of the instruction CFR. Finally, during state E a comparison is made between this constant and the second operand. 1. Third group of commands For this group, the state A,
Instructions executed in the order of B and C belong to it.

The time required for these executions is therefore 6 microseconds. These instructions are the command to receive a character from a peripheral (CDP), the command to send a character to a peripheral (CAP), and the skip command (SAL). These instructions have only one address and are therefore formed by two characters.

The first character contains a code characterizing the type of instruction within the limits of the group and associated change signals. The second character contains the storage address of the operand.

1 Command to accept characters from peripheral device (CDP) Command to accept characters from peripheral device (CDP) is code 0.
110 and this is the change signal bit b6
and transfers the operand from the peripheral device defined by b7 to the storage device address defined by the second character.

Bit b4 of the change signal defines the page of storage to which the address defined by the second character belongs. When b4=0, this address belongs to page 0, and when b4=1, it belongs to the current page. Furthermore, when bit b5=0, this address remains unchanged after execution of the instruction, and when bit b5=1, this address is incremented by one unit amount. During state A, the command CDP
is verified by circuit 62, which now produces signal 628 as an output.

During state B, the second character of the instruction is expressed as in the first and second groups of instructions. 2 of this command
The th character identifies the element part of the storage device 42 in which the character transmitted by the peripheral device 6, 7 or 8 defined by bits b6 and b7 of the change signal is to be recorded.
The central unit then moves from state B to state C "because in the AND circuit of block 63A (FIG. 5) 39 is energized by the OR circuit 133 and the outputs 626, 627 of circuit 63
,62,o,62,. This is because 62,3 is zero.

During state C, output 628 is output to AND circuit 197 (eighth
) is activated, and this AND circuit 197 is connected to the command COM17.
This command COM17 is sent to the storage device input circuit 47.
At this point, the characters present in channel 46 (FIG. 2) are transferred to the element portion of storage element portion 42 which was exposed during state B. During these operations, the central unit 5 returns to state A.

In fact, since the output 628 is on the bell 1, the OR circuit 1
98 (FIG. 5) is always energized. As a result, one input 199 of AND circuit 200 is energized, and the other input 201 is energized via inverter 169. In this case, the AND circuit 20 activates the AND circuit 202 which has been activated by the output 203 of the flip-flop FC. The output 204 of the AND circuit 202 energizes the flip-flop FA at the moment TS (FIG. 4),
As a result, the central unit moves from state C to state A. 2
Command to send a character to a peripheral device (CAP) The command to send a character to a peripheral device (CAP) is code 0.
111 and which causes the transfer of the arithmetic change signal addressed by the second character to the peripheral device defined by bits b6 and b7.

These bits have the same meaning as the corresponding bits of instruction CDP. During state A, this command is acknowledged by circuit 62, which now generates signal 629 as an output. The second character of this command, issued during state B, now identifies the address of the character to be sent to the peripheral defined by bits b6 and b71 of the change signal.

Again for this command, the central unit moves from state B to state C due to the fact that OR circuit turtle 33 of block 63A (FIG. 2) has been activated. During state C, the character of the address selected during state B is presented and simultaneously stored in register 50 (FIG. 2).
Additionally, output 629 energizes AND circuit 195 (FIG. 8), which generates command COM08. This command is sent to the selected peripheral device and sends it to the central device 5.
Prepare to receive characters sent from. After these operations, the central unit 5 is in state A as in the case of command CDP.
Return to 3. A jump instruction (SAL) is identified by the code 0010 and it is inherited during the course of a program where two instructions are being executed, even if they are not. Make it possible to move to one command.

The second instruction of instruction SAL indicates the storage address of the next instruction to be executed by central unit 5. During states A and B, the same operations are performed for instruction SAL as described for the previous instructions.

On the other hand, bits b6 and b7 of the change signal define the page to which the element defined by the second character of this command belongs, as well as for commands TRL and TLC. This storage element section now contains the first character of the instruction to be subsequently executed. Skipping can be conditional or unconditional.

For example, "In the comparison made by the command CDC,
The result is represented by bit E, which is fed into register 96 (FIG. 2) of central unit 5. In this case, the command SA
L is conditioned by either bits 8:0 or bits E=1 according to the particular arrangement of the program in progress. The value of bit E that conditions execution of a jump instruction is identified by bits b4 and b5 of the change signal of this instruction. More specifically, there are two cases. That is, if b4=b5=0 for the instruction SAL conditioned by the value E=0 that occurs when E:0, and
b for a jump instruction conditioned by the value E=1
This is the case when 4=0 and b5=1. The second character read and recorded in register 50' during state B now indicates the storage address at which the jump is to be made.

Block 63A is adapted to issue in a well-known manner an output signal CV representing the function:
Figure 5).

CV=b4+b5・E+b51E Therefore, CV is b4=b5=E=0 or b4
=0 and it is 1 when b5=E=1.

When the jump condition is not verified, i.e. when E=1 and E=0 in the above two cases, respectively.
Signal CV=0. At this time, the AND circuit 210 of block 63A is activated because the two inputs 211
and 212 are on bell 1 and the output 626 of circuit 62
This is because it is energized. As a result, OR circuit 2
13, the AND circuit 210 energizes the input 214 of the AND circuit 215, and the other input 216 is energized by the inverter 169. In this case, the AND circuit 215 energizes the input 217 of the AND circuit 218, and the other input 219 energizes the output 220 of the flip-flop FB.
'This is connected. As a result, output 221 of AND circuit 218 sets flip-flop FA through conductor 204 at instant TS. Therefore, when the jump condition is not verified, the central unit 5 returns from state B to state A;
As a result, the jump instruction is not executed. On the other hand, when the jump condition is verified, i.e.
If two cases are not considered, the signal CV is at level 1 when bit E has the values 0 and 1, respectively. This signal therefore energizes the OR circuit 137 and, via the AND circuit 137, the input 138 of the AND circuit 139. The other input of this circuit is activated by the flip-flop FB as long as the central unit 5 is in state B. As a result, the flip-flop FC is connected to the instant TS and the AND circuit DC
energized through. The central unit then moves from state B to state C, during which time the command COMIO is generated by the AND circuit 140 (FIG. 8) and this command transfers the contents of register 50 (FIG. 2) to addressing register 41. command the transfer of

In this way, the storage device address at which the jump is to be performed is stored in register 41. At instant TI, the gate circuit 226 (FIG. 8) generates a command COM12, which opens the gate circuit 221 (FIG. 2) and places bits b6 and b7 in the page register 71 indicating the page to which this address belongs. Forward. The AND circuit 226 further includes the command CO
MI I is generated, which is adapted to inhibit the counting circuit 44 (FIG. 2). In this way, when the AND circuit 227 generates the command COM04 at the moment TR, the same address stored in the register 41 will have the same address stored in the register 3
2, which is the second character that indicates the address at which the next instruction will begin execution. Once the instructions executed during state C have completed, the central unit 5 moves to state A as described for the instructions CDP and CAP.

During state A which then follows, the second character of the instruction and the address defined by bits b6 and b7 of the change signal are fed into addressing registers 41 and 71. An unconditional jump occurs, for example, when some peripheral interrupts a program during execution.

For example, an interrupt is caused when a peripheral device performs an operation instructed by a command CAP sent to the peripheral device by the central device 5, or when a peripheral device introduces a character to the central device 5 by a command CDP. This interrupt requires the central unit 5 to store a jump instruction in the storage element, which makes it possible to return to the last address taken into account by the program before the interrupt. This jump instruction is therefore not conditioned by the value of bit E. This in this case has a value of 1
and bits b4 and b5 of the change signal which take 0. At this time, the output signal CV of circuit 105 (FIG. 5) is always at level 1, regardless of the value of bit E. In this case, the same operations are performed by central counterfeit 5 as previously described for conditional jump instructions whose conditions are verified. Furthermore, there is an unconditional jump instruction called a "return jump" instruction, the meaning of which will be explained below. This instruction is identified by bits b4 and b5 of the change signal;
Both of these bits take the value 1. Signal CV is always at level 1 in this case, so that the same operations as previously described for conditional jump instructions whose condition is verified are performed by the central unit. 9. Fourth group of instructions To the fourth group of instructions belong the instructions which are executed by the central unit 5 in the order of states A and B.

This group also includes conditional jump instructions when the jump condition is not verified as described above. Also belonging to this group is the command to send a command to a peripheral (COP), which is identified by the code 0101 and which is defined by bits b6 and b7 of the change signal in the way described for the commands CDP and CAP. forwards the command with the code defined by the second character to the peripheral device specified.

Note that bits b4 and b5 of the modify signal are not used by this instruction and are therefore always at level 0. During state A, instructions are now decoded by circuit 62, which energizes output 627.

During state B, the second character of the command representing the command to be sent to the selected peripheral is raised and transferred to register 50. Two AND circuits 230 and 231 (FIG. 7) energized by output 627 now receive commands COM08 and COMO, respectively.
Generates 9.

Command COM08 causes the transfer of the contents of register 50 to the peripheral, and command COMO9 is sent directly to the peripheral to indicate that the character coming from the central unit is a command and not a write character. After performing these operations, the circuit 21 is energized by the output 627 to the circuit 62 at the instant TS.
3 (FIG. 5) sets flip-flop FA in the same manner as previously described for jump instructions where the condition is not verified, resulting in the central unit moving from state B to state A.

The characteristics of each instruction are summarized in the summary table below, which includes the symbol for each instruction, the corresponding name, the code associated with that instruction, the corresponding output of circuit 62, bit b4 and b5 and their meanings are indicated.

Table B shows the machine operating state in which each command is executed by the central unit 5, the group to which the command belongs, the values of bits b6 and b7 and their meanings. Ship Ship White Ship qW Interrupt As mentioned above, an interrupt command during the execution of one of the aforementioned commands reaches the central unit 5 from any one of the peripheral devices connected to the central unit 5 (FIG. 2). .

Execution of the currently executing program is interrupted to execute the current instruction and another series of instructions is executed. The machine operating states used to accomplish the interrupt are states F and G, so the interrupt is accomplished in 4 microseconds. When one of the peripheral devices 6, 7 and 8 sends an interrupt signal NT, the logic circuit 31 (second
(FIG. 5) energizes conductor 76, which introduces signal melon T into block 63A (FIG. 5).

If the first or second group of instructions (which ends in state E) is in the process of being executed at the moment the signal T is sent, the central unit 5 executes this instruction until this state is reached. continue. Then, as described above, the output ME of the flip-flop FE is energized and the AND circuit 233
input 232 is energized and the other output 234 of the circuit is energized.
is activated by signal INT. Therefore, AND circuit DF
The circuit 233 connects the instantaneous TS to the flip-flop FF via
as a result of which the central unit moves from state E to state F'. If a third group of instructions (whose execution ends in state C) is in the process of execution at the moment when the signal INT is sent,
Interrupts are only performed when this state is reached.

In fact, the output MC of the flip-flop FC is activated, and as a result the input 203 of the AND circuit 248 is activated.
The other input 235 of this circuit is activated only when AND circuit 236 is activated. This occurs only when both conductor 76 and the output of OR circuit 198 are at level 1. This OR circuit has its inputs as commands SAL and CA.
Outputs 626, 628, 62 corresponding to P and CDP
9 is activated when an instruction ending in state C is in the process of being executed. In this way, state C
It never occurs that the execution of an instruction that does not end in is interrupted in state C by the signal mT. When AND circuit 248 is activated via AND circuit DF, the central unit moves from state C to state F'. Similarly, when a fourth group of instructions ending in state B is in the process of being executed, signal mT takes effect only when this state is reached.

In fact, the output 220 of the flip-flop FB energizes the input 240 of the AND circuit 241, the other input 242 of which is energized by the AND circuit 243. Circuit 243 is activated only when both signal INT and the output of OR circuit 213 are present. This only occurs when a conditionally unverified jump instruction, or instruction COP, is in the process of being executed. In this way, the possibility that the execution of an instruction that does not end in state B is interrupted by signal T in state B is prevented. Therefore, AND circuit 241
is activated, the central unit changes from state B to state F'
I'm moving. In each case, during state F, the storage elements selected during the previous state are proposed in a known manner, as if the central unit 5 had returned to state A. . The contents of this element section are transferred to the output register 50' in the manner described above. At this time, the AND circuit 245 (FIG. 11) generates the command COM25 at the moment TM (FIG. 4), and this command is sent to the gate circuit 246.
(Fig. 2) to transfer the contents of register 32 to register 5.
Transfer to 7.

These contents correspond to the storage address of the last instruction in the process of execution. At the same time, the command COM25 is
All flip-flops of 1 are placed at level 1 and act on their respective set circuits. In this way, the element section 2
55 is selected because the signal shape 11 of register 41
This is because 111111 exactly corresponds to this element portion. The page to which this element section belongs is page 0, because the contents of register 71 are not transferred to addressing circuit 45 and gate circuit 113 is closed.

In fact, during state F the command COM18 to open the gate circuit 113 is not generated, as a result of which the signal shape 00
is present in the register 71. At this time, the output M' of the flip-flop FF generates a direct command COM23 (Fig. 11), and this command is sent to the memory device input circuit 47 (
2), output channel 481 has the character 001011 followed by the bits contained in register 71.
send in.

For this purpose, the logic circuit 47 includes a circuit 101 (FIG. 13) formed by, for example, six flip-flops, these flip-flops having the bit shape 00101.
1 are obtained at their outputs by the command COM23. Circuit 101 for this bit shape
adds two more bits coming from register 71 through input channel 82. These eight bit shapes are then transferred to output channel 48. Output channel 48 constitutes the input of storage device 42 (FIG. 2), so that the shape of these eight bits is stored in register 41.
The data is written into the element section of the memory device 42 selected by the address included in the address. This address is page 0 as mentioned above.
This corresponds to the element section 255 of . As mentioned above, the character 00
1011 defines a "return jump" instruction, while dot in register 71 defines the current page. At the moment TR (Fig. 4), the AND circuit 247 (Fig. 11) outputs the command COM04.
, and this command causes register 4 to be incremented by one unit amount.
1 content, that is, the character 000 corresponding to element part 0 of page 0
00000 is sent to register 32. Therefore, state F
During this period, a return jump instruction is written to the element section 255 of page 0, and the address 00 is written to the addressing register 32.
000000 force is sent. At the instant TS (FIG. 4) following these operations, the central unit advances to state G because the band circuit (FIG. 5) is energized.

During state G, another AND circuit 250 (FIG. 12) generates a command COMOI for instantaneous information mS, which command corresponds to the contents of register 32 for register 41, that is, element section 0 of page 0. Commands address transfer. At the instant TN (FIG. 4) following the instant TS, a further signal RO is generated in the AND circuit 251 (FIG. 12), which resets the flip-flop of the register 71 (FIG. 2) in a known manner and thus and select Tribute 0. The output MG of the flip-flop FG also generates a direct command COM14 (FIG. 12), which acts on the circuit 47 in the manner described above to determine the address in the memory of the last instruction in the execution process (this address is (included in register 57 (FIG. 2)) is transferred to element section 0 of page 0 of storage device 42. Therefore, due to the operation just described, an instruction for returning to and jumping to the page to which the address of the instruction currently being executed belongs is edited in the element section 255 of page 0 at the moment the interrupt occurs.

This address is further stored in the element section 0 of the contact 0. After these operations, another AND circuit 252 (
FIG. 12) generates the command COM26 at the instant TR following the instant mm (FIG. 4).

This command acts on the gate circuit 253 (FIG. 2) to transfer the contents of the logic circuit 31 to the register 32, in other words to transfer the address corresponding to the peripheral device 6, 7 or 8 that caused the interrupt to the register 32. Send it in. Through channel 33 the contents of register 32 are simultaneously transferred to reset logic circuit 3.
Sent to 4. Furthermore, command COM26 acts on gate circuit 255 to transfer the possible comparison bit E from register 96 to register 97, where it is stored for the entire duration of the interrupt. In fact, it is possible to use register 96 during the interrupt itself, for example when the interrupt contains instructions CFR or CDC. When the signal INT is generated during the course of a command by two or more of the peripherals 6, 7, 8 at the instant TI following the instantaneous beat R (FIG. 4), the asodo circuit 256 (FIG. 12) A command COM24 is generated to open the gate circuit 257 (FIG. 2).

This therefore causes a reset of the flip-flop in register 30 corresponding to the higher priority peripheral that caused the interrupt. In this way, after execution of the program corresponding to the interrupt introduced by this peripheral, another possible interrupt corresponding to a lower priority peripheral can be introduced again. After these operations, the central unit 5 at this moment switches on the flip-flop FG.
AND circuit DA (Fig. 5) attached by the output MG of
Returns to state A at the instant TS following the instant TI as long as is energized.

Therefore, execution of the first instruction whose address has been stored in the register 32 among a series of instructions related to the interrupt is started. As a result, during state A, in which the central unit 5 is at the end of an interrupt, inter alia a command COMOI is generated, which command transfers from register 32 to register 41 the address corresponding to the first instruction to be executed. Make it possible. This instruction, together with other instructions in the series of interrupt-related instructions, is then executed under the same conditions as described above, according to the type of instruction itself. In order to restart execution by the central unit 5 of an instruction interrupted by the interrupt, the last instruction of the interrupt-related lotus instructions always commands an unconditional jump to the address of the element section 225 on page 0. It is.

As described above, this element section stores the first character of an instruction that commands a return jump to the address determined by the second character of the instruction stored in element section 0 of page 0 following element section 5. ing. A return jump command is then executed by the central unit 5 in the manner described above, in effect returning the central unit 5 to the same condition it was in at the time of the interrupt.

More precisely, at the end of a return jump instruction, register 41 is recorded with the address defined by the second character of the instruction itself, ie the same address that central unit 5 occupied at the time of the interrupt. Additionally, during state B of the return jump instruction, bits b4 and b5 of the change signal
Since both take the value 1, command COM13 is generated by AND circuit 258 (FIG. 7). This directive is
bit E is transferred from register 97 to register 96 by acting on register circuit 259 (FIG. 2). Register 96 therefore stores the bit E that was present at the moment of the interrupt. Once the return jump instruction has completed, a return to state A occurs, which causes the program interrupted by the interrupt to continue. M Typewriter control device Control device 9 for typewriter 6 (Fig. 1 and Fig. 14)
is adapted to control the exchange of data and instructions between the typewriter 6 and the central unit 5.

The input/output device 12 of the typewriter 6 has an input device 12' for receiving the code of the character to be printed and the code of the function character from the control device 9. These codes are formed by 8 bits, 6 of which are used to define a character, 1 of which is a shift bit to define uppercase and lowercase letters;
One bit may be used as a parity bit, for example. The six bits of the character act on a series of six electromagnets to effect the selection of the character or function in a known manner. The device 12 furthermore has an output device 12'' adapted to transmit seven character and function codes which are entered in a known manner by means of a keyboard 270 and a keyboard 271, respectively, towards the control device 9.

Transmission of these codes is accomplished by switching six switches of any known type not shown in FIG. The function conductor 65 connecting the control unit 3 to the central unit 5 is connected to the typewriter 6 by the decoding circuit 65 in the manner described above.
is activated by the decoding circuit 66 only when .

Data is further exchanged with the central unit 5 through an output channel 46 connected to a storage input circuit 47 of the central unit 5 and an input channel 51 connected to an output register 50 of the central unit 5. Input channel 51 and register 5
The data present in 0 is transferred to the 8-bit type register 273 of the control device 9.

The operation of the control device 9 is controlled by the central device 5 by external commands COP and CAP for receiving write characters or commands from the central device 5 and by commands CDP for transmitting characters to the central device 5. More precisely,
The control device 9 can be placed into a transmitting or receiving state by the central device 5 using a command COP. In fact, as mentioned above,
Command COP generates two commands COM08 and COMO9, which are passed through conductor 269 to control device 9.
is sent to the decoding circuit 274. This circuit 274 decodes the received command in a known manner. This command is the command COM
08, circuit 274 energizes output COM08', and when it is command COMO9, it energizes output COMO9'. These outputs are sent to the control device 9
are placed in the transmitting state and receiving state, respectively. Central device 5
proposes to receive a character from the control device 9 with the command CDP, it sends the command CDP to the control device 9.
OP is sent, and this command COP generates command COM08.

This command, together with the signal present on conductor 652 selecting control device 9, energizes AND circuit 275, which acts on the reset circuit of flip-flop 276 to indicate to it that control device 9 is in the transmitting state. let them do it. When the operator activates a character key on the keyboard 270, the output device 12'' is connected to the conductor 2 in a known manner.
77 to energize an AND circuit 278, which is further fed by a flip-flop 276.

The output signal of the AND circuit 278 is the flip-flop 279
opens the gate circuit 280 so that characters entered from the keyboard 270' are transferred to the output channel 46. Conductor 277 Hashijita 3
0 (FIG. 2) and is connected to input 30a of register 3
0, causing an interruption of the operation of the central unit 5 in the manner described above. The central unit 5 then jumps to the memory address corresponding to the typewriter 6 identified by the conductor 30a and decoded by the circuit 31. This address contains the first character of the command CDP, so that the central unit 5
It is designed to receive characters that exist in . When the operator activates a function key on keyboard 271 (FIG. 14), the keyboard emits a signal on lead 285, which causes central unit 5 to send an interrupt signal in the same manner as lead 277.

It is therefore prepared to receive the characters of the function present on channel 46. Conductor 285
further energizes AND circuit 282, which acts on the set circuit of flip-flop 279 to open gate circuit 283, which places channel 284 in communication with output channel 46. put. Keyboard 271 also generates signals corresponding to actuated function keys on conductors 2861.

This signal acts on the decoding circuit 287, which supplies the code corresponding to the actuated key. This code is formed from eight bits, of which bits b4, b5 and b6 are always active and distinguish between function characters and printable characters. This code is sent to output channel 46 via channel 284 and through gate circuit 283. When it is desired to send command characters to the control device 9, the central device 5 sends the command COMO9.
A command CAP is sent to it through channel 57 to generate the command CAP.

This command is decoded by decoding circuit 274, and this circuit 2
74 energizes the output COMO 9' at this time. This output is passed through an AND circuit 290 to a flip-flop 276.
, which places the control device 9 in the receiving state. This state is identified by the output signal R of the AND circuit 291, which is momentarily activated by the flip-flop 276. The reason for the activation of the AND circuit 291 in the immediate N is that at this moment during the command CAP, the central unit 5 has already discussed the character to be sent to the peripheral in the memory 42, as described above. and then control it through the input channel 57 of bag counterfeit 9
This is because the data is stored in the register 50 (FIG. 2) connected to the register 50 (FIG. 2). Upon execution of instruction CAP, the characters present in channel 57 are stored in register 27 by central unit 5.
Transferred to 3. When this character is a function character identified by the 0 bits b4, b5 and b6 as described above, the decoding circuit 299 for these bits connected to the register 273 generates a signal Y; On the other hand, if the character is a printed character, decoder circuit 274 generates signal W rather than signal Y in well-known manner. In the first case, gate circuit 295 is opened, so that the characters present in register 273 are passed through channel 236 to decoding circuit 287.
sent to.

This circuit 287 generates a signal at an output 297 which is sent to the input circuit 12' of the typewriter 6 through a gate circuit 298 which is opened by the signal Y. The gate circuits 295 and 298 can obtain the receiving state (R=1) and the character is the function character (W=0 at Yhi1).
) should be noted that it is only opened when When the character present in the register 273 is printable, the signal W activates the gate circuit 300, so that this character is transferred to the input circuit *12' of the typewriter 6.

In the gate circuit 300, the control diamond 9 is in the receiving state (R=
It should be noted that it is opened only when 1) and the character is printable (W:1 and Y:0). What has been said above for a single character applies both to subsequent characters received and to subsequent characters sent.

Each time input circuit 12' receives a character, it generates a signal on conductor 301, which introduces an interrupt to central unit 5 via input 30a, so that central unit 5 receives another character. Prepare to send.

Based on the contents of the storage element as identified by the interrupt, the central unit 5 can now send a command or character with the next command.

For example, when the control device 9 is in the transmitting state, the central device 5
sends a command COP so that transmission continues, or a command CO commanding reception so that the control device 9 is placed in a receiving state.
You can send P. Of course, the letter is the next command C
It is sent from the central device 5 by the AP. M Command keyboard control device The command keyboard 8 is a control device 11 corresponding to a large number of commands.
is used to send the data to the central unit 5 through the

More specifically, the keyboard has a general switch, not shown, for supplying power to all devices of the printing mechanism. It furthermore has the well-known start button, which starts the operation of the device in such a way as to send as input a first set of instructions to the memory 42 of the central unit 5 in the manner described above. These instructions may also cause a particular group of instructions, referred to as "input" instructions, to enter as input into memory 42, which may cause any other group of instructions to enter memory 42 as input, in a manner to be described below. Make it possible. The keyboard 8 further has an indicator lamp which is turned on by a command coming from the central unit 5. For this purpose, this is done in the same way as described for the control unit 9 of the typewriter 6, since the exchange of commands between the central unit 5 and the keyboard 8 takes place via the command COP. It acts on More specifically, the decoding circuit 65
(Figure 2), the command COP selects the keyboard 8,
It accepts only the specific command represented by the second character of the command COP and formed by the 8 bits all at level 1. This command acts on the keyboard 8 in the manner described above and lights up the indicator lamp. The keyboard 8 is adapted to send only one interrupt signal to the central unit 5 by actuation of an interrupt key connected to the input 30c of the circuit 30 (FIG. 2).

The interrupt key then conditions the central unit 5 to execute the sequence of commands associated with the interrupt originating from the keyboard as described above. WiD magnetic tape storage device controller A controller 10 of the tape storage device 7 controls reading and writing of addresses, programs, and data in the storage device 7 .

The storage device 7 is formed of a closed loop magnetic tape 310 (FIG. 15) contained in a cartridge.

The cartridges are replaceable, so the device can include any number of cartridges. The tape 310 has a series of parallel tracks P1, P2......PN
and the data here is block B1...
B256 blocks are recorded in series, and each block corresponds to one line of printing. Each block is separated from neighboring blocks by an unrecorded area called an erased area. Each storage block has a fixed length and contains 80 characters each consisting of 8 bits.

The characters in each block are sequentially fixed numbers 0 to 79 (first
Figure 6) is attached. Characters 6 and 78 are used to record data related to the printing of the corresponding line,
Characters without 0 and 5 are used as function characters. More specifically, the first function character is selected by the central unit 5 to select the one track of track P1...PN that contains the block in which the next character is to be recorded. Contains constants used. The address of this track within the limits of the selected track is defined by the second character, whereas the cartridge itself is identified by the third character. The fourth character indicates the number of characters each line can contain.

This number can be selected by the operator to increase or decrease the length of the print line, as described below. The fifth character indicates the number of characters actually included in the printed line.

The sixth character indicates the code for the function to be performed on that line, such as centering, underlining, etc.

The 7th digit character is a vertical parity check character related to the remaining 79 characters.

Data track P1......In addition to PN, the tape 310 has data block address 11...1
Also includes one track PO containing 256.

Each address block 11...1256 is formed from 25 characters, only one of which is used to contain the address of a data block or program block. Since this character contains 8 bits, it is sufficient to define one data block from the remaining 255 in the selected track. The remaining 24 characters in each address block are used as function characters. The first three of these characters represent two constants used specifically to identify address blocks and program blocks, respectively. In fact - the track PO has 7 between one address and the next.
One program BP1 formed from 0 characters...
-BP256 is recorded, and the characters of the operation command of the printing mechanism are recorded here. Each address block 11...
...1256 is used to select the block of data that geometrically follows it in the direction of tape progression.

For example, the data block B2 recorded on the track PI......PN' is selected by the address block 12. Therefore, in order to unambiguously select a data block, one must first select the track to which it belongs and then, within the limits of that track, select the block itself from the remaining 255 blocks. The control device 10 is connected to the register 50 (FIG. 2) of the central unit 5 through an input channel 51 (FIG. 17) and to the input circuit 4 of the storage device 42 through an output channel 46.
7 is connected.

More specifically, the two channels 51 and 46 are connected to the control device 10 through two gate circuits 316 and 317.
It is connected to the register 318. Register 318 can exchange the bits stored therein with shift register 319 via two gate circuits 320 and 321. Register 318 further transmits the bits received from register 318 to decoder circuit 325, which generates a plurality of commands in response to the bits received from register 318. The decoding circuit 325 acts on a timer 326, which generates a time signal that controls the operation of the control device 10. The decoding circuit 325 can further be activated by a signal present on a conductor 327, which signal is at level when the start button of the keyboard 8 is actuated.

The decoding circuit 325 is connected via a gate circuit 328 to a four-position register 329 which is connected to the conductor 33.
01 signal which acts on the output head of tape storage 7 to select the track corresponding to the bit contained in that register. Register 319 is further connected to a further decoding circuit 335 which produces a signal at its output 336 when an address is present in register 319.

This signal present at output 336 acts on circuit 337,
This circuit 337, when activated, sends an interrupt signal to input 30b of circuit 30 (FIG. 2) of central unit 5. The register 319 is connected to the signal shaping device 33 by the gate circuit 338.
9, this circuit 339 is adapted to supply an output 3401 with a signal corresponding to the character contained in the register 319 from time to time.

These signals are used by a write device (not shown) of the storage device 7. Register 319 is a readout device 3 of known type.
42, this lifting device 342 is connected to the tape 3101
The recorded bits are serially connected and connected to conductor 3.
43 to the register. The exchange of data between the central device 5 and the control device 10 is carried out by the commands COP, CDP, CAP issued by the central device 5.
This is done by

The control device 10 is initially in a reset or inactive state. This situation is symbolized in FIG. 18, which diagrammatically shows the sequence of actions carried out by both the central unit 5 and the control unit 10. Control device 10
Actions performed by are shown as rectangular blocks, and logical decisions or alternative actions are shown as diamonds. The actions carried out by the central device 5 are indicated by arrows, which symbolically represent the opening of a gate circuit so as to allow the control device 10 to be transferred from one operating state to another. To write or extract information from the tape 31 of the storage device 7, the central device 5 sends a so-called "selection" command COP to the control device 1 in the manner described above.

When b6=0 and b7=1 in the first character of the instruction, the selected peripheral device is memory device 7, and these bits act on decoding circuit 65 (FIG. 2) of central unit 5 to (FIGS. 2 and 17), which energizes the input of AND circuit 350 of controller 10 (FIG. 17). The other input of AND circuit 350 is in state B
Command COM08 generated by command COP during
energized by. In this way, gate circuit 316
is opened, so that two of the instructions present on channel 51
The th character is introduced into register 318. This second character is simultaneously introduced into the decoding circuit 325, which circuit 3
25 is the conductor 352 when the so-called selected character is confirmed.
A signal is generated to start tape 310. This selected character is identified by the fact that bits b5, b6, b7 have the value 001. At the same time, the decoding circuit 325 generates a signal L in a known manner, which signal is transmitted to the gate circuit 3.
28 and transfers to register 329 the first four bits of the character present in the decoding circuit.

These bits are track P1 of tape 310...
...Used to select one track from among the PNs. Register 329 now sends a signal on conductor 330 that is used by storage device 7 in a known manner to select a track. Furthermore, the signal L pre-prepares the read circuit 342 to read the address in the manner described above.

Circuit 342 serially sends to register 319 the bits of the first character of the first address block to be read. These operations are symbolically represented by block 353 (Figure 18). It is equally possible to put the control device 10 into the addressed state by actuating the start button of the keyboard 8.

This button or key acts on circuit 325 in such a way as to simulate the selection command COP. Circuit 325 then performs the same operation as described above. As a result, controller 10 likewise assumes the logical state represented by block 353. As previously mentioned, address block 1, . . . 1256 of tape 310 is identified when the first three characters represent the corresponding constant.

Therefore, when the decoding circuit 335 (FIG. 17) verifies that the block read is an address block, it energizes the circuit 337, which is in turn connected to the circuit 30 of the central unit 5 (FIG. 2). Send an interrupt command on input 30b. These operations are symbolically represented by blocks 354 and 3
55 (FIG. 18). The central unit 5 now executes an interrupt. This interrupt causes the central unit 5 to execute a jump instruction to the element section corresponding to the memory device 7 in which the instruction CDP is recorded among the element sections of the memory device 42 (FIG. 2).

Central unit 5 then sends command CDP on channel 51 to register 318 (FIG. 17) of central unit 10. This command is decoded by circuit 325, which issues a signal M that places controller 10 in an address sending state (block 356 of FIG. 18). Signal M also opens gate circuits 321 and 317 and the extracted address is passed from register 319 to register 318 and from there to channel 46 and storage input circuit 47 (FIG. 2).
The data is transferred to a predetermined element section of the core storage device 42 via the. The central unit 5 then executes the command CDC, which causes the central unit 5 to store the address received from the control unit 10 in the register 5 representing the address of the block.
7 (FIG. 2).

If the result of the comparison between these two characters is negative (bit E: 0), the central unit 5 does not send any commands from the control unit 1 (logic decision 357 in FIG. 18), so that Controller 1 sends the next address in the manner previously described and the operations described in blocks 354, 355 and 356 of FIG. 18 are repeated.If the result of the comparison between the two characters is positive; (Bit E = 1) "Central unit 5 sends a command COP to issue or write. Of course the ÷ logical decision 357 is accomplished using a conditional jump instruction. In fact, when the condition is not verified (Bit E When this happens, the central unit 5 returns to state A as described above.
On the other hand, if it is verified (bit EEl), the central unit 5 executes a jump instruction to the storage address where the first character of the instruction COP is recorded. Directive type (
The command COP is decoded by circuit 325. When this character indicates a command, circuit 32
5 generates a signal L which activates the readout device 342 to cause a serial readout of the bits of the first character of the selected block, and the extracted bits are transferred to the register 31.
9 (block 358 of FIG. 18). When this register is filled, it energizes the circuit 337, which sends an interrupt signal to the central unit 5 (
block 360 of FIG. 18). In response to the command CDP, the central device transfers the read characters from the control device 10 to the storage device 42 (
Transfer to block 361) in FIG. In this way, all characters of the selected block are transferred to storage device 42. When the central unit detects that the character read is the last of the selected block, it sends a so-called end command COP to the control unit 10 (logic decision 362 in FIG. 18).

The decoding of the last character of this block is carried out by the central unit 5 using the command CDC, which contains a constant representing the consecutive number of characters to be extracted from time to time and a constant representing the maximum number of characters in the block. give rise to a comparison of If the result of this comparison is positive (bit E=
1), the central unit 5 generates the termination command CO using exactly the same process used for the generation of the command COP for proposing.
Generate P. Decoding circuit 325 (17th
) decodes the second character of the termination command COP and generates a command signal, not shown in the drawing, which transfers the control device 10 in a known manner into the state corresponding to the termination command COP. (Block 363 in Figure 18).

When this character indicates the end of a block presentation with a stop of the tape, the control unit 10 returns to its initial state (first
Return to Figure 8).

When the presentation of the next block begins despite indicating the end of presentation of a block, controller 10 returns to the state represented by block 358. When this character indicates the end of reading a block and at the same time a block that does not follow the block that has been read is started, the control device 10 is in the state of addressing the address.
That is, the process returns to the state represented by block 354.
If the central unit 5 proposes to record or write data to a selected block, it
Send command COP to write this (logical judgment 359)
.

This command is decoded by circuit 325 (FIG. 18), which in turn energizes circuit 337 with a signal date. Circuit 337 sends an interrupt to central unit 5 (block 365 of FIG. 18), which in turn sends command CAP to control unit 10 in the manner described above. This instruction is sent to circuit 325 (
18), it sends a signal K which opens gate circuit 320 and transfers the character to be written or recorded from register 318 to the register. At the same time, circuit 325
26, this timer 326 shifts the bits in the shift register 319 according to the time signal TH and introduces them serially into the write device 339. These operations are illustrated by block 366 in FIG. When the entire character has been recorded, the writing device generates a signal J in a known manner, which causes an interrupt to be sent by circuit 337 (block 367).

As a result, the central unit 5 issues the termination command CO in the manner described above.
P or command CAP can be sent (logical decision 36
8). In the first case, the control device 10 returns to the inactive state, and in the second case it returns to the state identified by block 366 in FIG. INTRODUCTION OF INSTRUCTIONS TO THE SIDE ID CENTRAL UNIT As previously mentioned, the operation of the present automatic printing device is controlled by a group of instructions, each associated with a particular processing operation to be performed on the text.

These commands are stored in program block BPI located in track PO of tape 310 (FIG. 15).
...Recorded in BP256. More specifically, the processing operations that may be performed on the text are either processing operations on the form of the text or processing operations on the constants. Type-related processing operations make it possible to selectively add or subtract characters in a printed line, in other words to justify the resulting line, and in other words to align the right-hand limits of the line, 1 It is possible to increase the underlining of one or more words in a line or lines, or to center one or more words with respect to the length of a printed line.

On the other hand, content-related processing operations allow one or more lines to be deleted, new lines or passages to be added, or errors to be corrected. Each of the described processing operations is defined by a corresponding group of instructions, which must be transferred from tape storage 7 to core storage 42 of central unit 5 (FIG. 2) in order to take effect. The central unit 5 then stores them in the storage device 42.
Execute in the order recorded in .

To transfer a set of instructions from the tape deposit device 7 to the core storage 42, the operator activates the start pushbutton on the keyboard 8. The decoding circuit 325 (FIG. 17) is then activated in the manner previously described and the controller 1 of the tape storage device 7
0 is placed in the proposed state 358 (FIG. 18). Central device 5
at this time leaves the inactive state represented by block 3801 of FIG. The address recorded in track PO of storage device 7 (FIG. 1) is now yielded and sent via control device 10 to central device 5.

Since each address is preceded by an interrupt, this is a jump instruction to the element part of the central unit 5 and the element part of the storage device 42 (FIG. 2) at the address determined by the interrupt itself as described above. Execute. A command CDC is recorded at this address, and in accordance with this command, the central unit 5 compares the address coming from the control unit 10 with the address stored in the register 57 in a circuit 98 (Fig. 3). Since the address stored in register 57 is formed by eight bits that are all 0, controller 10
Transfer of this block from tape storage 7 to core storage 42 occurs when the program sends to central unit 5 the address of the first program block recorded on tape 310' and identified by eight zero bits. The input of the first instruction is symbolically block 381 (first
Figure 9). The address of the element section of the storage device 42 in which the characters of this block are recorded is supplied by the addressing circuit 45 of the storage device 42. As mentioned above, the group of instructions recorded in the first block is the first instruction ~ which causes the central unit 5 to record subsequent instructions in the manner described below. Central device 5 is in state A
The readout of the first instruction is carried out during the period , and staying in this state causes the output signal B of flip-flop 35 (FIG. 2)
Defined by T. When this signal is 0, i.e. when the instructions of the first group have been completely written into the memory 42, the central unit 5 turns to the execution of the instructions contained in the first group of instructions (the (block 382 in Figure 19). At this moment, the central unit 5 (FIG. 2) is still in state A and the address decoding circuit 45 has recorded the address of the element following the element occupied by the first instruction of the first instruction group. There is.

When the central unit 5 moves to state B to execute the first instruction of the first instruction group, the contents of the element section of this last instruction are transferred to the output register 5, and then transferred to the command COM 15 (7th
2) is transferred to register 57 (FIG. 2). The first instruction of the first instruction group is the instruction CO
P, and this command causes the central device 5 to place the control device 10 in the issue state 358 (FIG. 18). Central unit 5 then compares the address supplied by control unit 10 with the previously stored contents of register 57 (FIG. 2).
These contents are the addresses of blocks recorded on tape 310' that were included in the input instructions that were associated with another set of instructions related to a particular processing operation to be performed on the text. When this address is verified by the central unit 5, the block thus identified is transferred from the tape storage 7 to the core storage 42. The operations performed by the central unit 5 to record the block of input instructions are symbolically referred to as block 382 (19th
block 354,3 represented by and previously described in FIG.
55 and 356 (also in FIG. 8). The block of instructions written to storage 42 in this manner includes the address of a second block, which is also a block of input instructions, as described above.

This second block is then written into storage 42 as described above. The central device 5 is now in an active state, symbolized by block 383 (FIG. 19). In this state, the first instruction group and the second
Two inputs. The gram block is written to storage 42 and resides there. Input blocks are above all “selections”
The selection commands enable the writing of specific commands, called commands, into the storage device 42, and the selection commands are assigned to tracks PO on the tape.
It is possible to select a particular group of commands issued on the keyboard 270 (FIG. 14) of the typewriter 6 from among all the commands recorded on the computer.

After the input input state represented by block 383 (FIG. 19), central unit 5 encounters a logic decision represented symbolically by block 384.

This logical decision represents the possibilities that the central unit 5 has for a group of general instructions or a group of selected instructions. This logical decision is represented by a conditional jump instruction recorded at the beginning of the first input block. This conditional jump instruction causes the central unit 5 to now select in the manner described above the address of the program block recorded in the track PC (FIG. 15) that corresponds to the commands entered by the operator on the keyboard 270. A jump is performed to the element portion of memory 42 containing the instruction COP, which places central unit 5 in a position to submit as input the general instruction indicated by block 386 (FIG. 19).

This jump allows central unit 5 to perform a jump to the element portion of storage device 42 containing the command COP associated with the "select" command (block 385 in FIG. 19). The central unit 5 executes the jump command to one or the other element according to the fact that the operator has entered or not entered a particular processing action on the keyboard 270. When the operator does not enter any processing operation, the central unit 5 executes a jump command to the storage device element section including a "selection" command COP. The address of this element portion is represented by the second character of the jump instruction. The first command of this prince is the command CO to direct the typewriter 6 to the control device 9.
It is P. This command causes the central device 5 to put the control device 9 into the receiving state, and then, by the following command CAP, type printing outside the label JOB? send. These operations are symbolically represented by block 388 (Figure 20).
The control device 9 then sends a command to the input device 12' (FIG. 14) to print this level, which will then appear on the printed paper. After this, the next command COP causes the central device 5 to place the control device 9 in the transmitting state, symbolically represented by block 389 (FIG. 20). The operator then enters a label or group of characters on the keyboard 270 (FIG. 14) of the typewriter 6 that forms the desired instruction group.

The controller 10 introduces an interrupt after each character as already explained in the description of the controller 10. The current state of central unit 5 is represented by block 390 (Figure 20). Thereafter, each character transmitted by the control device 10 is stored in the element portion of the storage device 42 (block 391). Upon receiving each character, central unit 5 must make a logical decision represented by block 392, by which it checks whether the label has been completely sent. More specifically, the central unit 5 checks whether the last character received from the typewriter 6 is the fourth character on the label. Typically, this logical decision is represented by a jump instruction conditioned on the result of the comparison operation made by instruction CFR. The method for executing this instruction is the same as for the logic judgment described above. If the last character received is not the fourth character of the label, the central unit 5 sends a command COP to the control unit 10 of the typewriter, which command causes it to
is placed in the transmitting state represented by block 389.

The delivery of the next character to the central unit 5 is then obtained, so that the central unit 5 returns to the state represented by block 389. When the fourth character is sent, the central unit 5
checks whether the sent character corresponds to one of the labels recorded on track PO of tape 310 (block 393). Of course, the command CFR performs a comparison, which is repeated many times until the selected label is verified. If the worker makes a mistake when pressing the key to insert a label, the central device 5 issues command C.
Label JOB for control device 1 0' by OP? is again commanded to be printed (block 388), resulting in the operator refeeding the label.

If the label has been inserted correctly, the central unit 5 stores the address 11...1256 in the storage device 7 of the first block of the instruction group that has been inserted. A jump instruction to the element section of the desecration 42 is executed. The central unit 5' now commands the reading of this element part of the storage device 42, and uses the address read there by the command TRA of the jump command of the second character group of the jump command of the input command group. The data is transferred to the element section of the storage device 42 corresponding to the second character. In this way, the central device 5
may implement the operation represented by block 386 (Figure 19). The element defined by this character contains the address 11 of the first block of instructions in the storage device 7 to be transferred to the storage device 42...1256
It is included. These operations are performed in block 394 (second
Figure 0). Thus, corresponding to each label entered with the keyboard, the address of the first block of instructions can be changed according to the entered label, so that the corresponding block selected by the label in storage 7 is stored in storage 42. may be transferred. Thereafter, the central unit 5 transfers this selected block to the storage device 42 by the act described with reference to FIG. 19 and symbolically represented by block 386 (FIGS. 19 and 20). do. In conclusion, when the printer starts up, the first command to memory 42 (block 3 in FIG. 19) is
81) is transferred, and this instruction is transferred to the tape storage device 7.
(block 383), and finally the input instruction places the selection instruction as input in the storage device 42 when no label has been selected by the operator (block 383).
Block 385). When these instructions are entered as input, the label JOB? is printed (20th
(block 388 of the diagram). As a result, by typing the label, the operator selects a set of operating instructions. The "select" instruction selects the address of the group from among those assigned to the various operating instruction groups and provides it to the input instruction (block 394). Finally, the input instructions block 386 enters the selected instructions into the storage device 42 so that they are executed by the central unit 5. G-Force Recording Text When it is desired to record text, the operator places the printing paper on the platen of the typewriter 6 (FIG. 1) and activates the start pushbutton on the keyboard 8.

Central unit 5 is thus conditioned to write initial instructions, input instructions and selection instructions to storage device 42 (FIG. 12) in the manner described with reference to FIGS. 19 and 20. Thereafter, the selection command controls printing of the label "JOB?" by the typewriter 6. The central unit then commands the typewriter 6 in a known manner with the command COP to "return to beginning with line basing". The worker then enters the label "REGI" on a typewriter (block 410 in FIG. 21), which is sent to the central unit 5.
, the so-called "record" command group of block BPI...B256 of tape 310 is selected (block 411).
and conditions it to be transferred to storage device 42.

These commands are intended to preset the limit adjustments and control the output of the text to be later typewritten by the typewriter in the tape storage device 7. In fact, a recording command is issued to the central device 5 to record the tape 310 (FIG. 14) on which each thing to be copied or printed is to be recorded.
The address of block BI......B256 is combined. For this purpose, track P1 of tape 310...
...... Each PN contains a special block called a "table block".

This table block is in a predetermined position in each track and is accessible by the central unit 5 in the manner described below using addresses which remain unchanged throughout the operation of the printing device. For example, each track PI...
Let us assume that the table blocks of PN (FIG. 14) are each block BI. This table block is formed by 67 8-bit type characters, so the first 64 characters contain a total of 512 bits. These bits are grouped in pairs, each of which is assigned to a data block B2...B256. More specifically, the first pair of bits of the table full block BI recorded in track PI are associated with the same block B turtle, the second pair is associated with block 82, and so on, the 256th crab. The pair is block B2
It is related to 56. Since the two bits of these pairs can take on four shapes, each of these shapes is associated with one item of information for the corresponding block.

More specifically, the meaning of these information items is summarized in the table below. The first combination indicates that the block is free and recordable and therefore can be occupied by data.

The second combination indicates that the block is occupied but can be recorded by erasing the data contained therein.

The third combination indicates that the block is free for data transfer, but is unrecordable due to change or wear of the magnetic material of tape 310, for example.

This prevents any lines of text from being lost because they are recorded in a corrupted block. The last combination is used to indicate that a block cannot be recorded if it is not desired to change its contents, such as in the case of table blocks. After the first 64 characters of the table block another group of three characters is recorded which is the same for all table blocks.

The first of these characters indicates the selection command COP, which, as previously described, selects tracks P1 and P1 of tape 310.
..... PN is selected. This command is used to select the track containing the first free recordable block, as described below. The second character of the group of three characters indicates the address of the first free recordable block, and the third character indicates the label of the tape cartridge to which this block belongs.

The first two characters, called "indication information", are sufficient to indicate the address of the first free recordable flock of tape, and the third character is used when multiple cartridges are used simultaneously and this It cannot be taken into consideration. Of course, the instruction information is updated within the tablecloth after each recording in the manner described below. The first of the "record" commands is a selection command COP directed to the control device 101 of the tape storage device, whereby the track PI of the tape 310 is selected and the control device 10 is sent to a state 358.
(FIG. 18), when the address corresponding to the table block BI of the track PI (which cannot be changed as described above) is confirmed, the "record" command controls the reading of the table block.

This condition is symbolically represented by block 412 (FIG. 21). Therefore, the tablecloth BI corresponding to the track PI is transferred by the central device 5 to the area of the storage device 42 . The jump command included in the "record" command then causes the central unit to jump to the element section of the storage device 42 where the first character of the instruction letter is recorded.

This element is always the same no matter what the table block is, since the characters defining the instruction information have a fixed position within the table block, and these characters are always in the same area of the memory 42, as is known. This is because it is recorded. Since the first character of the instruction information is a command COP commanding the selection of the track containing the first free recordable block, the address of this block is recorded in the next element of the storage device 42, so that the tape storage device The first free recordable block of 7 is thus identified.

This condition is symbolically represented by block 413 (FIG. 21). The selection command COP places the control device 10 of the tape storage device 7 in the addressing state (block 414) in the same manner as described above with respect to FIG.
).

The selection of free recordable blocks identified by the instruction information then takes place in the manner described with reference to FIG. 18 (block 415 of FIG. 21). Starting from the free block address, the central unit 5 then selects a series of 23 free recordable blocks in the following manner.

With command TRC it transfers to the element portion of storage device 42 the address indicated by the instruction information incremented by one unit amount. This new address defines the data block that follows the data block defined by the directive information. The central unit 5 then checks, on the basis of the contents of the table block BI, whether the data block defined by this address is free and recordable. In fact, it is
The command CDC checks whether the bits of the data block corresponding to this address both have the value 0. If the block identified by this new address is occupied, the result of the comparison is bit E=0.
give. The central unit 5 then executes the command TRC, using which it transfers the address of the occupied block, which has been increased by one unit amount, to another component part of the storage device 42. The same operations described above are then repeated to assess whether the block with this last address is free and recordable. If the result of this comparison is positive (bit E=1), the central unit 5 records this new address in the storage device 42 in two steps. In the first step, the central unit 5 executes a conditional jump instruction to the storage element in which the instruction TRL is recorded.
In the second step, using this instruction, it transfers the address following the address pointed to by the indication information to the storage element following the last element occupied by the table block, thus There are 2
Record the second block of 3 blocks.

The operations just described are summarized in block 416 (21st
Figure). This operation is repeated for the remaining blocks located at mutually spaced locations on tape 310.

In this way, the central unit 5 selects a group of free recordable blocks. The number of such blocks, 23, was chosen for the reason that this is the average number of lines of writing that would normally be made on a typeface. When the number of free recordable blocks is less than 23, the central device 5 moves on to the removal of the tablecloth belonging to the next track, so as to always supply 23 free blocks, by means of the next selection command COP.

In order to determine whether a block that is free is larger or smaller than 23, the central unit 5 transfers the bits of the table block corresponding to the data block following the block defined by the instruction information to the element part of the storage device 42, and CD
Check whether these bits are all 0 and whether the number is 46 using C. If so (logical decision 425), i.e. at least 23
When there is a free block, the central unit 5 performs the operations described with reference to block 416, or else it jumps to the read address state to read the table block of the next track (block 416). 414). Thereafter, the central device 5 puts the control device 9 of the typewriter 6 into a receiving state by the command COP.

Then, the next command CAP causes it to enter the input device 12' (
Send the address of the first free block to (Figure 14).
The input device 12' then instructs the typewriter 6 to print this address on the left edge of the paper below the label REGI in the manner described above (block 41 in FIG. 21).
7). Selection command CO recorded in the first character of instruction information
The central device 5 uses the controller 10 of the tape storage device using P.
is placed in a state of free address selection and reception (block 418). The central unit 5 then uses the command CAP to send a group of four space characters to the control unit 9 of the typewriter 6 to advance the carriage by four steps. At this point, the operator can enter, through the keyboard 2701 of the typewriter 6, a code corresponding to the operation that the central unit must perform on the print or write line during the next printing of text. Operations that central unit 5 can perform include determining the right limits of lines, centering, and underlining. To enter the codes corresponding to these operations, the worker activates the "1 step back" key on the keyboard 270 (logical decision 417 in FIG. 21).
'), which returns the carriage of the typewriter 6 by one step.

The control unit 9 of the typewriter 6 then sends the code for "return by one step" to the central unit 5 using the command CDP.

Central unit 5 verifies this code by circuit 98 (FIG. 13) of storage input circuit 47 under the control of command CFR. In response, the central device 5 sends the command CDP to the control device 1.
0, and the control device 10 enters the transmitting state. Command CDP
The second second character is the address of the element section of the memory device 42 in which the character coming from the control device 10 is to be recorded, and this character is the address of the print line or the memory device element section following the recorded element section. is not recorded. After this, the operator activates one key on the keyboard 270 from a group of alphanumeric keys associated with the operation that the central unit 5 is to perform.

The control device 10 then sends the code corresponding to this key to the central device 5, which records this code in the selected element of the storage device 42 (block 41).
7″).More specifically, the worker operates the back base (one step back) key and the L key to define the right limit (right margin) of the line, and also operates the back base (one step back) key and the L key a number of times equal to the number of characters in one print line. Perform only smoothing.

The central device 5 accepts the printed letter L and transfers it to a predetermined element of the storage device 42 in the manner described above.
The command following the command CDP for recording the character L in this manner is a jump command to another element section of the storage device 42 in which the command CFR is recorded. This command causes the central unit 5 to
compares the character L with the characters of the possible commands of the printing device. When this character is confirmed, the central unit 5 uses another jump command to count the space characters extracted following the character L' by a series of operations controlled by a series of commands TRC. Do this. Then, each time there is a transfer of a constant representing a space character incremented by one unit amount. For example, 000000000 for this constant
When a particular value such as is selected, at the end of counting the final constant corresponds to the number of characters entered for that print line. Furthermore, this command TRC causes the central unit 5 to transfer this number to a predetermined component of the memory 42, so that the line length remains recorded in the memory 42.

If the operator must enter other commands, such as centering a title, underlining, etc., the operator again enters "back one step" and accordingly activates the respective alphanumeric key thereafter.

In the same manner as described above, the code corresponding to this alphanumeric character is recorded in the corresponding element part of the storage device 42 instead of in the element part following the element part in which the row address is recorded. Upon writing of the letter L or other alphanumeric character associated with the command, the carriage recovers space "one step back" and is in the first position of the line.

The worker now enters the letter of the line of text to be recorded by means of the keyboard 270 (FIG. 14), which in turn indicates on the paper that this line is four steps away from the address of the flock to be recorded. It will be printed.

These characters are now stored in storage device 42 in the manner described above.
is serially transferred to the register 42' (FIG. 2). Register 42' of this storage device 42 (block 4 in FIG. 21)
19) is saved in this transfer. At the end of the line, the operator activates the key for carriage return with line basing, so that the carriage returns to the beginning. Furthermore, the relevant code is verified by the central unit 5 using the command CDC, which is conditioned as usual and places the central unit 5 into the next operating state using a jump command. In this state of operation, the central counter 5 transfers the line recorded in the register 42' (FIG. 2) to the register 42' of the storage device 42 and completes the data block therein with respect to the character of the function; It then begins searching for a block on tape 310 in which the completed block should ultimately be stored.

More specifically, using instruction TRA, the central unit transfers the track selection, address of the next free block, and instruction COP for the label corresponding to tape 310 to the first three characters of the block for subsequent processing. It defines the order in these blocks of operations, eg, operations for sequentially writing the various lines of a given text. In fact, since the characters of these three functions have been previously recorded in the predetermined element part of the storage device 42 (block 416 of FIG. This can be used for any data block without changing the second character of the instruction that defines the address of the section. Also, since these data blocks are subsequently recorded in the same element portion of the storage device, the third character of the instruction TRA is always the same. Using another command TRA executed subsequently, the central unit 5 enters in the fourth element of the data block the number of printed characters that the block can contain, which has already been recorded in the storage device 42. Forward.

The central unit 5 then uses the next command TRA to transfer the number of characters actually placed in the fifth element of each data block. This number is counted by the central unit 6 in a similar manner as for the number of spaces described above. However, in this latter case the command to start counting is given by the characters "carriage return with line basing". The central unit 5 then transfers to the sixth element of the block the code of the action to be performed on that row (centering, underlining, etc.).

Finally, the central unit 5 calculates the parity check character resulting from the entire data block in a known manner and transfers it to the seventh element of the block itself. The operations just described are represented briefly by block 420 (FIG. 21). Upon completion of the block just described,
The central device 5 uses the selection command COP to put the control device 10 of the typewriter 7 into a state where the tape 310 is released (first
(block 358 in Figure 8).

In this manner, the control device 10' searches in the storage device 7 for the address of the block in which the print line entered before the keyboard 2701 is to be recorded in the manner described above. While the control device 10 is searching for this address, the operator enters a second print line from the keyboard 27, which is transferred to the register 42' (FIG. 2) of the storage device 42 in the manner described above. . In this way, the central device 5 can simultaneously complete the block corresponding to the first print line by completing the block 42 corresponding to the second print line.
' and register 42 on tape 310
” and corresponds to the first printed line.

The data block is searched for the block to be recorded, and the completion of the data block is interrupted from time to time. When the control unit 9 of the type printer 6 or the control unit 10 of the tape storage unit 7 sends a character to the central unit 5, they cause an interrupt to the central unit 5 as described above. interrupts the completion of progress on the data block recorded in register 42'' in order to accept a character coming from one of the two controllers 9 and 10. The central unit 5 then restarts the completion of the advance. More specifically, the time at which the controller 10 searches the tape 310 for a block in which the contents of the register 42^ of the central unit 5 are to be recorded varies depending on the position of the block on the tape.

At most, this time is equal to the average time it takes for an operator to enter the next line from the keyboard 270'. As previously mentioned, controller 10 sequentially attempts to locate the addresses of blocks recorded on tape 310' until it verifies the address it receives from central unit 5.
Therefore, the maximum time required to locate these addresses is determined by the tape advance speed and the length of the tape itself. When the operator has completed feeding the second print line, he again activates the key for "carriage return with line spacing".

As a result, the central unit 5 registers 42 of the storage device 42
The completed data block corresponding to the first printed line of `` is transferred to the tape storage device 7, and the second printed line is transferred from the register 42' of the storage device 42 to the first register 42''. After this, central unit 5 returns to the recording state indicated by blocks 417 and 418 in FIG. The operator can now enter a third row, resulting in the operations described above being repeated. These operations are symbolically represented by block 421 (FIG. 21).

When the worker finally completes writing the text, the worker notifies the central device 5 of the end of the text.

To this end, after printing the last address, the operator activates the "one step back" key and then the key for initial E on keyboard 270 (logic decision 423). The central unit 5 then verifies the code associated with this key and eventually converts the first three characters of the block associated with the last printed line from the command TR to the 66th and 60,000th character of the table block. It is transferred to the element section of the storage device 42 where it is stored. As mentioned above, the table block has been recorded outside the register of the storage device 42 after the operator has entered the label REGI using the keyboard 270, and as a result, the instruction information has been updated in this way and is re-entered from the beginning. contains the address of a free recordable block (block 424 in FIG. 21), so that when recording the next text the central unit 5 again supplies the address of this block in the manner described above.

The 2nd and 37th characters of instruction TRA are stored in storage device 4.
No matter what table block is recorded in 2, it is always the same. In fact, since the table block is always recorded in the same element of the storage device 42, the command T representing the address to which the contents of the element identified by the second character are to be transferred
The third letter of RA is always the same and therefore valid for each taffle flock. Similarly, 2 of this command
The th character always remains unchanged, since the address of the free block is always recorded in the same element of the memory 42. The central unit 5 thus sets the address of the first free recordable block, controls the line-by-line recording of the text, and updates the address of the next data block and the line itself when that block is printed. It is obvious to insert into each data block a code of the type of operation to be performed on the print line to be recorded, and to update the value of the indication information after each recording.

Additionally, it should be noted that when the operator notices a typographical error during the printing of a line, the operator activates the "one step back" key.

The characters of the command associated with this key are recognized by the central unit 5 and the interrupt associated with this command inhibits the address from being incremented by the central unit as described above, so that the subsequently entered characters are It replaces the characters recorded in the storage device 42. When the operator proposes to underline one or more words on a printed line, the operator should add “1” after printing the address corresponding to this line.
Activate the "Step Back" key and then the key corresponding to the symbol S.

The operator then records the text of the line, and when the operator reaches the word to be underlined, the operator activates the underline key instead of the space key. The worker then records the words to be underlined. At the end of this word, the worker again activates the underline key instead of the space key.
- Therefore, the code corresponding to this underline key is recorded in the element part of the storage device 42 in such a way as to identify the beginning and end of the word to be underlined. (X) Text Correction The printing device is capable of correcting the content of the text, such as by adding or removing one or more lines.

When the worker wishes to insert one or more lines of previously printed text, the operator presses the keyboard 2 of the typewriter 6.
70 enters the label REGI. This label is verified by central unit 5 and forwards a set of "record" commands from tape storage 7 to core storage 42 in the manner described above with respect to FIG. These operations are collectively represented by block 425 (FIG. 22). The line or group of lines to be inserted into the text is then stored in the storage device 7 in a manner similar to the recording of the text as described above. The operator enters the label MODI on the keyboard 270 to insert the line now entered at any point in the text that has already been recorded.

More specifically, this label causes the transfer of a group of instructions referred to as "modify" or correction instructions within the tape storage to the core storage 42 of the central unit 45 in the manner previously described (block 426). This change symbol acts to change the order of the addresses of the data blocks so that during the reading and printing phases (these are described below) they are retrieved from the storage device 7 in a different order than they were recorded. Do it like this.

In fact, it was stated that each data block contains the address of the next data block in the first and second characters.

Modifying instructions operate on the contents of these instructions to change the address of the next data block. To accomplish this, after inserting the label MODI and returning the carriage of the typewriter 6 to its initial position, the worker activates the keyboard 27 alphabetic single numeric key, for example the key for the symbol "1"; Four labels can be inserted.
The first of these labels represents the address corresponding to the line of text that is printed on the paper during the discussion of the text and becomes the original text when the operator enters new text. The second label represents the address of the first line of insertion, which is also applied to the paper.

The third and fourth labels are respectively the address of the last line of insertion and the address at which printing of the previously recorded text should restart (this is usually the address of the line following the line into which the new line is inserted) represents.

These four addresses are recorded in the corresponding element portions of the core storage device 42 using the method described above. The central unit 5 confirms the command code 1 entered here (block 427).
). This code is insertion code 1 in this case, so
Using instruction CFR, the central unit executes a jump instruction to the predetermined storage element associated with code 1 (block 438). The first command of the group of change signals associated with code 1 is recorded in this element. This first command is the selection command COP, which places the control device 10 of the tape storage device 7 in the addressing state (block 428). In this way, a selection is made of the data block corresponding to the first of the four addresses entered, which is the point at which it is desired to enter the insertion, i.e. the address of the data block (see FIG. 22). Block 429). Using the subsequent instruction CDP, this first block is transferred to the corresponding group of elements of core memory 42 as described above.

Using the command TRA, the central unit 5 now uses the second address entered, ie the address of the first line of insertion, to identify the address of the next data block in the selected and just storage device 42. storage device 42 in which the second character of the data block transferred to is recorded.
(block 430 in FIG. 22).

Of course, the address of the first row of insertion is the same track PI where the address of the selected block is recorded...
.....When PN' does not belong, the central unit 5 further issues an instruction C to select the track whose address belongs to the first line of insertion into the first character of this data block.
Forward the OP. These transfer operations are symbolically indicated by block 430. The element portion of the storage device 42 in which the address following code 1 is recorded is predetermined, and it is exactly the same as if the element portion in which the selected block of the first address is recorded is fixed. For this reason, the second and third characters of the instruction TRA just described always have the same shape insofar as their lengths relate precisely to the addresses of these component parts. Thereafter, using another selection command COP, the central device 5 again places the control device 10 of the tape storage device 7 in the address reading state (
Block 431).

Therefore, the data block associated with the third address entered, the address of the last row of the insert, is selected (block 432). By the same operation as described above, other instructions TRA are executed in the first and second blocks of the selected block.
Controls the transfer of the fourth address entered after code 1, the address at which printing of the old text is desired to be restarted, to the storage element where the th character is stored. When the operator wishes to remove from tape 310 a line or group of lines of writing recorded thereon, the operator activates key E after label MODI.

The operator then enters two labels corresponding respectively to the address of the preceding line and the address of the line following the group of lines that the operator wishes to remove. Central unit 5 now identifies code E in the manner previously described and performs a jump to the corresponding storage element containing the first of the instructions associated with code E (block 439). This instruction is the selection instruction COP, which places the controller 10 of the tape storage 7 in the addressing state (block 435).
. Therefore, the data block corresponding to the address of the row preceding the first row of the group of rows to be removed is selected.
The central unit 5 then transfers to the first and second characters of this block the address corresponding to the line following the last line of the group of lines to be removed. In this way, the data block corresponding to the row preceding the group to be removed has recorded the address of the data block corresponding to the row following the group.

As a result, when these blocks are retrieved from tape storage 7, central unit 5 skips only the group of rows that the operator previously removed. When the operator wishes to append a previously recorded group of lines to the end of the text, the operator enters the label MODI and then activates the key T, which includes the address of the last line of the text and the operator's input to the text. Followed by the submission of the address of the first line of the group of lines that you want to end.

The central unit 5 identifies the code T and proceeds to the storage element containing the first of the corresponding instructions (block 443).
). In the manner described above, the central unit 5 inserts the second address into the first two characters of the data block identified by the first address. The facility provided by the present printing device is for example the end of a group of different personal letters or circulars which have a standard format and are recorded individually once for every letter. It is particularly useful for It is therefore clear that the text may be altered or corrected by acting exclusively on the addressing characters of the data block without changing the location in which the data block is recorded on the table 310'. As will be explained below, these blocks are removed from the tape storage 7 and introduced into the central unit, whereupon they are printed by the typewriter 6 in the order desired by the operator. The order of the addresses of the data blocks corresponding to the lines within the group of lines to be inserted or appended is not changed, so that these lines are printed in the order in which they were previously entered. It is noteworthy. Finally, when the operator wishes to replace one line with another previously recorded line, the operator activates key S after entering the label MODI, which includes the address of the printed line to be replaced and The sending of the address of the new print line continues. Central unit 6 identifies code S and performs a jump to the storage element in which the first of the corresponding instructions is recorded (block 444). The first command is the selection command COP
Using this command, the central unit 5 selects the track in which the address of the data block corresponding to the print line to be replaced or replaced is recorded (block 4).
40). The central unit 5 then transfers this data to the storage device 42 by successive commands COP in the manner described above (block 441).

In the same way, the central device 5 transfers the data block corresponding to the new print line to the storage device 42. The central unit 5 now executes a series of instructions TRA by which it transfers all the characters of the second block to the elements of the storage device 42 in which the characters of the first block were recorded. This results in the replacement of the characters of the line to be replaced by the characters of the new line. Since the elements of the storage device 42 in which these two blocks are recorded are fixed, the central unit 5 can use the same instruction TRA to perform the replacement, where the change signal is Increases the address of one operand by one unit. In this way, all the characters constituting the data block of a new line can be called up in sequence, and at the same time these characters can be transferred in sequence to the elements occupied by the characters to be replaced. These operations are illustrated schematically at block 442. Thus, the operations described above allow the operator to process text on demand, provided that the processing operations relate to the total number of lines.

(xi) Word correction When the operator detects thought words when rereading the recorded text, the operator can condition the central unit 5 to correct these errors.

More specifically, the worker presses the start key on the activation keyboard 8, which, as mentioned above, is labeled JOB? This causes printing. After this, the operator enters the label FAST via the keyboard 270, which is confirmed by the central unit 5 and eventually sends a group of so-called "correction" commands to the memory 42.
(block 445 in FIG. 23)
. Thereafter, the operator inserts the label corresponding to the address of the print line that he wishes to correct. This address is recorded in a predetermined memory element section using the method described above. The first of the correction commands is a selection command COP, which places the controller 10 of the tape storage 7 in an addressing state (block 446).

When the entered address is verified, the data block identified thereby is transferred to a predetermined element of storage 42 for text correction in the same manner as described above (blocks 447 and 448). The central unit 5 is then preconditioned to read the data block starting from the sixth character, ie skipping over the five function characters of the data block (block 449).
). This pre-adjustment is accomplished by a jump command to the storage element where the sixth character of the data block is recorded. When the first word in the line is correct (logical decision 4
50), the operator now activates the interrupt key on the keyboard, which causes the reading of the contents of the next storage element as described above (block 451), and the central unit begins to input characters. make it happen.

After each character is presented, the central fukuro counterfeit 5 checks whether this character is a space character by the command OFR. Here, the two operands are the space character and the extracted character (logical decision 452). If the read character is not a space character, the central device 5 controls the control device 9 of the typewriter 6.
A storage device 42 in which a command COP directed to is recorded.
Executes a jump command to the element section. As previously mentioned,
The command COP causes the printing of the characters read, resulting in the printing of the first word of the line in which the error was detected. When the read character is a space character, the central device 5 sends a command COP to the control device 9 of the typewriter 6, which command COP acts on the control device 12' (FIG. 14) to stop printing in the manner described above. (Block 454). When the word following the one printed is the correct word, the operator again activates the interrupt key on the keyboard 8, which causes the entry of the element following the element in which the space character is recorded and the central unit 5 returns to the state represented by block 451.

In this way, the words forming the selected line are printed individually. When the worker notices that the word following the printed word is a contrived word (logical judgment 45)
0), without activating the interrupt key, instead enter the correct word on the keyboard, which is sent to the central unit 5 by the command COP, and then to the element part of the storage device 42 in which the incorrect word was recorded. recorded (block 45
5).

If the number of letters forming the correct word is greater than that of the planned word, the worker must enter not only the correct word but all of the other words until the keyboard 27 row is completed. When the end of the line is reached (logical decision 456), i.e. when the last free element of the data block has been occupied, the central unit 5 reads out the line thus corrected in the tape storage. 'I'm moving.

For this purpose, the element section following the element section occupied by the last character of the data block contains a selection command COP, which puts the control device 10 into a receiving state. Thereafter, the corrected data block is transferred to the same location in the storage device 7 where it was previously recorded in a manner similar to that described for the case of text recording with respect to FIG. Thus, provided the operator does not introduce more characters than the maximum number of characters that can be recorded in the block, the operator can make any corrections to the text by the operations just described.

(xii) Printing of Corrected Text After the operator has made all corrections or changes to the content of the text and has made the corrections of the associated errors, the operator may print this corrected text into a "correct copy". can be commanded to be printed.

To accomplish this, the worker activates the start key on the activation keyboard 8, which is labeled or written JOB? as previously described. This causes printing. The operator then enters the label EDIT via the keyboard 270 (FIG. 14), which is confirmed by the central unit 5. As a result, a group of instructions called "print" instructions are transferred from tape storage to core storage 42. These operations are illustrated schematically by flock 460 (Figure 24). After the label EDIT, the operator enters from the keyboard 270' the label corresponding to the address of the first line of the first page of text to be printed. This operation is symbolically represented by block 460' (Figure 24). The first command of the group of print commands is the control unit 1 of the active keyboard 8.
This is the command COP directed to.

This command COP has a second character formed from the 8 bits located in bell I and lights up the indicator lamp of the keyboard 8 as described above. The operator is thus alerted that the printing paper must be changed. The operator now inserts the "correct copy" into the platen of the typewriter 6 and activates the interrupt key. The interrupt thus introduced causes the central unit 5 to extinguish the lamp and execute a jump command to the storage element associated with the keyboard 8. In this element section, a command COP for selection directed to the control device 10 of the storage device 7 is recorded. This selection command COP is on the keyboard 270.
The address entered in is sent to a predetermined element section of the storage device 42, and the central unit 10 is placed in an address setting state. When the address thus recorded in storage device 42 is verified (block 462), the data block thus identified is transferred from tape 310 to a predetermined group of elements of storage device 42 (block 462). 463
). Command CFR causes central unit 5 to issue the sixth character of the block transferred to storage 42, which indicates the particular operation to be performed on that line (logical decision 464).

If the sixth character is 0, the central unit 5 performs the so-called "legalization" of the line (block 46) in a manner described below.
5).

After that, the characters are written to the typewriter 6 by successive commands CAP.
(block 466), which takes care of printing the line itself in the manner described above. block 6
If the th character is not 0, the central unit 5 associates this character with a group of ``print r'' commands with the various operations to be performed on that line and records it in a predetermined element of the memory 42. Compare with possible characters (block 467
).

If the operation to be performed is centering or underlining characters in a line, central counterfeit 5 performs these functions in a manner described below (blocks 468 and 468'). After these processing operations, successive instructions C
The AP sends the characters to the control device 9 of the typewriter 6 to be printed. At the end of each line, central unit 5 checks whether the next block contains an end-of-text character B (block 469).

If this character is not verified, central unit 5 determines via storage 42 whether the printed line is the last on the page (block 475). If it is not the last row, the central unit 5 repeats the same operation as described from the block 461 for the next data block whose address is identified by the first three characters of the previous block; As a result, the central device 5 carries out printing of all lines of the recorded page sequentially.The element part of the storage device 42 in which the first three characters of each block are recorded is always the same, since all It should be noted that this is because the blocks are recorded sequentially in the same element occupied by the preceding block.The operation of addressing each block in this manner is described with respect to FIG. On the other hand, when the last line of the page has been printed, the storage device 42 signals the end-of-page condition to the central device 5 (logical decision 475).

The central unit 5 enters the samurai state (block 468) and commands COP directed to the controller 11 of the keyboard 8.
The indicator lamp will be lit again. The operator is thus warned that the paper must be changed. Furthermore, the central unit 5 enters the address of the first line of the new page into the memory 42 as an input (block 460''). After changing the printing paper, the operator again depresses the interrupt key, thereby printing the new page. When the central unit 5 finally sees the end-of-text character E (logic decision 469), it causes the typewriter 6 to stop, with the result that the device returns to a stopped or inactive state (block 476). ).

It was stated that for line justification each block contains a character whose function is related to the length of the printed line.

More specifically, the fourth character indicates the number of characters that the block, hereinafter referred to as NI, may contain, and the fifth character indicates the number NE of characters actually contained in the block. When the data block is transferred to the central unit 5 (block 463 of FIG. 24) and the sixth character of the data block is 0 (block 464), the central unit 5 receives the command C
Bu by FR. The fourth and fifth characters of the block are compared (logical decision 470 in Figure 25). When these characters are equal, printing of the block begins from the seventh character upwards, so that no function character is printed (block 466). This is typewriter 6
This is achieved by the command COP directed to the control device 9 of the typewriter 6 (which command puts the control device 9 of the typewriter 6 in the receiving state) and the command CAP which transfers the characters from the storage device 42 to the control device 9 of the typewriter 6. In fact, the second character of the instruction CAP points to the address in storage 42 that corresponds to the seventh character of each block. If the result of the comparison between the 4th and 5th characters of the block is negative (bit E:0), the central unit 5 uses the command CDC to start from the 7th character of the block and Test that the character is not a single space character (logical decision 471).

If this character is not a single space character, i.e. it is a printing character or is followed by another space (bit E=0), the central unit 5 issues the command TRA
It executes a jump instruction SAL to the element section of the storage device 42 in which the character is recorded, and by this instruction TRA it transfers the examined character to a predetermined element section of the memory storage device 42 (block 472). If this character is a space character, the central unit 5, after transferring the space character, executes a jump command to the storage element section in which another command TRA is recorded.

This other instruction TRA causes the transfer of another space character to the storage element following the element to which the first space character was transferred (block 473).
Transfer of the characters completing this data block to subsequent elements then occurs as described above for block 472. After completing the data transfer, the central unit 5 transfers the function characters to the corresponding element units. In particular, the character NE is incremented by one unit amount and transferred (block 474). Therefore, due to these operations, the central bank counterfeit 5
causes a block of data to be transferred from a first register of a storage device to its second register, but inserts another space character after the first space character.

In this way, the print line is lengthened by a length corresponding to one space. After this, the central unit 5 again compares the characters NI and NE (block 470).

When these characters are not equal, it transfers the block from the second register to the first register, while the first
Insert another space character in the position following the second confirmed space character that is a single space. Central device 5
repeats this operation over and over until the character NE is equal to the character NI. When this occurs, the rows are applied right-aligned (block 466). For example, when the capacity of the data block is 60 characters (NI=60) and it contains 57 characters (NE=57), the central unit 5 performs the justification in three stages as shown in the table below. carry out.

Here, ND is the difference between NI and NE, and S1...
......S5 is between the first and second word of the line, between the second and third word, etc., respectively.
・It is the number of spaces. If after inserting one space character after every space character present in the printed line, the difference ND is still different from 0, the central unit 5 performs a comparison term for interword spaces so that two consecutive spaces are identified. increase. In this way, it inserts one space character between the words forming the line, repeating the same operation as described above with respect to FIG. Therefore, by these operations, each line is printed with the right end aligned at a predetermined position. When the line length is not reached even if two spaces are added to the spaces between words, for example at the end of a sentence where the text leaves a long section before reaching the end of the line, the justification process stops.

As mentioned above, the line end position can be changed by changing the character NI. By suitably varying the letters NI, it is possible, for example, to leave space in the text for inserting numbers, or to print the text in several parallel columns. It was mentioned that when the sixth character of a block is 0, the central unit 5 compares this character with the possible function characters by command CFR (block 467 in FIG. 24). When the central unit 5 recognizes a centering character, for example represented by the symbol ℃'', it compares the characters NI and NE under the control of appropriate commands, as in the case of justification. Sometimes, it transfers a data block from a first register to a second register of storage 42 in a similar manner, inserting two space characters in between, one space character being the seventh of the data block. Before the character, the other space character is inserted after the last character occupied by information. After each transfer it increases the character NE by an amount of 2 units. The difference between NI and NE is the final zero. When , it commands the contents of the block being centered. When the central unit 5 sees an underlined character, represented by the symbol "S", it commands the printing of the line recorded in the block.

Then, with the command COP, it sends a command to the control device 9 of the typewriter 6 ordering the carriage return without line spacing, so that the carriage is moved to the position at the beginning of the line. After that, the central unit 5 receives the command CDC
It is checked whether an underlined character is recorded in the element portion of the storage device 42 corresponding to the first part of the line.

When this character is recorded, the central device 5 instructs the printing of an underlined character by a command COP sent to the control device 9 of the typewriter 6, and this printing is carried out by the central device 5 after printing each underlined character. This continues until the underlined character recorded at the end of the word to be underlined is identified using successive commands CDC. When the central unit 5 confirms this last character, it sends a space character one after another to the control unit 9, which causes the carriage to move until it confirms the next underlined character.

When this occurs, central unit 5 performs the same operations as described above for underlining subsequent words.
Of course, when one underline character is recorded at the beginning of a block and one underline character is recorded at the end of a block, the central unit 5 underlines the entire corresponding line in the manner described above. When the carriage reaches the end of the line, carriage return with line spacing is automatically commanded in the manner previously described. C) Variation of the invention According to a variant of the invention, the command S can be combined into the command corresponding to the label REGI before recording the print line.

In this case, the underline character is used only to indicate the end of the word to be underlined, and is not used as an existing underline character in its own right. In this case printing is carried out under the conditions described for the previous case. According to another variant of the invention, the underlined character is placed in such a way that the character is assigned a code different from that of the character without underlining, for example by using the 8th bit of each bit. It is possible to condition the printing of characters to be underlined.

In this case, during the printing of a correct copy, the central device 5 decodes these characters in a known manner and then prints an underline symbol for each character in sequence, returns one step and commands the next character. When a symbol is associated with a so-called "dead key", ie, a print month key that does not command subasing, the command to go back one step after each underlined character is suppressed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a printing device according to the present invention. FIG. 2 is a block diagram of the central unit of the apparatus of FIG. FIG. 3 is a block diagram of the timing circuit of the central unit of FIG. FIG. 4 is a diagram of timing signals generated by the circuit of FIG. 3. FIG. 5 shows a circuit for generating the operating states of the central unit of FIG. 6-12 show command circuits corresponding to an equal number of operating states of the apparatus of FIG. FIG. 13 shows the input circuit of the central unit of FIG. FIG. 14 is a block diagram of a control system for the input and output devices of the apparatus of FIG. FIG. 15 shows the length of the magnetic tape for the device of FIG. FIG. 16 shows details of the tape of FIG. 15. FIG. 17 is a block diagram of a Hishitaka control device for recording and recording magnetic tape in the apparatus of FIG. FIG. 18 is a flowchart of the operation of the control device of FIG. 17. 19 and 20 are flowcharts of writing instructions to the device of FIG. 1. FIG. 21 is a flowchart relating to recording text. FIG. 22 is a flowchart relating to changing the format of text. FIG. 23 is a flowchart relating to the correction of lines of text. FIG. 24 is a flowchart relating to printing text. FIG. 25 is a flowchart relating to justifying lines of text. 5: central unit, 6: peripheral device typewriter, 7: magnetic tape storage device, 8: keyboard, 9: typewriter control device, 10: magnetic tape
centre. Storage device control device, 11: control device, 12: input/output device, 39: processing device, 42: core storage device, 20: timer, 21: oscillator, 22: shift register, 23: inverter, 24: AND gate circuit , 30: register,
44, 88: Counting circuit, 45, 62: Decoding circuit, 47:
Storage device input logic circuit, 63: Command logic device, 90: Exchange circuit, 98: Comparison circuit. Figure 3 Figure 1 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 25 Figure 21 Figure 22 Figure 23 Figure 24

Claims (1)

[Scope of Claims] 1. Means 270 for inputting each line of text information including a character signal and a space signal, for each line of text information, the number of space units (
means (27) for inputting line length information defined as
0, backspace key, L key, spacing key)
, and means (270, backspace key, L key) for inputting a text print line alignment signal (6th character = 0), and a manual input device 6 that stores the input information on the recording medium 310 and stores the input information on the recording medium 310. The first read in a predetermined order.
a second storage device 42 that receives information from the first storage device and stores one input line of text to be printed; and a second storage device 42 that receives information from the first storage device and stores character signals and space signals from the second storage device. a printing device 6 that prints one line of characters by sequentially receiving the characters, and is associated with the input device 6, the printing device 6, and the storage devices 7, 42, and responds to the print line alignment signal (character 6 = 0). A control device 5 includes a counting device (42 registers) for counting the number of space units regarding character signals and space signals actually included in one input line of text, and an output from this counting device. The number (NE) is the number that determines the line length (
A comparator (CFR, 470) for comparing with NI), which responds to this comparator and, if the number output from the counting device is smaller than the line length determination, the number stored in the second storage device 42 to be printed is A device (CDC, 471, TRA, 473) for storing one space unit signal that provides a space of one space unit width next to one space signal included in one input row; comprises a device 474 for incrementing said counting device each time said counting device is stored, and again after each increment of said counting device said comparator device compares the number output from the counting device with a number determining the line length; A device 5 operates the printing device to print one line according to the signal stored in the second storage device when the number output from the counting device becomes equal to the number defining the line length. A text processing device including a device (CAP, 466). 2. In the text processing device according to claim 1, the first storage device is composed of a magnetic tape that is divided into a plurality of blocks each capable of accommodating one line of text information, and the first storage device is configured to define the line length. The number is recorded as the first character in the predetermined first position of each block, and the number of space units for character signals and space signals actually included in the text input line is recorded in the predetermined second position of each block.
A text processing device in which the text is recorded as a second character at the position. 3. In the text processing device according to claim 1, the first storage device comprises a magnetic tape that is divided into a plurality of blocks each capable of accommodating one line of text information, and the first storage device defines the line length. The number is recorded as the first character in the predetermined first position of each block, and the number of space units for character signals and space signals actually included in the text input line is recorded in the predetermined second position of each block.
text processing in which the number defining the line length is variably settable by a manual input device, so that the format of each printed line can be selectively changed. Device. 4. In the text processing device according to claim 1, the first storage device comprises a magnetic tape divided into a plurality of blocks each capable of accommodating one line of text information, and the first storage device defines the line length. The number is recorded as the first character in the predetermined first position of each block, and the number of space units for character signals and space signals actually included in the text input line is recorded in the predetermined second position of each block.
, the number defining said line length being variably settable by a manual input device, so that the format of each printed line can be selectively changed; The device includes a device for inputting an end-of-line signal (carriage return) after inputting the character and space signals of each line, and said counting device (42 registers) is activated during input of each line to count the space units of that input line. The control device 5 includes a decoding device (CDC) configured to check the end-of-row signal, and when the end-of-row signal is verified by the decoding device, the control device 5 transmits the output of the counting device to the block. a device (TRA, 4) for storing in the second location;
21).