JPS6014435B2 - Storage device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a storage device.

In microcomputer systems, in order to reduce the number of wiring and IC package pins, a method is used in which data and addresses are output on the same bus in a time-division manner.

If a data processing device (hereinafter abbreviated as CPU) and a storage device (hereinafter abbreviated as memory) are manufactured using the same level of semiconductor technology, the operating speed of the CPU and the operating speed of the memory will be different. Compared to CPUs, memory is intended to have a larger capacity, and therefore has a larger number of active elements within the same area. Accordingly, the operating speed of the memory is slower than that of the CPU in terms of heat generation. In the past, various measures could be taken to use such slow memory.

For example, by using a high-speed, small-capacity cache memory configuration, by adding innovations to the CPU side, and by using polyphase control inside the CPU, during the waiting time for memory access, the CPU performs data processing inside the CPU, or by simply waiting. I was in a situation. However, the control of the cache memory is complicated, and the polyphase control inside the CPU is also wasteful in terms of the operating speed of the elements.

An object of the present invention is to provide a storage device that can shorten the effective access time.

Another object of the present invention is to provide a storage device that allows high-speed access even when relatively slow memory is used in a system in which part or all of data and addresses are shared between a CPU and memory. be.

If the content stored in the memory is a program, it is stored in an area of consecutive addresses in the memory.

Accesses from the CPU are also often performed in the order of addresses. Here, the memory is divided into multiple blocks. For example, if the memory block is divided into two memory blocks A and B, the contents of even addresses before division are collected in the memory block A, and the contents of odd addresses are collected in the memory block B in order. In this way, when block A is accessed, it can be predicted that block B will be accessed next, and the address is also the last one.
It can also be seen that if the bits are ignored, the value is the same as the address of the A block access.

At this time, if a register that holds the address value and a circuit that memorizes the next access are added to the memory block, it is necessary to wait for the memory access time Ta when accessing immediately after the address is sent from the CPU. When accessing continuously, Ta is reduced by the cycle time TC.
It is only necessary to wait for one TC time, and it can be considered that the memory access time is effectively shortened. 1 more
The address must be sent from the CPU to the memory the first time, but if you want to access consecutive addresses, you can use the address register of the memory block as a counter.
In the second and subsequent accesses, there is no need to send an address onto the bus, and the bus usage efficiency can be measured. FIG. 1 shows an embodiment of the present invention.

The figure shows a system in which a CPU IOO and a memory 200 are coupled via a bus 300. J Here, bus 300
can transfer both data and addresses. C
PUIOO is micro program counter (MPC) 1
01, and the contents of MPCIOI can be provided to memory 200 via bus 300. Data sent from memory 200 via bus 300 is sent to buffer 02.
be taken in. In addition, lines 103 and 104 indicate the memory 200.
This is a control line for controlling. There are multiple memories 200 (
Here, it consists of two memory blocks 210 and 220, each of which is composed of a semiconductor memory.

The memory block 210 includes a memory element array 211, an address counter 212, and an address determination circuit 213 formed on the same substrate. Memory block 220 is similarly configured. Address counters 212 and 222
is a presettable counter and can be set by taking an address on bus 300. In this system, the address of the memory 200 seen from the CPUIOO is
Memory bank 210 has a corner address, memory bank 2
201 odd addresses are assigned to each of them.

First, CPUIOO outputs the contents of MPCIOI, that is, the address, to the bus 30. At the same time, CPU10
0 brings line 103 low. Line 103 is bus 300
This shows the type of signal above; low level indicates address, and high level indicates data. memory block 2
When the 10, 22 river line 103 is at a low level, the signal (address) on the bus 300 is taken in. Assuming that the address consists of N bits, the contents of the upper (N-1) bits are set in the address counters 212 and 222, and the lowermost bit (B) is set in the address judgment circuit 21.
3 and 223. Each memory block reads data corresponding to an address from the storage element array according to the contents of address counters 212 and 222, respectively. However, these data cannot be output unless control signals 214 and 224 from address determination circuits 213 and 223 are supplied. Address judgment circuit 21
3, in addition to the signal on the control line 104 and the address determination circuit 223 of the memory block 220 via the line 301.
An output signal 224 is supplied.

The address determination circuit 223 includes the control line 104 in addition to BB.
and the output signal 214 of the address determination circuit 213 of the memory block 210 are supplied via the line 302. The difference between the address judgment circuits 213 and 223 is that the address judgment circuit 213 of the corner addressed memory block 210 is in a valid state when BB is "0", whereas the address judgment circuit 223 is in a false state when BB is "0". “1
”, the CPU is enabled.
If the address output from IOO is an even address,
The LSB is "0" and the address determination circuit 213 is enabled.

Next, after setting the CPUIOO' control line 103 to a high level, a read signal is output to the line 104 to perform data access. Here, the CPUIOO has two read timing sequences prepared. There is a timing A when accessing immediately after sending an address to the memory 200, and a timing B when accessing consecutive addresses. Since CPUIOO has just sent out the address, it sets line 104 to low level according to timing A.
The read signal on this line 104 is supplied to the address determination circuit 213 in the enabled state, and the address determination circuit 213
generates an output signal 214. This signal 214 causes the data in the storage element array 211 to be output to the bus 300 and taken into the data buffer 102 of the CPUIOO. Signal 214 is sent to address determination circuit 22 via line 302.
3, the address judgment circuit 223 is enabled, and the address counter 212 is incremented by one.

Although not shown, the address determination circuit 213 is released from the enabled state by the signal 214. When CPUIOO wants to read data at consecutive addresses from memory 200, it outputs a read signal to line 104 again from timing B'. This time, the address judgment circuit 223
Since the address determination circuit 223 is in a valid state, the address determination circuit 223
generates an output signal and the data in memory block 220 is output onto bus 300. Further, the signal 224 increments the address counter 222 by 1, changes the address judgment circuit 213 to the enabled state via the line 302, and releases the enabled state of the address judgment circuit 223. Similarly, each time CPUIO0 outputs a read signal to line 104 at timing B, memory blocks 210 and 220 operate alternately and sequentially send data at consecutive addresses to CPUIOO via bus 300.

Assuming that each memory block is formed using the same semiconductor technology and that its access time is Ta, only Ta is required to read data after the initial address is supplied to the memory block.

Timing A requires only the time specific to this memory.
However, when reading data at consecutive addresses, each memory block is already in a state where predetermined data can be selected and read from the storage element array according to the contents of its own address counter. Let Ta be the temporal ear Tc required to select
It is possible to read only the time Ta-Tc subtracted from . This is the effective access time at timing B. Therefore, according to the present invention, the apparent access time can be significantly reduced, and the speed of the memory can be substantially increased.

FIG. 2 shows another embodiment of the invention. In the same figure,
Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted. In FIG. 2, memory 20 functions as a control memory for CPU IOO. That is, the memory 200 stores a microprogram that defines the operation of the CPUIOO. Microprograms are often placed in memory in an orderly manner, but depending on the execution of certain instructions in the program, the contents of the memory may jump to other (address) areas that are not consecutive. For example, this is an instruction to read the contents of memory at a certain address into a register. In this case, the microprogram counter 10
Setting a value different from the value of 1 in the address counter of the memory 200 is inefficient because the CPU IOO must send the address again to the memory 200 in order to read the instruction at the address consecutive to this instruction.

Therefore, in FIG. 2, another control line 105
will be established. Further, each memory block 210, 220 has an address register 215, 225. CPUIO river is connected and there is no address (hereinafter referred to as a single address) on bus 3.
If 00' is sent, the control line 105 notifies the memory 200 that this address is a one-shot address. The memory blocks 210 and 220 check the state of the line 105, and if the address is a single address, the address register 2 is
Latch at 15,225. After the data corresponding to this single address is read from the memory 200,
Data at consecutive addresses can be read out in the same manner as in FIG. As described above, according to the present invention, high-speed reading can be performed even if a relatively low-speed memory is used.

In particular, the memory-using device does not need to send an address every time data is accessed, so the hardware configuration is also simplified. Further, particularly in semiconductor memories, if the initial address is inputted through a data terminal without providing an address terminal, the number of pins can be reduced, and this is suitable for large-capacity memories. It goes without saying that the present invention is not limited to the above embodiments.

Although the number of memory blocks is not essential, it is desirable to divide the memory blocks into 2n (n to 1) blocks in order to simplify the peripheral circuitry of the memory. Furthermore, in the embodiment shown in FIG. 1, since the conditions for enabling the address determination circuits 213 and 223 are different, it is necessary to manufacture two types of memories. To avoid this (that is, when using the same address determination circuit for memory blocks 210 and 220), if the initial address points to memory block 220 (odd address), the data is sent at timing A. The order of memory blocks that receive read signals may be determined in advance. This is the control line 104,3
It is determined by determining the connection method of 01 and 302. On the other hand, the CPUIO0' address B may be stored as the address that was just sent, and in the case of FIG. When).

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the invention, and FIG. 2 is a diagram showing another embodiment of the invention. 1 0 0...CPU, 2 0 0...Memory, 2 10,220...Memory block, 212,
222...address counter, 213, 223...address determination circuit, 300...bus. Figure 1 Figure 2

Claims (1)

[Claims] 1 A memory block equipped with a memory element array and a selection circuit for selecting a desired memory element in this array is integrated on the same substrate, and the address terminal and data terminal of this memory block are shared. , the selection circuit includes a counter for storing an address indicating a storage element in the storage element array, means for incrementing the counter in response to a data access, and means for incrementing the counter in response to the data access, and a means for incrementing the counter in response to the data access. and means for supplying a read signal to the block.