JPS6014436B2 - semiconductor memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory system, and more particularly to a semiconductor memory IJ system configured using static memory cells.

By placing a polycrystalline silicon layer above a field effect transistor built into a semiconductor substrate and using the polycrystalline silicon layer as a resistor element, the cell size can be reduced and the bit capacity of the memory within the LSI chip can be increased. , power consumption can also be reduced.

However, even with this method, as the memory capacity increases, the number of memory cells connected to the row line (word line) selected during reading increases in the memory cell matrix, and the load on the row decoder increases accordingly. , the 1/0 bus line, and the address buffer that drives the row decoder have the disadvantage of increasing power consumption.

Therefore, an object of the present invention is to provide a semiconductor memory system that can reduce power consumption and increase memory size.

According to the present invention, the above object is achieved by dividing a desired memory capacity into first and second memory cell matrices, and using a row decoder for row direction selection to select one of the first and second memory cell matrices. By arranging the line to select a predetermined row line, the number of memory cells selected by the row line is halved compared to the conventional one, the current flowing to the 1/0 bus line is halved, and the load on the row decoder is further halved. Line deco
This can be achieved by halving the power consumption of the column 11 and the power consumption of the address buffer that drives the row decoder.

The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a static random access memory (hereinafter abbreviated as S-RAM) as one of the conventional semiconductor memory systems. Table 1 shows the results of examining the ratio of power consumption to the whole in each part of this S-RAM. Table 1 As can be seen from Table 1, about 65% of the total power is occupied by the row and column (address) decoders and the 1/0 bus line (including memory cells).

This means that on the 1/0 bus line, the field effect transistors for address selection of all memory cells connected to the word (row) line selected by the row decoder are turned on, and the "0" of the memory cell is transferred from the digit line (column line). This is because current flows through the driving field effect transistor on the data side. Focusing on this point, the present invention reduces the number of memory cells arranged in the row direction selected by the word line when reading data by half, thereby reducing the power consumption in the 1/0 bus line, row decoder, and address buffer. This drastically reduces power consumption and the power consumption of the entire S-RAM. The present invention will be described below by applying it to an S-RAM with a 2048 word x 8 bit configuration.

In FIG. 2, AO to AIO are address terminals, and address terminals AO to A2 are address buffers ABO.
through AB2 to the input side of the column decoder 20. Address terminals A3 and A4 are address buffer AB3
, AB4, and its output is connected to the input of NOR gate G
It is connected to the input side of the row decoder 21 via I to G4. Address terminals A5 to AIO are address buffer A
It is connected to the input side of the row decoder 21 via B5 to ABI O. The output of the row decoder 21 is transmitted to the first memory cell matrix 22 and the second memory cell matrix 23.
connected to the row direction line (word line). This first and second
The memory cell matrices 22 and 23 each have 128 word lines and 64 column lines (digit lines) arranged in a matrix for 8 words each having 8 bits per word.
First and second memory matrices 22, 23 and column decoder 20 are each coupled to a 1/0 bus line 24. reading data from memory matrices 22 and 23;
Writing is performed via this 1/0 bus line 24. External data is sent to the 1/0 bus line 24 through input/output terminals loo to 1.
07 to 1/0 via input buffers IBO to IB7
Directed towards bus line 24, 1/0 bus line 2
Data is sent from 4 to the outside using the output buffer OB.
This is done through OB7.

Input buffers IBO to m7 and output buffers OBO
OB7 to OB7 perform data input/output control under the control of a control circuit 25 comprising NOR gates G5 and G6 and control signal input terminals CS, WE, and OE. Input terminal CS receives a chip select signal, WE receives a write enable signal, and OE receives an output enable signal. For example, when a write enable signal or a chip select signal is applied, an output is sent from gate G5 to input buffers IBO to IB7, and input data is sent to memory cell matrices 22 and 23 via 1/0 bus line 24. It will be done. Furthermore, when the output enable signal is applied together with the chip select signal, data is read out through the output buffers OBO to OB7. The memory cell matrix, input/output circuit, output buffer, and input buffer shown in Figure 2 are for 8 bits, but since they are all the same circuit, only 1 bit will be explained in detail below. do.

FIG. 3 is a specific circuit diagram of the row decoder 21, memory cell matrices 22, 23, and 1/0 bus line 24 in FIG. 2.

In FIG. 3, row decoder 21 is divided into 32 row decoder circuits RDO to RD31. Row decoder circuit RD is connected to word lines XO to X3 in memory cell matrix 22 and word lines x0' to x3' in memory cell matrix 23. Similarly, other word lines X4 to X127 and X4' to X127' are connected to four-by-four row decoder circuits RDI to RD31. Word line XO
The other ends of the word lines X127 are connected to the power supply terminals via the resistors RO to R127, and the other ends of the word lines XO' to X127' are connected to the power supply terminals via the resistors RO' to R127'.
Reference symbols YO to Y7 are the outputs of the column decoder 20,
A3 to AI0 and A3 to AIO are each address buffer A.
The outputs of B3 to ABI0 are shown.

Address buffer output AIO is connected to the gate of transistor QIO, output A9 is connected to the gate of transistor QII, A8 is connected to the gate of Q12, A7 is connected to the gate of Q13, A6 is connected to the gate of Q14, A5 is connected to the gate of Q15 . Q17,
A5 are respectively connected to the gates of Q16. Output A6,A
7, A8, A9, AI Kawama each transistor Q18, Q
Connected to the gates of I9, Q20, Q21, and Q22.
The sources and drains of transistors QIO to Q17 are connected in series, and transistor Q14 is connected to transistor Q15. Transistors Q18 to Q22 are connected to transistor Q16. Furthermore, transistor Q
16 has transistors Q23, Q26, Q29, Q32
is connected to the transistor Q23, and the transistor Q23 is connected to the transistor Q23.
4, Q25, Q26 and Q27. Q28 is connected,
Similarly, transistor Q29 is connected to transistor Q30.
Q31 is connected to transistor Q32, and transistor Q33 is connected to transistor Q32.
, Q34 are connected to each other. Transistor Q23 is a buffer circuit B composed of transistors Q35 to Q40.
connected to the word line XI through the transistor Q2
6 is connected to word line X through a buffer circuit B2 having a similar structure.

Transistors Q29 and Q32 are also connected to word lines XI' and XO' via similarly configured buffer circuits B3 and B4, respectively. A circuit similar to the circuit configured as described above connected to word lines X0, X1, XO', x1' is also provided in row decoder circuit RDO for word lines X2, X3, X2', X3'. It is being Other row decoder circuits RDI to RD31 are similarly configured. Note that the transistors QIO to Q13 and Q35 are depletion type transistors (hereinafter referred to as D-type transistors), the transistors Q14 and Q37 are transistors whose threshold voltage is near 0 volts (hereinafter referred to as type 1 transistors), and the transistor Q15 ~Q34,Q36,Q3
8 to Q4 are enhancement type transistors (hereinafter referred to as E-type transistors). The word line XO of the memory cell matrix 22 is connected to the word terminal of the memory cell CI, and the digit terminal of the memory cell CI is connected to the transistors Q41, Q.
42.

The word line XO' of the other memory cell matrix 23 is similarly connected to the word terminal of the memory cell C2, and the digit state of the memory cell C2 is connected to the transistors Q43 and Q44. Within the 1/0 bus line 24, transistor Q
41 and Q42 are connected to transistors Q45 and Q46, respectively, and transistors Q43 and Q44 are connected to transistor Q4.
8, connected to Q47.

Transistor Q41 is further connected to transistors Q49 and Q53.
At the connection point of transistor Q42, transistor Q50
, Q54, transistor Q43 is connected to the connection point of transistors Q51 and Q55, and transistor Q44 is connected to the connection point of transistors Q52 and Q56, respectively. The gates of transistors Q49, Q50, Q51, and Q52 are connected in common so that chip select signal CS is applied, and the gates of transistors Q53 and Q54 are connected to address signal A.
3, address signal A3 is applied to the gates of transistors Q55 and Q56. Next, the operation of the circuit shown in FIGS. 2 and 3 will be explained.

The circuit consisting of transistors QIO to Q22 is a NOR type decoder, which saves current by supplying the load side with an address signal having the opposite phase to the driver side. This decoder circuit selects two word lines from among the 12 word lines in the row direction. Load side transistor Q1
5. Use an E-type transistor for Q16, and use address signals A5, Q16, Q17 for transistors Q15, Q17.
By supplying the address signal A5 to the address signal A5, no current flows to the decoder not selected by the address signal A5. Furthermore, by using type 1 transistor Q14, current can be saved without reducing speed.
Next, a circuit consisting of transistors Q23 to Q34 selects one of the remaining two and selects the left and right memory cell matrices 22 and 23. A3/A4, A3/A created from signals at addresses A3, A4
4, one of the buffers BI to B4 is selected by the signals A3 and A4, A3 and A4, and the signals A3 and A3. Word lines XO to X12 depending on the selected buffer
7, one of XO' to X127' is driven, and the transistor for selecting the address of the memory cell following it is opened.
Buffers BI to B4 use a Pootstrap circuit,
The load transistor Q39 in the output stage is of E type, and the output is “
0" level so that no current flows. Also, a transistor Q37.Q is connected in parallel with the output stage inverter.
38 is connected, and its output is passed through a capacitor C to a transistor Q37. We are bootstrapping the node of the gate of Q39. Since the load capacitance of the output of the inverters connected in parallel is very small, the bootstrap speed is very fast and the transistor Q39 can be strongly driven. In addition, by using a type 1 transistor for transistor Q37, the gate width can be made smaller by using an E type transistor.
This also reduces the parasitic capacitance of the node that performs bootstrapping, making it easier to bootstrap. Node cut of the node to be put strapped is performed by transistors Q23, Q26, Q29, and Q32.
These transistors are used for left and right, upper and lower buffers BI~B.
It has the role of switching 4. Thereby, the number of transistors for the /door cut can be reduced by four. The output of the buffers BI to B4, that is, the word line X0
, X1, XO', ×1' (other word lines ×2 to X127
, X2' to X127' are driven by E-type transistors, so in order to keep the "1" level at the power supply level, resistors RO to R127 and R made of high resistance polycrystalline silicon are used.
It is backed up by O' to R127'. One word line on either side of the left or right memory cell matrix circuits sandwiching the row decoder circuit 21, that is, XO-X127, XO'-X12
Only one of 7' is selected.

Among the memory cells connected to the selected word line, data on the digit line selected by the outputs YO to Y7 of the column decoder 20 is led out to the 1/○ bus line 24.
For example, when the output YO is selected, data on the digit lines connected to transfer gate transistors Q41 and Q42 is transferred, but data other than the data from the digit line whose word line is not selected is not transferred. In FIG. 3, a circuit consisting of transistors Q45 to Q67 is a 1/0 bus line 24. Here, transistor Q
All E-type transistors are used except for 53 to Q56 and Q59, which are type 1 transistors. Transistor Q45~Q
48 is a load transistor, transistors Q49 to Q52
, Q57, and Q58 set all input/output circuit levels to “1” when the chip selection input terminal CS is at “1” level.
This is a load transistor to quickly maintain the CS level at the "0" level, and when CS is at the "0" level, the gate becomes the "0" level and is cut off. Transistor Q59 is CS
This is a transistor for shorting the nodes when the input terminal is at the "1" level. Transistors Q53-Q5
Reference numeral 6 designates a transfer gate for selecting a data line from which data of a memory cell selected by the row decoder 21 and column decoder 20 is output from the left and right memory cell matrices 22 and 23. Transistor Q53, Q5
The address signal A3 is supplied to the gate of Q4, and the address signal A3 is supplied to Q55 and Q56, so that the word line side selected by the row decoder is selected. A circuit consisting of transistors Q60 to Q63 and Q64 to Q67 is a writing circuit. Transistor Q64~Q
67 is a write circuit, and when reading, DIN, D
Both river inputs become "0" level, all are cut off, and at the time of writing, the DIN and DIN inputs are transferred and written into the memory cell. Transistor Q60~Q
The circuit consisting of 63 is a circuit for raising the "0" level of the data line to the original level when writing is completed. In this circuit, the followers were attached to each data line independently, but the transistor Q6 in Figure 3
0 and Q63 each serve as two conventional transistors, and transistors QS1 and Q62
A data line is driven through. During reading and writing, the "1" level of the data line is always at the level (V, V, V, H) as the power supply voltage Vcc threshold voltage V, so the "1" level of the transistors Q61 and Q62 The side connected to the side is always cut off, and only the side whose “0” level has been dropped almost to the ground level by the write circuit during writing is turned on, and when the write is finished, the level is returned to the original level. Pull up. The data passing through transfer gates Q53-Q56 then enters output buffers OBO-OB7 in FIG. 2, and the data appear at input/output terminals 100-107.

Next, the address buffer ABO that drives the row decoder 21
The detailed circuit structure of AB3 to AB5 of ABIO will be explained with reference to FIGS. 4 and 5.

FIG. 4 shows details of address buffer AB5 in FIG. 2.

Here, transistors QIOO to QI02, transistors QI03 to QI05, transistors QI06 to QI0
8 are connected in series. Furthermore, transistor Q
IOS-QII1 and QI13-QI15 are connected in series, QI12 is connected in parallel to transistor QI11, and QI16 is connected in parallel to transistor QI15. The gates of transistors QIO0, QI03, and QI06 are commonly connected and supplied with a chip select signal CS, and the gate of transistor QI02 is supplied with an address signal A5. The chip select signal CS is also supplied to transistors QIO9 and QI13, and the CS signal is supplied to the gates of transistors QI12 and QI16. Internal address signal A5 is transmitted through transistors QII0 and QII1
, QI12, and the internal address signal A
5 is supplied from the connection point of transistors QI14, QI15, and QI16. Here, transistor QIOO. Q
I03, QI06, QIO9, QI13 are type 1, QIO
1, QI○4, QI07, QII○, QI14 are D type,
QI02, QI05, QI08, QIII'QI12,
QI15 and QI16 are E-type transistors. From external address signal A5 to internal address signal A5, A
Generate 5. When the CS input terminal is at ``1'' level, both internal address signals A5 and A5 are dropped to ``0'' level. Internal address signals A5 and A5 are transmitted through transistors Q15 to Q17 of row decoder 21 in FIG. Q17', and when the CS input terminal is "1", both A5 and A5 signals are at "0" level, so transistors Q15 to Q
17, Q171 are all cut off, and the current to the row decoder is cut off.
The details of part 4 are shown.

Transistors QI17, Q120, Q123, Q145
, Q148, Q151 are type 1, transistor QI18,
Q121, Q124, Q126, Q127, Q130,
Q131, Q134, Q135, Q138, Q139,
Q146, Q149, Q154, 157, Q156, Q
159 is a D-type transistor, and the others are E-type transistors. Internal address signal A3 from external address signals A3 and A4
, A3, A3・A4, A3・A4, A3・A4, A3・
Generate A4. When the CS input terminal is at the "1" level, the current is reduced by the type 1 transistor. A3, A
At that time, the signals of 3 are both pulled up to the "1" level by transistors Q156 and Q159. Internal address signals generated from external address signals A3 and A4 select the left, right, top, and bottom word lines in the row decoder 21 of FIG. The circuit configuration described above has achieved a significant reduction in power consumption.

As a result, the power consumption distribution was as shown in Table 2. As a result, a single-bit S-RAM with a total current consumption of 70 mA and an access time of 8 seconds was obtained. Table 2 The S-RAM from which the results shown in Table 2 above were obtained has the circuit configuration shown in Figures 2 to 5, and the memory cells composing the memory cell matrices 22 and 23 are shown below. I used a configuration like this.

This will be explained below. The plane pattern diagram of each four memory cells shown in FIG. 6 depicts a diffusion region, a first polycrystalline silicon pattern, a data wiring pattern, a power supply wiring pattern, and a word line pattern. This shows a resistive element connected to the outside of the transistor shown in FIG. 6, in which a second polycrystalline silicon pattern is drawn with respect to a first polycrystalline silicon pattern. Figure 8 is an equivalent circuit diagram drawn for Figures 6 and 7, Figure 9A
-E show manufacturing processes for explaining the contact method of the first and second polycrystalline silicon layers shown in FIGS. 6 and 7. In FIG. 6, a 1/4 area area in the upper left corner is a portion of one memory cell, and four field effect transistors Q.sub.2 to Q.sub.2 are built therein. Similarly, bottom left,
Ishigami, the remaining three memory cells in the lower right are transistor Q.
Formed by ■～Q■. Reference number D1, D1, D
2 and D2 indicate digit line patterns, and W1 and W2 indicate wide line patterns. These transistors Q■ to Q■ have a structure with a gate called a polysilicon gate, and the gate electrode is connected to the first polycrystalline silicon layer la, l.
b, 2a, 2b, 3a, 3b, 4a, 4c. Among these transistors Q■ to Q■, driver transistors Q■, Q■, Q that constitute a flip-flop
■, Q■, Q■, Q■, Q■, Q■ are respectively two driver transistors Q■Q■, considering the improvement of their performance and the reduction of the occupied area. Q■Q■,Q■Q■,Q■,
Q■ is formed facing the fishing shape. On the other hand, switch transistors Q■, Q■, Q■, Q■, Q■, Q■
, Q■Q■ only perform switching, so the size can be made small. Here, it is desirable that the diffusion capacitance of the source and drain regions constituting the transistors Q2 to Q2 be formed as small as possible in order to keep the leakage level of the memory cell as good as possible. Therefore, in the memory cell shown in FIG. 6 with these configurations,
The area occupied by the diffusion pattern and gate pattern per memory cell is the minimum size, and high speed is taken into consideration. Incidentally, in FIG. 6, number 6 is a contact portion of the power supply. By the way, in this memory cell, a second polycrystalline silicon layer (pattern in Fig. 7) that acts as a load is provided above the drive transistors Q■Q■, Q■Q■, Q■Q■, Q■Q■. As shown in FIG. , R■ for Q■, R■ for Q■, Q
R■ for ■, R■ for Q■, R■ for Q■
, Q■ are connected as R■, respectively.
A current path is formed between the power supply line Voo and the ground line Vss, but when structuring them, the same current path is formed above each transistor, such as R■ for transistor Q■. Place a resistor that acts as a load.

By the way, the data lines D1, D1, D2, D2,
The ground line Vss and the power line Voo are formed of aluminum in the same process, but in order to effectively run these lines, it is required that the underlying region be effectively arranged. In the memory cell used in the present invention, since the base region is processed by connecting the power supply line VoD ground line Vss with one metal line, the element arrangement per 4 bits is such that each memory cell block has a rectangular shape. At the same time, the fourth blocks (Q13-Q
16) is the third block for the second block (Q5 to Q8).
The blocks (Q9 to Q12) are arranged symmetrically with respect to the same midpoint. Then, the drive transistors Q■, Q■, Q■, Q■, Q
■． Q■, Q■, QQ students respectively Q■, Q■
They can be formed back to back, such as Q■ for Q■, Q■ for Q■, and Q■ for Q■, and the diffusion region can be the same region for each transistor. It will be possible. Therefore, the wiring contact can be taken out at one point in this diffusion region.
Not only can the wiring be reduced to one, but it also eliminates the need to provide contacts for each flock, reducing the number of contacts and improving yield. By the way, the structure of the above-mentioned mori cell is difficult to understand because it is planar in Figures 6 and 7, so its structure is shown in Figures 9A to 9E.
This will be explained using a manufacturing process diagram as shown in .

9A to 9E are shown at the cross-sectional positions taken along line A-A' in FIG. 6. In FIG. 9A, a field insulating film 92 is formed on a P-type semiconductor substrate 91, and a thin insulating film 93 is formed in the active region.

This becomes a gate oxide film 93. Then, a portion (peride contact) 94 that directly contacts the polycrystalline silicon layer
, 95 are removed, and a first polycrystalline silicon layer 96 is deposited over the entire surface of the substrate 91 including these regions 94 and 95. These first polycrystalline silicon layers 96 are subjected to a photolithography process, leaving only necessary portions 96' as shown in B, and the remaining first polycrystalline silicon layers 96 are
The thin insulating film 93 is removed using ' as a mask.

Since the surfaces of the base 91 are exposed in the removed portions, impurities are diffused from these surfaces to form N-type impurity regions 97 to 100 that function as sources and drains. At this time, since impurities are diffused into the first polycrystalline silicon layer 96', the first polycrystalline silicon layer 96' becomes conductive and can be used as a gate electrode and wiring. After forming these diffusion regions 97 to 100, a first insulating film 102 is formed as shown in C, and a contact portion 103 with the diffusion region 98 and the first polycrystalline silicon layer 96' is opened. Thereafter, as shown in D, a second polycrystalline silicon layer 105 is formed over the entire surface of the substrate including these openings 103. These second polycrystalline silicon layers 105 are provided with a desired sheet resistance, and by partitioning them, desired resistance values can be selected as the resistors R1 to R2 shown in FIG. Next, the second polycrystalline silicon layer 105 is patterned by photolithography, such as dry etching.

(See Figure 7) Next, on the top surface there is a second
An insulating film 108 is formed, and a contact 106 for guiding an electrode wiring to the second polycrystalline silicon layer 105 is formed together with other contact holes (not shown). Subsequently, electrode wiring 109 is formed. These wiring 109
112, the form of each part of the first polycrystalline silicon layer 96' and the second polycrystalline silicon layer 105 will become clearer if FIG. 6, FIG. 7, and FIG. 9 are made to correspond. Note that the second polycrystalline silicon layer 1 in contact with the N+ region 98 in the step of FIG. 9D
The contact portion 05 undergoes back diffusion of impurities from the region 98 when subjected to heat treatment in the subsequent E step, and an ohmic contact is formed between the two 98 and 105.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional static random access memory, FIG. 2 is a block diagram of a static random access memory according to an embodiment of the present invention, and FIG. 3 is a block diagram of a static random access memory according to an embodiment of the present invention. A specific circuit connection diagram of the row decoder and 1/0 bus line, FIGS. 4 and 5 are circuit connection diagrams of the address buffer in FIG. 2, and FIG. 6 is a memory used in the embodiment of this invention. A plane pattern of a part of a cell, FIG. 7 is a pattern of a polycrystalline silicon layer formed on the pattern of FIG. 6, FIG. 8 is a circuit diagram of the memory cell shown in FIG. 6, and FIG. FIG. 6 is a process diagram for explaining the manufacturing process of the portion cut along line A-A' in FIG. 6; 20... Column decoder, 21... Row decoder, 22... First memory cell matrix, 23... Second memory cell matrix, 24... 1/0 bus line,
25... Control circuit, Q■, Q■... Drive transistor, R■, R■... Load resistance, 9
1... Semiconductor base, 92... Field insulating film, 93... Gate oxide film, 96, 96
'...first polycrystalline silicon layer, 97-100...
...Impurity region, 103... - Contact hole, 105... second polycrystalline silicon layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1 a first memory cell matrix, a second memory cell matrix, a first decoder that selects a predetermined row line of one of the first and second memory cell matrices; A transistor for transmitting both H and L levels of the decoder output is connected in series on each row line between the decoder and the first and second memory cell matrices, and an output compensated for the voltage drop in this transistor is provided. a second decoder for selecting one of the column lines of the first and second memory cell matrices that intersects the selected line; A semiconductor memory system comprising: an I/O bus line for outputting data read from a memory cell matrix selected from a first or second memory cell matrix by an output of a decoder.