JPS6014440B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory in which a memory cell is an IG-FET (insulated gate field effect transistor) having charge trapping means in a gate insulating film.

Conventionally, as a nonvolatile semiconductor memory whose memory cell is an IG-FET having a charge trapping means (floating gate) in a gate insulating film, for example, EPROM (Erasab
There is a programmable ROM).

Information can be written to the IG-FET having a floating gate by, for example, setting the source to the ground level, applying a program voltage (for example, 25 V) to the gate and drain, and injecting electrons into the floating gate by impact ionization. Let's do it. Figure 1 shows an EP like the one above.
This shows the configuration of the ROM, and is an example of 4-bit output.

That is, the memory cell array 1 includes IG-FETs (memory cells) M, . ~Mmn, which is provided for 4 bits. The row line has a write load circuit 2 that applies a program voltage to the row line during writing, and an address input Ao.
The row decoder 3 selected at ~A5 is connected. A column line is selected by a column selection gate 4, and a write load circuit 5 that applies a program voltage during writing and a column decoder 6 selected by address inputs A6 and A7 are connected to the column selection line that selects this column selection gate. be done. The output of the selected column line that has passed through the column selection gate 4 is connected to an output circuit 9 via a write circuit 7 and a transmission gate 8 that is turned on only during reading to transmit column line information. Here, the signals R/W and R/W are “1” and “1” respectively at the time of reading.
0", and becomes "0" and "1" during writing. Also, the program voltage is supplied from the program power supply, and the program power supply voltage VP is 25V and the power supply voltage Vc is 5V. FIG. In the detailed circuit diagram of 10,
When the input DIN is "0", the transistor T is turned on and the program power supply voltage VP is sent to the column line.

When writing information to the EPROM configured as described above, when the write mode is set, the signal R/W is set to "1" (25V in this case) by the write control circuit (not shown).
R/W becomes "0", and the transistors T2, ~T2n, and ~Tyanagi of load circuits 5 and 2 are turned on, but "high voltage is applied only to the selected row line and column selection line from the program power supply VP. is applied.

Also, an input circuit 10 that operates according to input information D, N, -D, N4 of the write circuit 7. The outputs of transistors T, . ~T,4 is turned on or off, the selected column line and power supply VP are connected, and information is written into the memory cell. For example, by row line R and column line CS, column line C. is selected, the memory cell M, is selected, a high voltage is applied from the power supply VP to its gate and drain, and electrons are injected into the floating gate, thereby allowing information to be written. In the above writing method, only one cell (four cells in a 4-bit configuration) can be written at a time per one output (one bit).
However, since the time required to write to this nonvolatile memory cell is approximately 50 ms, the test time, especially the time in the die sort test process at the semiconductor wafer stage, increases significantly. 4096 words x
In the case of 8-bit) memory, approximately 200 to 300 chips can be obtained from a 100-side wafer. Therefore, assuming the yield of writable (normal) chips as 300 chips/wafer is 50%, the time required for the write test is 300 x 0.5 x 4096 x 50XIO-3 = 3072
Nosa=8-insect time, resulting in a huge amount of test time.

The present invention has been made in view of the above-mentioned circumstances, and it divides the memory into a plurality of memory flocks, selects any plurality of these memory flocks at the same time, and processes the selected memory flocks. The object is to provide a non-volatile semiconductor memory that can shorten test time by writing data into each data.

An embodiment of the present invention will be described below with reference to the drawings. Third
The figure is a block diagram showing the same embodiment, and corresponding symbols are used for parts corresponding to those in FIG. 1. In this configuration, the first
A major feature is that the memory array 11 shown in the figure is divided into four, for example, into memory blocks 11.about.114. Here, 1, to 14 are memory cell arrays divided into four, 21 to 24 are write load circuits, which are also divided into four, 3, to 34 are row decoders, and 4, to 44 are column selection gates. , 5, to 54 are the same write load circuits, 6, to 64 are the same column decoders, 7, to 74 are the same write circuits, and 8, to 84 are the same transmission gates, but the mutual wiring within each block is different from each other. The structure is similar to the conventional one to obtain a 4-bit output. To select one of the memory blocks, the memory block selection/non-selection circuit 21 sends a signal MS, , MS, ~MS4, MS4 to the address input, which is selected by A.
controlled by Write load circuits 21 to 24, 5, to
54 is controlled by the selection/non-selection circuit 22 of the write load circuit. The outputs of the column decoders 6, .about.64 and row decoders 3, .about.34 of each block are selected by address inputs .about.A7. 23 to 30 are address buffers.

The outputs of the memory blocks 11, - 114 are sent to the write circuit 7. ~74 and is connected to transmission gate 8
, to 84 are commonly connected to the output circuit 9. The write circuits 7, ~74 output the outputs WS, ~TS4 of the selection/non-selection circuit 31 of the write circuit, and the output D of the input circuit 32.
,N. The multiple write switching circuit 33 is
In order to select multiple memory blocks and perform simultaneous writing (multiple writing) to multiple memory cells, signals MW, MW2, MW2, and
MW,. Send MW2 to enter multiple write state. Fourth
The figure shows a specific example of the address buffer 23 or 24.

Here, 41 to 44 are transistors (hereinafter referred to as i-type transistors) whose threshold voltage is approximately zero volts.
5 to 47 are depression type transistors, 48 to 56
is an enhancement type transistor. Signal MW,
or MW2, MW, or MW2 are typically “
0”, “1”, and the address buffer 23 or 2
4 performs normal operation according to the address input or A, but a multiple write state occurs and the signal MW or MW
When 2, MW, or MW2 becomes "1" and "0", respectively, the address outputs, a, a, a, and a, are all "0". FIG. 5 shows a specific example of the multiple write switching circuit 33. shows.

Here, 61 to 64 are depletion type transistors, 6
5 to 68 are enhancement type transistors. In this circuit, the address input Ao or A, for example, is 10V.
An inverter 69 that senses “1” above (multiple write state) and “0” below (normal state)
and the output MW, or MW2, MW, or M
Get W2. That is, when the voltage to the address or A is 10V or less, the output MW. or MW2 is “0”, MW, or MW
2 becomes “1”, and when N or A, is 10V or more, MW
, or MW2 is “1”, MW, or MW2 is “0”
and controls the address buffer shown in FIG. 6th
A specific circuit example of the memory block selection/non-selection circuit 21 is shown in the figure. Here, 71 to 74 are depletion type transistors, and 75 to 79 are enhancement type transistors. This circuit has inputs ao and a,, ao and a,,
Four circuits are provided for ao and a, , ao and a,. This circuit receives address outputs ao to nen, a to a, and outputs outputs MS to MS4, MS to MS4. Normally, one of MS, .about.MS4 and MS, .about.MS4 becomes "1" and "0", respectively, depending on the state of the address output. At the time of multiple writing, the outputs MS, ~MS4 are all "1", and the outputs MS, ~M are all "0" because heat and a, and heat and a are all "0".
S4 is all ``0'', and memory block 11,
.about.114 are all selected to enable multiple writing. FIG. 7 shows a specific circuit example of a row decoder (or column decoder). Here, 81 is an i-type transistor, 82 to 84
are depletion type transistors, and 86 to 89 are enhancement type transistors. The normal operation of this circuit is that for the selected memory block, the signal MSi="1".
”, MS,=“0'1 (ISi mi 4), so an output corresponding to the address output can be obtained. In the non-selected memory block, the signal MSi="0" and MS,="1", so the output will be "0" regardless of the address output.
No memory cells are selected. On the other hand, during multiple writing, as mentioned above, MS, ~MS4 are all "1", and MS
, -MS4 are all "0", so all memory blocks 11, -114 are selected, and outputs corresponding to the address outputs can be obtained from all memory blocks. FIG. 8 shows a specific circuit example of the selection/non-selection circuit 22 of the write load circuit.

Here, 91 to 93 are depletion type transistors, 9
4 to 98 are enhancement type transistors. The circuit of FIG. 8 is provided with four circuits for inputs and a, , father and a, , also and a, , and a, and has a signal R.
Signals R/W, to R/W4 are obtained from /W. The write circuit selection/non-selection circuit 31 has a configuration corresponding to the memory block selection/non-selection circuit 21. Therefore, it may be considered that the signal WS,=MS, or WS4=MS4. A specific circuit example of the write circuit 7, for example, in FIG. 9 is shown.

Here, 101 to 103 are depletion type transistors, and 104 to 108 are enhancement type transistors. In this circuit, the signal D...="0" and WS,="
1'', the transistor (corresponding to the transistor T, . in FIG. 1) that sends the program power supply voltage VP to the column line is turned on at the output OUT.The write circuits 72 to 74 have the same configuration as the write circuit 7. However, the contacts at which the gate inputs of transistor 06 in FIG. Since the memory block is divided so that multiple writing can be performed in each memory block, the time required for the write test is reduced to 1'4 compared to the case shown in FIG.

Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, in the embodiment, write circuits 7, - 74 and transmission gates 8, -
84 is provided for each memory block, however, only one transmission gate may be provided in common, or one writing circuit and one transmission gate may be provided in common. In this case, the write circuit selection/non-selection circuit 31 is no longer necessary. Alternatively, the write load circuit selection/non-selection circuit 22 may not be provided, and the write load circuit may be controlled by a corresponding signal. Further, although the multiple write gate circuit 33 is provided for each address A, one circuit may be provided for each address. In this case, the degree of freedom in cell selection is lost, as only all memory blocks can be selected. Further, although the address input is used as the multiple write switching signal, other signals may be used, and a dedicated terminal (pad) used only during testing may be provided. Further, in the embodiment, four row decoders and four column decoders are provided, but four column decoders and four write load circuits may be provided by using a common row decoder including a write load circuit. 10th
The figure shows an example in which row decoders and column decoders are each commonly connected. That is, write circuits 7 and 74 and sense amplifier 1101 are connected to column selection dates 4 and 44, respectively.
~1104 are provided, and the sense amplifier outputs are commonly connected and sent to the output circuit 9, and one of the write circuits and sense amplifiers of the memory blocks 111 to 114 is selected by the address signal N,A, to perform normal operation. At the time of multiple writing, the multiple writing gate circuit 33 controls the address buffers 23 and 24 to write the write circuits 7, to 7.
4 are selected at the same time. In addition, in the embodiment, all 4 cells (actually 16 cells because of the 4-bit configuration) were written simultaneously, but for example, if one of the address signals, A, is in the multiple writing state, 2 cells (4 cells)
(8 cells in bit configuration) may be written simultaneously. Further, in the present invention, the number of memory blocks can be increased as long as the number of addresses is increased, and in principle, it is possible to write to any number of cells at the same time, ie, two or more cells. As explained above, according to the present invention, a subordinate memory array is divided into a plurality of memory blocks, arbitrary plurality of blocks are selected simultaneously, and writing is performed in each of these selected blocks. As a result, the test time can be shortened.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing the configuration of a conventional EPROM, FIG. 2 is a partially detailed circuit diagram of the same configuration, FIG. 3 is a configuration diagram showing an embodiment of the present invention, and FIG. 4 9 to 9 are partially detailed circuit diagrams of the same configuration, and FIG. 10 is a configuration diagram showing another embodiment of the present invention.

1,~14...Memory cell array, 2,~24,5
, ~54...Writing load circuit, 3, ~3
4... Row decoder, 4. ~44... Column selection gate, 6, ~64... Column decoder, 7, ~74
...Writing circuit, 11. ~114... Memory flock, 21... Memory flock selection/non-selection circuit, 22... Write load circuit selection/' selection circuit, 23-30... Address buffer, 31・
...Writing circuit selection/non-selection circuit, 33...
...Multiple writing successful fusuma circuit.

Figure 1 Figure 2 Figure 3 Fifth... Figure 4 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10

Claims (1)

[Claims] 1. A row line, a memory cell consisting of an IG-FET driven by the row line and having means for storing charge in a gate insulating film, a column line connected to the memory cell, and one row line and one column line each. a memory block group comprising a plurality of memory blocks each having a decoder section that selects one memory cell at a time, and a control means for writing information into one memory cell selected by the decoder section according to external input data;
A method for simultaneously writing information into a plurality of memory cells is provided with the aforementioned block group when writing information and selection means for simultaneously selecting any plurality of memory blocks from the aforementioned block group when writing information. A nonvolatile semiconductor memory characterized by selecting a plurality of memory blocks for writing information into cells.