JPS6015166B2 - Electronic channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic channel selection device applied to receiving devices such as television receivers and FM receivers.

In a tuner having a variable reactance element for tuning, the reception frequency is determined by the tuning voltage. To easily generate a tuning voltage, use multiple variable resistors, preset the resistance value of the variable resistor, and then selectively supply the tuning voltage generated by the variable resistor to the tuner by tuning operation. Just do it. However, the preset operation is complicated due to the use of a variable resistor, and the DC stability is insufficient due to the presence of contacts. A frequency synthesizer type electronic tuning device using a PLL does not have such drawbacks, but it has problems in that fine tuning is difficult and an expensive programmable variable frequency divider is required.
The present invention aims to provide an electronic channel selection device that does not use a variable resistor and does not suffer from the problems that would occur when using a PLL.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, numeral 1 indicates a channel designation switch consisting of a 1M push key representing numbers 0 to 9. A channel number code corresponding to the one pressed on the channel designation switch is supplied to the address control circuit 2, and the station memory 3 is configured as a non-volatile RAM.
address is specified by the channel number code. A memory control circuit 4 and a band switching signal generator 5 are provided in association with the station memory 3. A mode changeover switch SW and a write switch SW2 are provided in connection with the memory control circuit 4. When the mode selection switch SW, is connected to the a side, the program mode is set in which the voltage code from the station counter 6 can be written to the station memory 3, and the mode selection switch SW, is connected to the b side. When the channel selection switch 1 is operated, a corresponding channel is selected. When the write switch SW2 is turned on in the program mode, the voltage code is written into the station memory 3. In addition, in connection with the band switching signal generator 5, a band designation switch S&
, SB2, S& are provided. In the program mode, the band designation switch is selectively operated, and VHF
The band's roach yannel, its Haitian yannel, UHF
Band switching signals (codes) corresponding to the three bands are input to the station memory 3. The station counter 6 is an addition/subtraction counter, and its addition input terminal U receives a pulse via a gate circuit 7U or 8U, and its subtraction input terminal D receives a pulse via a gate circuit 7D or 8D. This gate circuit 7U, 7
Pulses from the pulse generator 9 are applied to D, 8U, and 8D. The gate circuits 7U and 7D are controlled by a manual upward sweep switch 10U and a downward sweep switch 10D, respectively. When one lift switch 10U is turned on, the gate circuit 7U is turned on, and the pulse from the pulse generator 9 is supplied to the addition input terminal U of the station counter 6 via the gate circuit 7U. When the other downward switch 10D is turned on, a pulse is similarly supplied to the subtraction input terminal D of the station counter 6. Gate circuits 8U and 8D are controlled by a digital AFT signal, which will be described later. The voltage code from the station counter 6 is converted into a tuning voltage by the DA converter 11, and the VHF
and UHF tuner 12.

A band switching signal from the station memory 3 is also supplied to the tuner 12, and the tuner 12 is controlled to receive a predetermined channel. The video intermediate frequency signal obtained from the tuner 12 is applied to a video signal system similar to a normal video signal system including a video intermediate frequency amplifier, a video detector, a video amplifier, etc. (not shown). In the channel selection device of this example, the receiving channel is first programmed. Therefore, the station counter 6 is reset and the mode changeover switch SW is connected to the a side. In the case of the Tokyo area, first the band designation switch SB is pressed, the tuner 12 is placed in the VHF band low channel reception state, and the number key 1 is pressed on the channel designation switch to select the corresponding channel number. The code is supplied to the address control circuit 2 and the address of the station memory 3 is designated. Further, the AFT switch 13 is manually turned off, and the AFT loop is broken. Then turn on the lift switch 10U. As a result, the gate circuit 7U is turned on and the pulse from the pulse generator 9 is applied to the addition input device U of the station counter 6, so that the voltage code generated by the station counter 6 increases. Along with this, the tuning voltage formed by the DA converter 11 also increases. Conversely, when the descending switch 100 is turned on, the tuning voltage decreases. While looking at the screen, turn on the sweep switch 10U or 10D to receive one channel. Thereafter, the write switch SW2 is turned on to erase the contents of the designated address, and then write the voltage code corresponding to one channel from the station counter 6 to this address. The same goes for the next 3-channel writing. Mode changeover switch S
W. In the channel selection mode where is connected to the b side, the AFT switch 13 is turned on manually, and the corresponding voltage code is read from the station memory 3 by specifying the channel number with the channel designation switch 1 and transferred to the station counter 6. be done.

The voltage code transferred to the station counter 6 is corrected by an AFT operation or a fine tuning operation, which will be described later, and this corrected voltage code is converted into a tuned voltage by the DA converter 11. By supplying this tuning voltage, the band switching signal from the station memory 3, and the tuner 12, the selected channel can be received.
A local oscillation (hereinafter abbreviated as local oscillation) signal of the tuner 12 is supplied to the tube divider 14 .

The frequency of the frequency divider 14 is divided by the number of employee turnover (f). The output pulse of frequency divider 14 is applied to AND gate 15 .

16 is a reference oscillator, for example, 1 [MH
2] signal of the reference frequency is generated.

It is supplied to the frequency divider 17 of the starting rib (I 4) of the standard grader 16,
The output pulse of frequency divider 17 is supplied to AND gate 15 via delay circuit 18 . The output of AND gate 15 is 1
It is input to a 5-bit comparison counter 19. The comparison counter 19 is preset with the channel frequency code extracted from the channel frequency memory 20. - The output of the frequency divider 17 is used as a load pulse for this purpose. The channel frequency memory 20 has a ROM configuration, and its read address is the channel number code from the channel designation switch 1 which is the address control circuit 21.
determined by the amount supplied to the This channel number code is also supplied to the display decoder 22, and the channel number is displayed on the display section 23. Furthermore, a reset signal generator 24 is provided in association with the channel designation switch 1, and the comparison counter 19 is reset by a reset signal generated each time the channel is switched. The comparison counter 19 performs an operation in which the output of the AND gate 15 is subtracted from the preset channel frequency code.

The 15-bit output of the comparison counter 19 and its borrow output P are combined with the discrimination circuit 25. This discrimination circuit 2
5 is also supplied with the output pulse of the delay circuit 18. The contents of the comparison counter 19 are separated at the falling timing of the output pulse of the delay circuit 18. In other words, when the output pulse of the delay circuit 18 falls, no borrow output has occurred and all 15 bits of the comparison counter 19 are "0", the determination pulse P2 is generated, and at the time of the same aircraft, the comparison counter 19 If even one bit out of the 15 bits is "1", a determination pulse P3 is generated. The discrimination pulse P2 has a local frequency f,
indicates a tuned state in which is a specified value, and the discrimination pulse P3 is
It shows that the local oscillation frequency fl is lower than that, and the pollo output P, of the comparison counter 19 shows that the local oscillation frequency f, is higher than that. RS flip-flop 26U, 26D
is reset by the discrimination pulse P2, the flip-flop 26D is set by the pollo output P, and the flip-flop 26U is set by the discrimination pulse P3. This flip-flop 26U, 26D
The output of E river E. becomes a digital AFT signal, and this AF
The T signal is passed through the AFT switch 13 to serve as a control signal for the gate circuits 8U and 8D, so that the gate circuits 8U and 80 are turned on when the AFT signal is "1". The channel frequency code is the local frequency fl
32 times the number is expressed in a 15-bit BCD code. For example, the local oscillation frequency of the VHF band and the number 32 times the number are shown in the table below.

As an example, when selecting channel 6,
As described above, the AFT switch 13 is manually turned on, and the push button number 6 is pressed on the channel designation switch 1, so that the tuner 12 is placed in a state where it receives channel 6.

The local oscillator signal of the tuner 12 is supplied to the frequency divider 14, and the frequency divider 14 generates the pulse shown in FIG. 2A. Now, if the local oscillation frequency fl is the specified value (242 [MHZ]),
In the period of the output pulse of the frequency divider 14 (T silkworm visit; [mS
]) becomes. Moreover, the output pulse of the frequency divider 17 is
As shown in Figure B, the power rises at a constant period 16. Paper 4 [
ms], and therefore the period of "1" among them is 8.
It becomes 192 [ms]. The comparison counter 19 is preset at the rising edge of the output pulse of the frequency divider 17. A load pulse for presetting is shown in FIG. 2C.
The comparison counter 19 is preset with a BCD code corresponding to 7744 as shown in the table above. The output pulse of the delay circuit 18 is as shown in FIG.
A pulse shown in FIG. E appears, and this is taken as the subtraction input of the comparison counter 19. Comparison counter 1 and gate 1 to 9
The number of pulses combined from 5 (half base 2 = 7744
) and match the set channel frequency code value. As shown in FIG. 2F, the content of the comparison counter 19 is determined by a pulse generated at the falling time t3 of the output pulse of the delay circuit 18, a determination pulse P2 is generated from the determination circuit 25, and the determination pulse P2 causes the flip-flop 26U and 26D are reset. In this way, in the tuned state, both AFT signals EU and 8D are "0".
Therefore, both gate circuits 8U and 8D are turned off, and the voltage of the station counter 6 does not change. Unlike such a tuned state, if the local interrogation wave number is too high, a subtraction input of 7745 or more is applied to the comparison counter 19 via the AND gate 15, so that a borrow output P, is generated.

The borrow output sets flip-flop 26D and outputs AFT signal E. becomes “1”. This turns on the gate circuit 8D, and a subtraction input is applied to the station counter 6 via the gate circuit 8D. When the voltage code is decreased by the subtraction input, the tuning voltage is lowered, and the local oscillation frequency reaches a specified value, a discrimination pulse P2 is generated and the flip-flop 26D is reset. Furthermore, if the local oscillator frequency is too low, only a subtraction input of 7743 or less is applied to the comparison counter 19 via the AND gate 15, so at the time of determination, at least 1 of the comparison counter 9 is input.
The bit is "1". For this reason, a discrimination pulse P3 is generated from the discrimination circuit 25, the flip-flop 26U is set, and the AFT signal EU becomes "1". As a result, the gate circuit 8U is turned on, and an addition input is applied to the station counter 6, causing the tuning voltage to rise and the local oscillation frequency to rise. When the local oscillation frequency reaches a specified value, a discrimination pulse P2 is generated and the flip-flop 26U is reset. The above AFT operation maintains the tuned state of the tuner 12.

Figure 3 shows AFT signals EU and E for local frequency f.
The change in o is shown. For example, the top and bottom are each 6 [MH2
] There are 6 channels with intervals of 192, and there is a difference of 192 in the channel frequency code. ] (=3 skins [KHZ]) frequency change occurs. Therefore, as shown in Fig. 3, when the local frequency f is 242 [MH2] or less, the AFT signal EU is
1", and when this is 242.03125 [MHZ] or higher, the AFT signal Eo becomes "1", and the AFT signal Eo becomes "1" between the two.
Signals Eu and Eo both become "0". Furthermore, fine tuning can be performed by canceling the AFT operation. While the upward sweep switch 10U is on, the local frequency fl increases, and while the downward sweep switch 10D is on, the local frequency f decreases. In this case, it goes without saying that the AFT switch 13 is turned off. According to the present invention described above, since a variable resistor for generating a tuning voltage is not required, the presetting operation is easy and the DC stability is excellent.

Further, an expensive programmable variable frequency divider like the PLL system is not required. However, since the tuned state can be maintained even if the local oscillator control loop is cut off, it is easy to perform fine tuning.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram used to explain its operation, and FIG. 3 is a diagram used to explain the AFT signal. 1 is a channel designation switch, 3 is a station memory, 6 is a station counter, 7U, 7D, 8U, 8
D is a gate circuit, 10U and 10D are an up sweep switch and a down sweep switch, 11 is a DA converter, 12 is a tuner, 14 and 17 are frequency dividers, 16 is a reference oscillator, 19 is a comparison counter, and 20 is a channel frequency. memory, 25
is a discrimination circuit. Figure 3 Figure 1 Figure 2

Claims (1)

[Claims] 1 a tuner having a variable reactance element for tuning;
a reference oscillator that generates a signal of a predetermined frequency; a gate circuit that gates the local oscillator output of the tuner with the output of the reference oscillator; a memory device that selectively reads a channel frequency code corresponding to the received frequency; A comparison circuit that compares the channel frequency code and the output of the gate circuit, a discrimination circuit that discriminates the contents of the comparison circuit, and a voltage code that is changed by either the output of the discrimination circuit or the fine adjustment means. and a DA converter that converts a voltage code from the counter into a tuning voltage for a tuning variable reactance element of the tuner.