JPS6015171B2 - Adjustment method to minimize glitches in high-speed D/A - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides current sources 1, 12, and 12, each having a load corresponding to each bit of a digital signal, between the input terminals of a differential amplifier.
Switching circuits S, , S2, S3, . . . 13, .
A high-speed and high-precision digital-to-analog converter (hereinafter referred to as D/A
Minimize glitches in the analog output waveform when each switching circuit (hereinafter referred to as FET) is formed by a field effect transistor (hereinafter referred to as FET) that is controlled on/off by applying a drive voltage of a digital signal to the gate. This relates to how to adjust the

A conventional example of this type of D/A and its problems will be explained with reference to FIG.

In Fig. 1, 1, 2, 3, . . . are terminals 90.
, 91 are connected in parallel between the first, second, third, .
. . . are current circuits, 10 is a current source that causes a current of magnitude 1 to flow through the first current circuit 1, 20 is a current source that causes a current of magnitude 1/2 to flow through the second current circuit 2, and 30 is a current source that causes a current of 1/4 of the magnitude to flow through the third current circuit 3. Although not shown in the drawings, in general, up to a current moat that allows a current of magnitude 1/2n-1 to flow through the n-th current circuit is similarly provided. 11, 12, 21, 22, 31, 32,...
. . . are N-channel junction FETs, and a pair of them constitutes a switching circuit, and each is inserted in the middle of each current circuit.

That is, taking the first current circuit 1 as an example, FET II
The source terminals of FET II and 12 are connected in common and connected to one end of the current source 10, the drain terminal of FET II is connected to terminal 9, and the drain terminal of FET 12 is connected to terminal 9.
Connected to 1. Then, a drive voltage 13 of a digital signal is applied as the gate voltage of FET II,
A constant DC voltage V is applied as the gate voltage of the FET 12. In the above configuration, the FET 12 is controlled to be on (conducting) or off (non-conducting) depending on whether the drive voltage 13 of the digital signal is applied to the gate of the FET 11 or not. The current 1 may or may not flow.

That is, the current circuit 1 is switched by the drive voltage 13 of the digital signal. Similarly, the current circuits 2, 3, . . . are switched by the drive voltages 23, 33, . . . of the digital signals, respectively. n-bit D
/A, each current source is given a weight of 1 to 1/2n-1, and each current circuit is connected in parallel between terminals 90 and 91, so terminals 90 and 91 are connected to a summing amplifier. By adding the input currents flowing through each current circuit, a digital signal determined by a combination of drive signals input to each gate terminal is converted into an analog signal and can be taken out from the summing amplifier. However, in the conventional device described above, since the gate voltage applied to the FETs forming the switching circuit cannot be arbitrarily variably adjusted, variations in characteristics appear among the individual FETs, and waveforms at on/off times differ from FET to FET. There was a problem in that large glitches appeared in the analog signal obtained as an output.

An object of the present invention is to provide an adjustment method that can minimize the glitch in high-speed D/A.

A feature of the present invention is that each switching circuit of the load current addition type high-speed D/A is controlled by a first FETQ, which is controlled on/off by applying a digital drive voltage V, whose voltage value can be adjusted, to the gate. and a second FET Q2 which is applied with a gate voltage V2 whose voltage value can be adjusted and is turned off when the first FET is turned on and turned on when it is turned off, and these two gate voltages V, , V2 are The purpose of this method is to fix each gate voltage value V, V2 by variably adjusting each switching circuit to minimize glitches in the output analog voltage.

The present invention will be explained below with reference to the drawings.

FIG. 2 is a block diagram of a high-speed D/A to which the present invention is applied.

In FIG. 2, 1, 2, 3,...n-, . ■ are current circuits, 1,, Z, 13,...ln-,,
ln is the current source of each current circuit, S,, S2, S3,...
...Sn-,,Sn are switching circuits inserted in the middle of each current circuit, G,,G2,G3,...,Gn
-,, Gn is a drive signal that drives and controls each switching circuit on and off, AMP is a summing amplifier that adds the currents flowing in each current circuit, Rf is a feedback resistor of the summing amplifier,
EoM is the output signal. Current source 1 supplies current 1, current source 13 supplies current 1/2, current source 13 supplies current 1/4, current source ln-, supplies current 1/2n-2, current source ln is a current source that causes current 1/2n-1 to flow through each current circuit. That is, Fig. 2 shows an n-bit D/A with n switching circuits, and the current sources include 1, 1/2, 1/4, ..., 1/2, 2, 1/2, and It is given a weight of 1. Drive signal G, ~Gn
By turning on an arbitrary combination of switching circuits, the currents flowing through the current circuits can be added by the summing amplifier AMP and taken out as a voltage output Eout. FIG. 3 is a block diagram showing the switching circuit in FIG. 2 in detail.

The switching circuit is composed of two junction FETs Q and Q2. V, is the gate voltage of Q, and V2 is the gate voltage of Q2. When Q, is cut off and Q2 is turned on, the switching circuit is in the on state, and at this time, a current of magnitude 1 flows through the current circuit and the summing amplifier AMP
'This is entered. When Q, is turned on and Q2 is cut off, the switching circuit is turned off, and at this time there is no current input to the summing amplifier AMP. however,
A crab stream of size 1 is flowing through Q. The gate voltage y, determines the on-state level of the switching circuit,
Gate voltage V2 determines the off-state level. Complete on/off of the switching circuit depends on these two gate voltages V
,,Adjust with V2. In the case of high-speed D/A, the glitch is
It is a very difficult and harmful phenomenon to avoid.

There are two main possible causes of glitches: skew (time delay between switching waveforms) and differences in switching waveforms between on and off times. FIG. 4 schematically shows glitches caused by skew.

td indicates the time delay between the switching waveforms, and the shaded area indicates a glitch appearing in the current waveform flowing through the current circuit. FIG. 5 schematically shows glitches that occur due to differences between on and off switching waveforms.

torr is the time required for the current to become completely zero when turned off, t. n is the time required for the current to finish rising completely when turned on, and this torr and t. The difference in n causes glitches shown with diagonal lines. The present invention is directed to the third
The idea is to make the gate voltages V, , V2, shown in the figure variably adjustable, and fix each of the above gate voltages by adjusting these gate voltages appropriately to minimize the glitch that appears in the analog output waveform. It is.

FIG. 6 is a diagram showing an example of a change in switching waveform due to adjustment using a waveform close to the actual one. However, in reality, each individual switching circuit usually exhibits a more complex waveform due to its own skew and disturbance of on/off waveforms. However, for any switching circuit, by variably adjusting the two gate voltages V, , V2, it is possible to find the point that minimizes the glitch. FIG. 7 is a diagram showing the parasitic inter-electrode capacitance that causes spikes appearing in the switching waveform. This parasitic inter-electrode capacitance causes a spike as shown in FIG. 6F. This spike is the Q in Figure 3.
, it is possible to change its magnitude depending on the voltage y, which determines the drive voltage of . In other words, if the absolute value of voltage V is increased, the spike will also become larger, and V
If the absolute value of , is reduced by 4, the spike will also become smaller. Furthermore, the skew can also be changed by varying V and V2. Therefore, it is extremely easy to minimize glitches that appear in the output through spike correction and skew adjustment. As explained above, according to the present invention, harmful glitches caused by various causes can be eliminated by arbitrarily changing the skew and spike by adjusting the two gate voltages V, V2 for each switching circuit. It has the advantage of being able to be fixed at the minimum point.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional example, Fig. 2 is a block diagram of a converter to which the present invention is applied, Fig. 3 is a detailed diagram of its switching circuit, and Fig. 4 explains glitches caused by skew. FIG. 5 is a time chart illustrating glitches caused by differences in waveforms; FIG. 6 is a diagram showing changes in switching waveforms when using the method of the present invention;
FIG. 7 is a circuit diagram illustrating locations where parasitic capacitance occurs. Explanation of symbols, 1, 2,...■...Current circuit,
L~ln...Current line, S,~Sn...
Switching circuit, G, ~Gn...drive signal, AMP
...Summing amplifier, Q,,Q2... Field effect transistor, V. , V2... Gate voltage. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1 Current sources I_1, I_2, I with loads corresponding to each bit of the digital signal are connected between the input terminals of the differential amplifier.
Switching circuits S_1, S_2, S_3, whose opening and closing are controlled by digital signals of each bit, respectively.
A load current addition type high-speed D that is connected in parallel through ... to output an analog voltage corresponding to the input digital signal.
Each of the above-mentioned switching circuits of /A (digital-to-analog converter) has a first FET (field effect transistor) Q_1 which is controlled to be turned on and off by applying a digital drive voltage V_1 whose voltage value can be adjusted variable to its gate. , a second FET is applied with a gate voltage V_2 whose voltage value can be adjusted and is turned off when the first FET is turned on, and turned on when the first FET is turned off.
FETQ_2, and these two gate voltages V_1, V_2 are variably adjusted for each switching circuit, and each gate voltage value V_1, V_2 is fixed in order to minimize glitches in the output analog voltage. Features a high-speed D/A glitch minimization adjustment method.