JPS6015173B2 - parallel encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an encoding circuit that quantizes the difference between two analog signals and converts it into a digital signal.

For example, a level comparator that compares the levels between two input signals, i.e., a parallel analog-to-digital converter configured to sequentially compare levels by arranging many comparators in parallel, is used. , when quantizing and encoding the difference between two analog signals, the two analog signals are added in advance to, for example, a dynamic amplifier to form an analog signal corresponding to the difference between the two signals. Then, the analog difference signal was supplied to the above-mentioned parallel analog-to-digital converter, etc., where it was quantized and encoded.

However, in the conventional quantization of analog difference signals, since the difference between two analog signals to be compared is formed using a differential amplifier, the differential amplifier is affected by fluctuations in the DC operation level, that is, DC If there is a drift in the DC component, the DC component will immediately appear as an error in the output analog difference signal, so a digital signal that accurately corresponds to the difference between the two analog signals cannot be obtained, and the accuracy of encoding will be reduced. There was a drawback that it decreased significantly. Therefore, for example, Japanese Patent Application Laid-open No. 50-112844y or
As seen in Publication No. 1-107752, in a parallel analog-to-digital converter, a comparison input signal is supplied in parallel to a large number of comparators arranged in parallel, and each comparator is connected to a common level comparison range. In other words, by taking advantage of the fact that the comparison operation is performed in the common mode range, two analog signals, one of which is folded to the reference level signal, are directly supplied to the comparators in parallel. , an improved version has been developed in which the analog difference signal is quantized all at once.

However, although such conventional improved parallel converters are intended to directly supply two analog signals to multiple comparators in parallel, they actually form reference level signals. The signal is divided by the stray capacitance existing at each connection point of the resistance bleeder circuit and the bleeder resistance value that increases sequentially for each connection point, and is supplied to one end of the resistance bleeder circuit and superimposed on the reference level signal. The disadvantage is that the analog signal attenuates as the distance from the input point increases, and the signal level to be compared differs for each comparator, making it impossible to perform accurate analog-to-digital parallel conversion. Ta.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to obtain an analog difference signal between two analog signals by directly supplying them in parallel to a large number of comparators while maintaining accurate signal levels. It is an object of the present invention to provide a parallel encoding circuit that can accurately perform high-precision encoding by eliminating the influence of DC drift of circuit elements that are caused by separately forming circuit elements, and that has a significantly simplified circuit configuration.

That is, the parallel encoding circuit of the present invention includes a plurality of comparators, and for each of the comparators, one comparison input terminal is supplied with the first analog signal, and the other comparison input terminal is supplied with the first analog signal. By supplying the second analog signals in parallel via respective capacitors and also supplying a reference level signal corresponding to the encoding level in the comparator, the first analog signal is used as the comparison output of the plurality of comparators. The present invention is characterized in that a digital signal corresponding to the difference between the analog signal and the second analog signal is generated.

The present invention will be explained in detail below with reference to the drawings.

An example of the configuration of a parallel encoding circuit according to the present invention is shown in FIG.

In the configuration shown in the first diagram, an impedance conversion amplifier, abbreviated as an impedance converter, is used to supply analog signals A and B from respective input terminals to a large number of comparators 4, which will be described later, at low impedance. 1 and 2, respectively, and supply the low impedance output analog signal A from the converter 1 in parallel to one comparison input terminal of a large number of comparators 4 arranged in parallel. The other comparison input terminal of these comparators 4 is connected to a DC current of an appropriate magnitude from a constant current source 3 by connecting a large number of resistors R in series in correspondence with each comparator 4. A reference level signal voltage of a value corresponding to each quantized bell set sequentially to each comparator 4 is supplied to one end of the resistor network from the connection point of each resistor R, and the impedance described above is supplied to one end of the resistor network. The low impedance output analog signal B from the converter 2 is connected via a capacitor C to the connection point of each resistor R mentioned above, and is supplied to the other comparison input terminal mentioned above together with each reference level signal voltage mentioned above. supply. Note that since the terminal of the resistor network described above is grounded via the output impedance of the converter 2, which has a much smaller value than the resistance value of the resistor R, the reference level signal voltage supplied to each comparator 4 By appropriately setting the constant current value from the constant current source 3 and the resistance value of the resistor R, the value of can be made to correspond accurately and stably to a predetermined quantization level for each comparator. With the circuit configuration described above, each comparator 4 is supplied with the analog voltage of the difference between the two analog signals A and B together with the quantized signal reference level signal voltage assigned to each comparator 4. In this case, the level comparison between the analog difference signal and each reference level signal is directly performed, and encoding is performed with extremely high precision.

The comparison output of each comparator 4 that has performed such level comparison is sequentially determined by the number n of comparators 4 arranged in parallel.
These comparison outputs are led to the code converter 5, where they are converted into, for example, a commonly used binary code signal, and output as encoded outputs. In the parallel encoding circuit of the present invention configured as described above, when supplying the input analog signal B to each comparator 4 in a manner superimposed on the respective reference level signal voltage,
The input analog signal B is connected in parallel to each comparator 4 from the impedance converter 2 with a low output impedance through a resistor network and a capacitor C having a capacitance sufficiently larger than the stray capacitance of each comparator input circuit. As a result, changes in the potential of the input analog signal B are quickly and without distortion supplied to each comparator 4, and changes in the signal potential are directly supplied to each comparator 4. so that

Further, each reference level signal voltage supplied to each comparator 4 is formed by a series circuit network of resistors having a resistance value R by a high impedance constant current source 3, so that the reference level signal voltage supplied to each comparator 4 is Regardless of changes in the output terminal voltage of the impedance converter 2 on the side that supplies the reference voltage, a reference level signal voltage without DC drift can be obtained using a constant value of current and a constant value of resistance. There is. In addition, fluctuations in the DC level that may occur in the input analog signals A and B themselves due to DC component drift in the impedance converters 1 and 2, which are the supply sources of the analog signals A and B that are supplied in parallel to each comparator 4, are also considered. In order to further improve the accuracy of the encoding circuit of the present invention by eliminating the , if the DC level fluctuations caused in the respective output analog signals A and B due to the DC drift of the respective converters 1 and 2 are made equal and of the same polarity, at least the analog difference signal between these two signals will be Since these DC level fluctuations are canceled out, the influence of DC drift of the input analog signal source is also removed, making it possible to perform parallel encoding with extremely high precision.

Regarding the configuration of the encoding circuit of the present invention, one input analog signal is supplied to one comparison input terminal of each of a large number of comparators arranged in parallel, and the other input analog signal is supplied to the other comparison input terminal. The configuration of the circuit that supplies each signal is not limited to the example described above, as long as the voltage is supplied directly via the capacitor, and the respective reference level signals are also combined and supplied. Of course, this can be implemented with appropriate changes.

As is clear from the above description, according to the present invention, a difference signal between two analog signals can be accurately quantized and encoded using a circuit with an extremely simple configuration, and converted into a digital signal.

Therefore, in a series-parallel analog-to-digital converter that is configured by connecting analog-to-digital conversion stages in multiple stages, and converts an analog signal into a multi-value signal, quantizes it into a digital signal, and converts the analog signal into a digital signal, the original analog signal and the quantized It is very suitable to use the encoding circuit of the present invention in the second and subsequent analog-to-digital conversion stages that quantize the difference signal from the residual analog signal. In addition to being extremely simple, it is suitable for wide use in various types of digital processing that require quantizing the difference between two analog signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a parallel encoding circuit according to the present invention. 1, 2... Impedance converter, 3...
...Constant current source, 4...Comparator, 5...
...Code converter, C...Coupling capacitor, R...Voltage dividing resistor. Figure 1

Claims (1)

[Claims] 1 Equipped with multiple comparators, and for each of these comparators, one comparison input terminal has a first
analog signals are supplied in parallel, and a second analog signal is supplied in parallel to the other comparison input terminal via a capacitor, and a reference level signal corresponding to the encoding level in the comparator is also supplied. The parallel encoding circuit is characterized in that a digital signal corresponding to the difference between the first analog signal and the second analog signal is formed as a comparison output of the plurality of comparators.