JPS6015981B2 - Superimposed pulse discrimination control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for an electronic device or the like, and more specifically, the present invention relates to a control device for an electronic device, etc., and more specifically, a plurality of external input signal generating devices B. B2...is shared by BN, and when there is a case where the generation of input pulses of the input signal generator overlaps, the generation of the later input pulse is stopped until the earlier input pulse disappears, and the input pulse generation of the earlier input pulse is stopped. This invention relates to a superimposed pulse discrimination control device that makes it possible to generate a subsequent pulse only after the previous pulse disappears.

In the following explanation, there are two external input signal generators, B and &, which are commonly connected to the input bus line of device A, and are input by a wired-OR (red-oR) that functions as an OR circuit. The case will be described, and later the case where there are three or more will also be described.

Conventionally, as shown in FIG. 1, when external signal input signals B and B2 are input to one input bus line 1 of device A via inverters 2.3, B
, the generated input W2 from , W2, and the input W3 to the device A may have waveforms that are difficult to distinguish as shown in FIG.

That is, taking a normal device as an example, and assuming that device A operates by detecting the falling edge of a pulse, in this case, the counterfeit A detects two pulses as one.

SUMMARY OF THE INVENTION An object of the present invention is to provide a superimposed pulse discrimination control device that eliminates the above-mentioned drawbacks.

According to the present invention, in a bus common type system, a register is set and operated by a bus signal indicating a bus usage state and an AND signal of an input signal, and a discrimination circuit that resets the register when the input signal is cut off. A superimposed pulse discrimination input control system with a superimposed pulse discrimination input control method is obtained. As described above, the present invention comprises a register for sending external signals and a bus, and a return circuit for detecting the state of the bus and operating the register. The present invention will be described in detail below with reference to the drawings.

FIG. 3 shows the configuration of the present invention, and a case will now be described in which when there is no signal on input bus line 1 of device A, input signal W is input from device B.

Input bus line 1 of Gisatsu equipment A is at “H” level (hereinafter “
H”), so inverters 4 and 5 are missed and AND
One input 7 of the circuit 6 is at "H". When W, occurs, it is therefore passed through the AND circuit 6 to the register REI.
Since the set terminal 8 of the device A is set to "H", the input bus line of the device A is set to "L" through the inverter 10, and the REI is cleared.
Circuit 12 for creating the negation of AND via inverter 4
Since the input terminal 13 of the NAND circuit (hereinafter referred to as a NAND circuit) is set to "L", the clear terminal 11 of REI is set to "H".

Also, when W, is input, NAND is applied via the inverter 14.
Since the input terminal 15 of the circuit 12 is set to "L", the clear terminal 11 of REI remains "H" and does not affect the output 9. When W3 becomes “L”, inverters 4 and 5 and resistor 1
6. Set the REI setting state 8 to "L" via the delay circuit 18 of the capacitor 17 and the AND circuit.

The input of REI to the set terminal 8 is shown by waveform W4 in FIG. 4, but since REI operates at the rising edge of "L" → "H", it does not affect the output 9.

The time T during which W4 is at "H" is the time required for the signal to be transmitted through the REI inverters 10, 4.5, the AND circuit 6, and the delay circuit 18. Now, in this state, if the input W becomes "L" without waiting for the input of W2, the input terminal of the NAND circuit 12 becomes "H" via the inverter 14, so the clear terminal 11 of REI becomes "L". Since the output 9 is cleared to "L", W3 returns to ``H''1. At this time, W8 is connected to NAND via inverter 4.
Since the input terminal 13 of the circuit 12 is set to "L", the waveform W5 at the clear terminal 11 of REI becomes "H". When the waveform W5 is “L”, the borrowed goods 2 is connected to the REI inverter 10.
．． 4. This is the time during which a signal is transmitted through the NAND circuit 12.
The relationship between W, , W3, W4, and W5 is shown in FIG.

The same applies when only W2 is input. On the other hand, W
2 has already been input, W. We will discuss the case of superimposed pulse generation where . In this case, the third
Since one input 7 of the AND circuit 6 in the figure is at "L", W, is not input to REI.

When W2 disappears, the input terminal 1 of the device A becomes "H" and one input 7 of the AND circuit 6 becomes "H", so that the same operation as described above is started.

Here, after W2 disappears, the input 7 of the AND circuit 6 is set to “H”.
The time T3 until W3 can be inputted is the time required for W3 to become "H" and for the signal to be transmitted through the inverters 4, 5 and the delay circuit 18.

W,,W2,W3,W4. The relationship of W5 is also shown in FIG.

Delay at state reversal such as T, , T2, T3
y) is usually a very small value, and the delay circuit 18
As explained above, in the example where there are two external input devices B, , & and each has input pulses W, W2, the time constants of the delay circuits are the same. That's fine.

Next, a case will be described in which there are three or more external input devices B...BN.

At this time, by changing the time constant of the delay circuit 18 of this device attached to each input line, the shared bus signal W
Since the time period m3 until external input becomes possible after disappearance of B.3 is different, external input baggage counterfeit B. . . . It becomes possible to assign a position order to the BN, and it becomes possible to discriminate between superimposed pulses as in the case of two BNs.

As described above, according to the present invention, it is possible to automatically discriminate and input superimposed pulses by a simple TTL combination, and various applications can be considered in a bus-sharing system, and it is extremely effective in practical use.

[Brief explanation of drawings]

Fig. 1 is a diagram of an external signal input circuit wired-OR (Mred-oR) to input bus line 1 of device A, Fig. 2 is a waveform diagram of each part of Fig. 1, and Fig. 3 is a configuration of the present invention. REI is a set/reset type resist, and 18 is a delay circuit for creating a delay. FIG. 4 shows operation waveforms of each part when a single bus or multiple buses are input from the outside to the circuit of the present invention. O figure O 2 figure *J phantom juice★ figure

Claims (1)

[Claims] 1 a delay circuit that delays a signal on a bus; a first gate to which an input signal and the output of the delay circuit are supplied; a second gate to which an input signal and a signal on the bus are supplied; 1. A superimposed pulse discrimination control device comprising: a register having a gate output supplied to a set terminal, a register having a second gate output supplied to a reset terminal, and supplying an output signal onto the bus.