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JPS6016748B2 - Manufacturing method of semiconductor device - Google Patents
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JPS6016748B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPS6016748B2
JPS6016748B2 JP11251179A JP11251179A JPS6016748B2 JP S6016748 B2 JPS6016748 B2 JP S6016748B2 JP 11251179 A JP11251179 A JP 11251179A JP 11251179 A JP11251179 A JP 11251179A JP S6016748 B2 JPS6016748 B2 JP S6016748B2
Authority
JP
Japan
Prior art keywords
metal layer
insulating material
aluminum
film
electrically insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11251179A
Other languages
Japanese (ja)
Other versions
JPS5530899A (en
Inventor
秀男 常光
宏 柴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11251179A priority Critical patent/JPS6016748B2/en
Publication of JPS5530899A publication Critical patent/JPS5530899A/en
Publication of JPS6016748B2 publication Critical patent/JPS6016748B2/en
Expired legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置半導体装置の菱造方法にかかり、
とくに好ましくは浅い接合を有する半導体装置の電極配
線の装造方法に関するものである。
[Detailed Description of the Invention] The present invention relates to a Ryozo method for a semiconductor device,
Particularly preferably, the present invention relates to a method of fabricating electrode wiring of a semiconductor device having a shallow junction.

従釆、半導体装置の電極材洋としては一般にアルミニウ
ムが使用されてきたが、アルミニウムは半導体材料と比
較的低い温度で合金反央をおこすため、超高周波増中用
トランジスタや超高速度スイッチ用トランジスタなどの
極度に浅い接合を有する半導体装置の場合には容易に反
応領域が接合部に到達して接合を破壊するという欠点が
あつた。
Aluminum has generally been used as the electrode material for semiconductor devices, but since aluminum undergoes alloy decomposition with semiconductor materials at relatively low temperatures, it is often used in ultra-high frequency boosting transistors and ultra-high speed switch transistors. In the case of a semiconductor device having an extremely shallow junction such as the above, there is a drawback that the reaction region easily reaches the junction and destroys the junction.

このため従来のアルミニウム電極を用いた半導体装置は
熱的に箸るしく不安定であった。この発明の目的は信頼
度の高い半導体装置を容易に得ることのできる新規なる
装造方法を提供することにある。すなわちこの発明の特
徴は、所定表面上にシリコン酸化膜を有する半導体基板
上に第1の金属層を形成し、該第1の金属層上に第2の
金属層を形成し、該第2の金属層上に第3の金属層を形
成した積層金属層体を選択的に電気絶縁物質に変換する
に際し、前記第2の金属層と前記第3の金属層とは異な
る上記変換特性を有し、これによりまず前記第3の金属
層を選択的に電気絶縁物質に変換し、しかる後に該第3
の金属層の電気絶縁物質に変換されない部分をマスクと
して該第3の金属層を選択的に電気絶縁物質に変換した
とは異なる条件で前記第2および第1の金属層の所定部
を順次選択的に電気絶縁部質に変換する半導体装置の袋
造方法である。このように積層金属体を選択的に電気的
絶縁物質に変換する工程を二度に分けて行うから、機方
向の形状が所定の値とすることができる。すなわちまず
第3の金属層を横方向への絶縁物質の藤がりも含めて所
定形状に選択酸化する。このときに第2の金属層はスト
ッパーの役割を行う。そして次に第2,第1の金属層の
選択酸化のできる条件でこれら金属層の変換を行うから
結局、全体の積層金属体は所定形状に形成される。しか
も積層金属体の全体を同じ条件で連続的に選択酸化を行
う場合、長い時間を必要としこのために第3の金属層上
の同一のマスクのみではそのマスクの劣化等も考えられ
、かつ断面形状が厚さ方向において異ることも考えられ
る。この点本発明では第3の金属層の残余せる部分もマ
スクとして作用するから第2,第1の金属層の選択酸化
は確実に行なわれる。又、2回に分けて選択酸化を行う
ことは厚さ方向の断面形状の制御、修正がその条件をコ
ントロールすることによって可能であることはいうまで
もない。この発明によれば、好ましくは半導体と良好な
オ−ム接触を保つために設けられた極めて薄いアルミニ
ウム薄膜層(以下同機)とこの上に接着したタンタル、
タングステンあるいはモリブデンからなる遮蔽膜層とさ
らにこの上に接着したアルミニウムからなる導電膜層と
から構成される電極が装造される。
For this reason, conventional semiconductor devices using aluminum electrodes have been extremely unstable thermally. An object of the present invention is to provide a new fabrication method that allows a highly reliable semiconductor device to be easily obtained. That is, a feature of the present invention is that a first metal layer is formed on a semiconductor substrate having a silicon oxide film on a predetermined surface, a second metal layer is formed on the first metal layer, and a second metal layer is formed on the first metal layer. When selectively converting a laminated metal layer body in which a third metal layer is formed on a metal layer into an electrically insulating material, the second metal layer and the third metal layer have different conversion characteristics. , thereby first selectively converting the third metal layer into an electrically insulating material, and then converting the third metal layer into an electrically insulating material.
Sequentially selecting predetermined portions of the second and first metal layers under different conditions from selectively converting the third metal layer into an electrical insulating material using the portion of the metal layer that is not converted into an electrically insulating material as a mask. This is a bag manufacturing method for semiconductor devices that converts it into an electrically insulating material. Since the step of selectively converting the laminated metal body into an electrically insulating material is performed in two steps, the shape in the machine direction can be made to a predetermined value. That is, first, the third metal layer is selectively oxidized into a predetermined shape including the lateral waviness of the insulating material. At this time, the second metal layer serves as a stopper. Then, since the second and first metal layers are converted under conditions that allow selective oxidation of these metal layers, the entire laminated metal body is eventually formed into a predetermined shape. Moreover, when selectively oxidizing the entire laminated metal body under the same conditions continuously, it takes a long time, and for this reason, if the same mask is used only on the third metal layer, the mask may deteriorate, and the cross-sectional It is also conceivable that the shape differs in the thickness direction. In this respect, in the present invention, the remaining portion of the third metal layer also acts as a mask, so that the selective oxidation of the second and first metal layers is reliably performed. Furthermore, it goes without saying that selective oxidation can be performed in two steps to control and modify the cross-sectional shape in the thickness direction by controlling the conditions. According to the invention, an extremely thin aluminum thin film layer (hereinafter referred to as the same) preferably provided to maintain good ohmic contact with the semiconductor, tantalum bonded thereon,
An electrode is constructed of a shielding film layer made of tungsten or molybdenum and a conductive film layer made of aluminum bonded thereon.

このような電極構造において、電極と半導体とのオーム
接触は半導体基板を適当な温度に加熱して得られる。こ
の際に、シリコンとアルミニウムの合金温度は575o
○であり、一方タンタル、タングステン、あるいはモリ
ブデンとの合金温度は各々2400qo、2150つ○
、187000とアルミニウムに比べて極めて高温度で
あるから、シリコン基板の加熱温度をアルミニウムの合
金温度附近に選ぶことによりアルミニウム薄膜層のみを
シリコンと反応させて金属シリサィドを形成し良好なオ
ーム接触を得ることができる。形成される金属シリサイ
ド層の深さは加熱温度とアルミニウム膜の厚さによって
決まるから、あらかじめ接合の深さに対応してアルミニ
ウム膜の厚さを制御しておけば長時間の熱処理を施して
も接合の破壊をさげることができる。たとえば、シリコ
ン基板を400q0〜50ぴ0に加熱してアルミニウム
薄膜とのオーミツク・コンタクトをとる場合、シリコン
基板中の最も浅い接合の深さが0.2〜0.8ミクロン
であれば、アルミニウム薄膜層の厚さは接合深に応じて
0.01〜0.05ミクロン以下とすれば、オーミック
・コンタクト用の熱処理およびその後の熱処理(一般に
50000を越えることはない)によて接合が破壊する
のを防止できる。
In such an electrode structure, ohmic contact between the electrode and the semiconductor is obtained by heating the semiconductor substrate to an appropriate temperature. At this time, the alloy temperature of silicon and aluminum is 575o
○, while the alloying temperature with tantalum, tungsten, or molybdenum is 2400 qo and 2150 qo, respectively.
, 187,000, which is extremely high temperature compared to aluminum, so by selecting the heating temperature of the silicon substrate near the alloy temperature of aluminum, only the aluminum thin film layer reacts with silicon to form metal silicide and obtain good ohmic contact. be able to. The depth of the metal silicide layer that is formed is determined by the heating temperature and the thickness of the aluminum film, so if you control the thickness of the aluminum film in advance according to the depth of the bond, it will work even after long heat treatment. Breakage of the joint can be reduced. For example, when making ohmic contact with an aluminum thin film by heating a silicon substrate to 400q0 to 50p0, if the depth of the shallowest junction in the silicon substrate is 0.2 to 0.8 microns, the aluminum thin film The layer thickness should be less than 0.01-0.05 microns, depending on the bond depth, so that the ohmic contact heat treatment and subsequent heat treatments (generally not exceeding 50,000 µm) will destroy the bond. can be prevented.

アルミニウム薄膜上のタワタル・タングステンまたはモ
リブデンの層はその上のアルミニウム導電層に対するバ
リアとして有効な厚さを有すればよい。下に述べる選択
酸化法を用いる場合は菱造上の便宜からたとえば0.1
ミクロン前後が好都合である。このように本発明の電極
構造を用いれば極めて浅い度合を有する半導体装置の場
合にも優れた熱日年安定性が得られる。更に本発明によ
れば、電極部の形成にあたっては従来のような選択エッ
チング法によらず、操択酸化法を用いるため、電極形成
と同時に半導体表面が電気的、化学的に安全な金属酸化
被膜で完全に覆われる。
The tungsten or molybdenum layer on the thin aluminum film need only have a thickness that is effective as a barrier to the overlying aluminum conductive layer. When using the selective oxidation method described below, for example, 0.1
Around micron is convenient. As described above, by using the electrode structure of the present invention, excellent thermal/annual stability can be obtained even in the case of a semiconductor device having an extremely shallow degree. Furthermore, according to the present invention, since the selective oxidation method is used to form the electrode portions instead of the conventional selective etching method, the semiconductor surface is coated with an electrically and chemically safe metal oxide film at the same time as the electrodes are formed. completely covered with.

このため半導体内部に形成されている接合は外部からの
汚れに対して保護され高い信頼度を得ることができる。
次に本発明をよりよく理解するために本発明について図
を用いて説明する。
Therefore, the junction formed inside the semiconductor is protected from contamination from the outside, and high reliability can be obtained.
Next, in order to better understand the present invention, the present invention will be explained using figures.

各図の共通する部分については同一参照番号を付して示
してある。第1図a乃至gを参照するとこの発明の好ま
しい実施例の装造方法は、次に示すような選択陽極酸化
法を用いて行われる。始めに所定のPN接合を有し、か
つ電極取出しのための開孔部を除いて他のすべての表面
部分がシリコン酸化膜2で覆われた半導体基板1〔第1
図a〕の表面に均一に厚さ0.01ミクロンのアルミニ
ウム薄膜3を蒸着し、しかるのち引き続いて厚さ0.1
ミクロンのタンタル薄膜4および厚さ1.5ミクロンの
アルミニウム膜5を蒸着する〔第1図b〕。次にアルミ
ニウム膜5の表面全体に第1の化成処理を施して厚さ約
0.1ミクロンの多孔性アルミナ膜6を形成する〔第1
図c〕。この多孔性アルミナ膜6は次の第2の化成処理
工程においてホトレジストの接着性を増す効果がある。
多孔性アルミナ膜6の形成には10%のクロム酸水溶液
を用い、化成電圧10Vで10分間定電圧化成するのが
適当である。次に多孔性アルミナ膜6の表剖にホトレジ
ストを施し、電極配線となる部分以外の部分をホトレジ
スト12で覆い、ホトレジストをマスクとして第2の化
成処理を施し、多孔性アルミナ膜6のホトレジストが付
着していない部分に無孔性アルミナ膜7を形成する〔第
1図d〕。この第2の化成処理はエチレングリコールに
側酸アンモンを飽和させた化成液を用い化成電圧80V
で15分間定電圧化成するのが適当である。ついで、ホ
トレジストを除去したのち、前記無孔性アルミナ膜7を
マスクとして第3の化成処理を施し、無孔性アルミナ膜
7で覆われた部分以外、すなわち多孔性アルミナ膜だけ
で覆われた部分のアルミニウム層5をその厚さ全体にわ
たって多孔性ァルミナ8に変換する〔第1図e〕。第3
の化成処理は10%の希硫酸を用い、化成電圧10Vを
印加して定電圧化成を行なうのが好適である。この実施
例では約15分間の化成処理で無孔性アルミナ膜7によ
ってマスクされた部分以外のアルミニウム層の部分が多
孔性ァルミナに変換される。また、この第3の化成処理
ではタルタン薄膜4はほとんど化成されない。これは、
タルタン酸化物は無孔性のものしかできず、多孔性の酸
化物をつくる化成液では無孔性酸化物は形成されないと
思われる。次にタルタン薄膜4を陽極酸化するために第
4の化成処理を施す。この際には前記の無孔性アルミナ
膜7に覆われて残存しているアルミニウム腰部分がマス
クとなり「これに覆われていない部分のタンタル薄膜部
分及びアルミニウム薄膜部分が陽極酸化されてタンタル
酸化物9及びアルミナ10‘こ変換される。〔第1図f
〕。第4の化成処理はクエン酸アンモニウムの3%水溶
液を化成液として用い、この実施例では化成電圧20肌
で15分間定電圧化成するのが適当である。次に半導体
基板に450℃にて1時間の熱処理を施す。この熱処理
によって電極部分と半導体との間に良好なオーム接触が
形成されると同時に陽極酸化によって形成されたアルミ
ナ及びタンタル酸化物が化学的に安定化される。最後に
外部リードまたは上層の配線層を取付けるための関孔部
11を電極配線を覆うアルミナ膜7の所望の部分に設け
て、電極配線の形成を完了する〔第1図g〕。この実施
例に示した製造方法で形成される半導体装置では、シリ
コン半導体と合金反応を起すアルミニウムの量が極めて
正確にかつ少量におさえられるため熱処理に対する安定
性が極めて高い。
Common parts in each figure are designated by the same reference numerals. Referring to FIGS. 1a-g, the preferred embodiment of the present invention is fabricated using a selective anodization process as described below. First, a semiconductor substrate 1 [the first
A thin aluminum film 3 with a thickness of 0.01 micron is uniformly deposited on the surface of Figure a], and then subsequently with a thickness of 0.1 micron.
A micron tantalum thin film 4 and a 1.5 micron thick aluminum film 5 are deposited [FIG. 1b]. Next, a first chemical conversion treatment is performed on the entire surface of the aluminum film 5 to form a porous alumina film 6 with a thickness of about 0.1 micron.
Figure c]. This porous alumina film 6 has the effect of increasing the adhesion of the photoresist in the next second chemical conversion treatment step.
To form the porous alumina film 6, it is appropriate to use a 10% aqueous chromic acid solution and perform constant voltage anodization at a forming voltage of 10 V for 10 minutes. Next, photoresist is applied to the surface of the porous alumina film 6, parts other than those that will become electrode wiring are covered with photoresist 12, and a second chemical conversion treatment is performed using the photoresist as a mask, so that the photoresist of the porous alumina film 6 adheres. A non-porous alumina film 7 is formed on the remaining portions (FIG. 1d). This second chemical conversion treatment uses a chemical solution in which ethylene glycol is saturated with ammonium lateral acid, and the chemical conversion voltage is 80V.
It is appropriate to carry out constant voltage conversion for 15 minutes. Next, after removing the photoresist, a third chemical conversion treatment is performed using the non-porous alumina film 7 as a mask to remove the parts other than the parts covered with the non-porous alumina film 7, that is, the parts covered only with the porous alumina film. The aluminum layer 5 is converted into a porous alumina 8 over its entire thickness (FIG. 1e). Third
For the chemical conversion treatment, it is preferable to use 10% dilute sulfuric acid and apply a chemical conversion voltage of 10 V to perform constant voltage chemical conversion. In this embodiment, the portions of the aluminum layer other than the portions masked by the nonporous alumina film 7 are converted into porous alumina by a chemical conversion treatment lasting about 15 minutes. Further, in this third chemical conversion treatment, the tartan thin film 4 is hardly chemically converted. this is,
Tartan oxide can only be made in a nonporous form, and it is thought that a chemical conversion solution that forms a porous oxide will not form a nonporous oxide. Next, a fourth chemical conversion treatment is performed to anodize the tartan thin film 4. At this time, the remaining aluminum waist portion covered with the non-porous alumina film 7 acts as a mask. 9 and alumina 10' are converted. [Figure 1 f
]. In the fourth chemical conversion treatment, a 3% aqueous solution of ammonium citrate is used as the chemical conversion liquid, and in this example, it is appropriate to perform constant voltage conversion at a conversion voltage of 20 for 15 minutes. Next, the semiconductor substrate is subjected to heat treatment at 450° C. for 1 hour. This heat treatment forms a good ohmic contact between the electrode portion and the semiconductor and at the same time chemically stabilizes the alumina and tantalum oxides formed by the anodization. Finally, a barrier portion 11 for attaching an external lead or an upper wiring layer is provided at a desired portion of the alumina film 7 covering the electrode wiring, thereby completing the formation of the electrode wiring (FIG. 1g). The semiconductor device formed by the manufacturing method shown in this embodiment has extremely high stability against heat treatment because the amount of aluminum that causes an alloy reaction with the silicon semiconductor is kept very precisely and to a small amount.

接合の深さが0.3ミクロンのウオッシュドェミッタ構
造を有するシリコン半導体素子に従来のアルミニウム電
極を適用すると300こ○の熱処理では約30分間で、
40ぴ○では約5分間でェミッタ接合短絡を引きおこす
が、本発明の実施例では40000で2畑時間、500
00で5時間の熱処理をおこなったが何らの損傷も認め
られなかった。上に、この発明について説明したが、こ
の発明の主たる部分は、半導体と良好なオーム接触を形
成する金属の制御された膜厚の薄膜層と、この上に被着
された半導体との反応温度が箸るしく高い金属の薄膜層
と「更にこの上に被着された良好な電気伝導性を有する
金属の膜層を積み重ねたのち陽極酸化法を適用して電極
配線に加工する工程にあり、この発明の大きな効果は熱
的に極めて安定な電極を持ち、かつ半導体表面が電気的
化学的に安定な金属酸化被覆で完全に保護された半導体
装置を容易かつ確実に得ることができることにある。
When a conventional aluminum electrode is applied to a silicon semiconductor device having a washed emitter structure with a junction depth of 0.3 microns, a heat treatment of 300 mm will take about 30 minutes.
At 40 pm, an emitter junction short circuit occurs in about 5 minutes, but in the embodiment of the present invention, it takes 2 hours at 40,000 pm, and 500 pm at 40,000 pm.
00 for 5 hours, but no damage was observed. As described above, the main part of the invention is to control the reaction temperature between a thin film layer of controlled thickness of a metal that forms a good ohmic contact with a semiconductor and a semiconductor deposited thereon. The process consists of stacking a thin metal film layer with an extremely high electrical conductivity and a metal film layer with good electrical conductivity, and then processing it into electrode wiring by applying an anodic oxidation method. The great effect of this invention is that it is possible to easily and reliably obtain a semiconductor device which has a thermally extremely stable electrode and whose semiconductor surface is completely protected by an electrochemically stable metal oxide coating.

従ってこの発明の技術的範囲は上記実施例に限定される
ものではなく、この発明の権利は特許請求の範囲に示す
全ての装置に及ぶ。
Therefore, the technical scope of this invention is not limited to the above embodiments, and the rights of this invention extend to all devices shown in the claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜gは本発明による一実施例による装造方法の
各工程における半導体素子断面図である。 図中1はシリコン基体、2はシリコン酸化膜、3,5は
アルミニウム膜、4はタンタル膜、6,7,8,10は
アルミナ、9はタンタル酸化物である。 髪′図
1A to 1G are cross-sectional views of a semiconductor device at each step of a manufacturing method according to an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 and 5 are aluminum films, 4 is a tantalum film, 6, 7, 8, and 10 are alumina, and 9 is tantalum oxide. hair figure

Claims (1)

【特許請求の範囲】[Claims] 1 所定表面上にシリコン酸化膜を有する半導体基板上
に第1の金属層を形成し、該第1の金属層上に第2の金
属層を形成し、該第2の金属層上に第3の金属層を形成
した積層金属層体を選択的に電気絶縁物質に変換するに
際し、前記第2の金属層と前記第3の金属層とは異なる
上記変換特性を有し、これによりまず前記第3の金属層
を選択的に電気絶縁物質に変換し、しかる後に該第3の
金属層の電気絶縁物質に変換されない部分をマスクとし
て該第3の金属層を選択的に電気絶縁物質に変換したと
きとは異なる条件で前記第2および第1の金属層の所定
部を順次選択的に電気絶縁物質に変換することを特徴と
する半導体装置の装造方法。
1. A first metal layer is formed on a semiconductor substrate having a silicon oxide film on a predetermined surface, a second metal layer is formed on the first metal layer, and a third metal layer is formed on the second metal layer. When selectively converting a laminated metal layer body in which a metal layer is formed into an electrically insulating material, the second metal layer and the third metal layer have different conversion characteristics. The third metal layer was selectively converted into an electrically insulating material, and then the third metal layer was selectively converted into an electrically insulating material using a portion of the third metallic layer that was not converted into an electrically insulating material as a mask. 1. A method for manufacturing a semiconductor device, comprising sequentially and selectively converting predetermined portions of the second and first metal layers into an electrically insulating material under different conditions.
JP11251179A 1979-09-03 1979-09-03 Manufacturing method of semiconductor device Expired JPS6016748B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11251179A JPS6016748B2 (en) 1979-09-03 1979-09-03 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11251179A JPS6016748B2 (en) 1979-09-03 1979-09-03 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9140571A Division JPS557020B2 (en) 1971-11-15 1971-11-15

Publications (2)

Publication Number Publication Date
JPS5530899A JPS5530899A (en) 1980-03-04
JPS6016748B2 true JPS6016748B2 (en) 1985-04-27

Family

ID=14588472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11251179A Expired JPS6016748B2 (en) 1979-09-03 1979-09-03 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6016748B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158965U (en) * 1987-04-03 1988-10-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158965U (en) * 1987-04-03 1988-10-18

Also Published As

Publication number Publication date
JPS5530899A (en) 1980-03-04

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