JPS6017140B2 - Execution order control method for microprograms in data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling the execution order of microprograms in a data processing device, particularly in a data processing device in which a data transfer operation between a main storage device and an input/output device is controlled by a microprogram. It is related to the control method.

Conventionally, in this type of data processing device, in order to control the execution order of microprograms, a test pattern for controlling the execution order of microprograms and various status information of the controlled circuit are input to the microprogram. A control method has been developed in which calculation is performed using a control-dedicated calculation circuit and the calculation is performed based on the calculation result. However, it is not economically desirable to provide a special arithmetic circuit solely for controlling the execution order of microprograms. In order to improve the inconvenience of such a follow-up, this invention requires a dedicated arithmetic circuit by sharing an arithmetic circuit used for general data manipulation as an arithmetic circuit that controls the execution order of microprograms. The aim is to obtain an economical method for controlling the execution order of microprograms without having to use a microphone to transfer data between the main memory and the input/output device.

In a data processing device controlled by a program,
The microprogram word has a test pattern for controlling the execution order of the microprogram and a control field for controlling various operations, and the test pattern Z pattern of the microprogram word is provided for the arithmetic bus used for general data manipulation. This information is connected to state information indicating various states of the controlled circuit, and both of these pieces of information are subjected to, for example, an AND operation in a general arithmetic circuit under the control of the microprogram word, and the result of the operation is stored at an address in the control memory. This is a microprogram execution order control method characterized by controlling the execution order of microprograms by embedding them. Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 FIG. 1 shows the arrangement of a data processing device to which the present invention is applied, and in this FIG. 2 is a central controller that executes general instructions including instructions to control the processing device; 3 is a data transfer device that transfers data between the input/output device and the main memory; Processing units 4, 5 and 6 are input/output devices. (b) The data processing device 3 performs the data transfer operation under the control of a microprogram,
FIG. 2 shows the structure of the microprogram word.

In FIG. 2, P is parity, TP is test pattern, RQ is memory requirement condition, TST is test condition, and DC
is the data specification that specifies the execution order of the microprogram, AD is the content of the operation bus R, and the modification and AL of the address of the microprogram specified by DC.
This is an address update condition that specifies the logical operation type for U.As is clear from this figure, the microprogram word structure includes a test pattern, and the circuit state is checked based on this test pattern. Mike depending on the result. The program execution order is determined.
Further, the data processing device 3 includes, as hardware,
A data structure of the channel control section shown in FIG. 3 and a control memory for storing microprogram words and its peripheral circuitry shown in FIG. 4 are provided. That is, in FIG. 3, 1
0 is a flip-flop group indicating various states, 11
12 is a general arithmetic circuit that operates on general arithmetic buses A and B and outputs the result to R, 13 is a latch register, and 14 is a register that stores the contents of this latch register 13. An increment/decrement circuit adds or subtracts 1, 15 is a local memory, and 16 is a buffer register. In addition,
In this embodiment, the test pattern shown in FIG. 2 is set, but the test pattern information may be set from a storage device other than the microprogram. Further, in FIG. 4, an address generator 21 determines the address of the microprogram from the contents of the microprogram service request and the microinstruction register, 21 is an address register that holds the address, and 22 is the address update condition. A selector selects the contents of the address register based on the control or fills the contents of the operation bus R into the lower 8 bits of the contents of the address register, for example, a control memory 23 stores a microprogram word, and 24 this selector. This is a microinstruction register that holds microinstructions read from control memory. However, in each of the above configurations, when attempting to control the execution order of microprograms based on the state of the controlled circuit, address update conditions are specified using microprogram instructions, and test pattern information for the circuit state to be tested is generated. Then, this pattern and the contents of the flip-flop group holding circuit state information are supplied to the general arithmetic circuit 12 via the general arithmetic bus, and a logical operation, for example, an AND operation, is performed on the two.

Then, the logical operation result is sent to the selector 22 via the operation bus R.
Then, in the selector, the contents of the operation bus R are changed to the contents of the address register according to the address update condition, e.g.
This is written into a bit and used as the address of the control memory 23. Therefore, as explained above, according to the present invention, the arithmetic bus and general arithmetic circuit used for general data manipulation are used to control the execution order of the microprogram, and the test pattern of the microprogram word is By taking the following conditions: and the circuit state of the controlled circuit, it is possible to control the execution order of microprograms extremely economically without requiring a dedicated arithmetic circuit as in the prior art.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the arrangement of a data processing device to which an embodiment of the control method according to the present invention is applied, FIG. 2 is an explanatory diagram showing the microprogram language structure for controlling the data processing device, and FIG. 4 are block diagrams showing the data structure, control memory, and peripheral circuits of the channel control section of the data processing apparatus. 1... Main storage device, 2... Central control unit, 3... Data processing device, 4-6... Input/output device, 10... Flip flop Group, 11...
...Test pattern holding register, 12... General arithmetic circuit, 13... Latch register, 14... Increment/decrement circuit, 15... Local memory,
16...Buffer register, 20...Address generator, 21...Address register, 22...Select register,
23...Control memory, 24...Microintrusion register. 1st year, 2nd year, 3rd year, 4th term

Claims (1)

[Claims] 1. In a data processing device that uses microprograms to control data transfer operations between the main memory and input/output devices, the microprogram words include test patterns for controlling the execution order of the microprograms and control fields for controlling various operations. It specifies address update conditions using microprogram instructions, generates test pattern information for circuit states that are not to be tested, and supplies this test pattern information and circuit state information to the general arithmetic circuit via the general arithmetic bus. , a microprogram execution order control system characterized in that the general arithmetic circuit performs a logical operation to determine whether the two pieces of information match, and creates an execution address for the next microprogram based on the result.