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JPS60175476A - Manufacture of integrated semiconductor device - Google Patents
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JPS60175476A - Manufacture of integrated semiconductor device - Google Patents

Manufacture of integrated semiconductor device

Info

Publication number
JPS60175476A
JPS60175476A JP59030182A JP3018284A JPS60175476A JP S60175476 A JPS60175476 A JP S60175476A JP 59030182 A JP59030182 A JP 59030182A JP 3018284 A JP3018284 A JP 3018284A JP S60175476 A JPS60175476 A JP S60175476A
Authority
JP
Japan
Prior art keywords
semiconductor
heat sink
semiconductor device
elements
sink body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59030182A
Other languages
Japanese (ja)
Inventor
Hideto Furuyama
英人 古山
Yoichi Unno
海野 陽一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59030182A priority Critical patent/JPS60175476A/en
Publication of JPS60175476A publication Critical patent/JPS60175476A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0233Mounting configuration of laser chips
    • H01S5/0234Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0233Mounting configuration of laser chips
    • H01S5/02345Wire-bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0235Method for mounting laser chips
    • H01S5/02355Fixing laser chips on mounts
    • H01S5/0237Fixing laser chips on mounts by soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/40Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/4025Array arrangements, e.g. constituted by discrete laser diodes or laser bar

Landscapes

  • Led Device Packages (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To enhance the arraying accuracy and improve the heat sink of a semiconductor element by bonding a plurality of metal pieces through insulating pieces in a sandwich shape, and then mounting fixedly the element through a solder material. CONSTITUTION:A heat sink body 1 and an insulator 2 are selected to have an equal arraying interval of semiconductor elements in the total of the thicknesses and the solder material. The body 1 and the insulator 2 are bonded with hard brazing material. Then, the solder material is selectively deposited and plated on the body 1. Then, an electric isolation is formed between the elements to form a semiconductor array, which is mounted fixedly on the position of the heat sink body. Thus, the element array is mounted up-side-down. The elements are electrically connected through each of the heat sink body.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は一次元配列を有する集積化半導体装置に恍り、
特に各素子の放熱を改善した集積化半導体装置の製造方
法に関する。
[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an integrated semiconductor device having a one-dimensional array,
In particular, the present invention relates to a method of manufacturing an integrated semiconductor device that improves heat dissipation of each element.

〔従来技術とその問題点〕[Prior art and its problems]

半導体素子を規則的配列をもって集積した集積化半導体
装置は、各種半導体素子を用いた応用が可能である。特
に光半導体素子を一次元配列によつ°〔集積したL E
 I)アレイ、半導体レーザーアレイ、クニアイメージ
センサ等は光情報処理用光源。
An integrated semiconductor device in which semiconductor elements are integrated in a regular arrangement can be applied using various semiconductor elements. Especially when optical semiconductor elements are arranged in a one-dimensional array [integrated L E
I) Arrays, semiconductor laser arrays, Kunia image sensors, etc. are light sources for optical information processing.

センサとして重要でちる。これらの集積化半導体装置の
中でも電流注入により動作する半導体素子を用いたもの
は、個々の半導体素子に対する放熱対策が必要となる場
合が多い。
Important as a sensor. Among these integrated semiconductor devices, those using semiconductor elements operated by current injection often require heat dissipation measures for each semiconductor element.

集積化半導体装置の作製方法としては、半導体基板上に
半導体素子の形成とアイソレーションを行った集積化素
子を、能動面を上にしてマウントするいわゆるup −
s 1de −upでマウントする方法と。
A method for manufacturing an integrated semiconductor device is a so-called up-type method in which an integrated device, in which a semiconductor element has been formed and isolated, is mounted on a semiconductor substrate with the active surface facing upward.
How to mount with s1de-up.

個々に作製した半導体素子を能動面を下にしてマウント
するhわゆるup −s ide −downでマウン
トかつ配列を行う方法とがある。
There is a so-called up-side-down mounting and arrangement method in which individually fabricated semiconductor devices are mounted with their active surfaces facing down.

第1図C二前者の従来例を、また952図に後者の従来
例を示す。
FIG. 1C shows the former conventional example, and FIG. 952 shows the latter conventional example.

これらの従来例にはそれぞれ次のような問題点を有して
いる。まず、前者は放熱体1上の半導体基板2上で素子
の集積化及び配列を行っているため配列荷度が高いとい
う長所を有しているが、11!動領域3からの放熱が半
導体基板2を通して行われるため放熱が悪く、電流注入
動作型の半導体素子には不利であるという短所を有し工
いる。また。
Each of these conventional examples has the following problems. First, the former has the advantage of having a high arrangement load because the elements are integrated and arranged on the semiconductor substrate 2 on the heat sink 1, but 11! Since heat is dissipated from the dynamic region 3 through the semiconductor substrate 2, heat dissipation is poor, which is disadvantageous for current injection type semiconductor devices. Also.

後者は能動領域3が放熱体1に直接接しているため放熱
が良く電流注入動作型半導体素子に有利であるという長
所を有するが、半導体素子を個々に配列しなければなら
ないため配列精度が劣るという短所を有している。
The latter has the advantage of good heat dissipation because the active region 3 is in direct contact with the heat sink 1, and is advantageous for current injection operation type semiconductor devices, but the arrangement precision is poor because the semiconductor devices must be arranged individually. It has disadvantages.

〔発明の目的〕[Purpose of the invention]

本発明は上記した点に鑑み表され念もので、同一半導体
基板上C二手導体素子の形成とアイソレーションを行っ
た集積化半導体素子をup −s ide −down
のマウントを行い、配列精度が高く且つ各半導体素子の
放熱を^めることが可能な集積化半導体装置の製造方法
を提供することを目的としている。
The present invention has been developed in view of the above-mentioned points, and is an integrated semiconductor device in which C two-handed conductor elements are formed and isolated on the same semiconductor substrate.
It is an object of the present invention to provide a method for manufacturing an integrated semiconductor device that can perform mounting, have high alignment accuracy, and improve heat dissipation from each semiconductor element.

〔発明の概要〕[Summary of the invention]

〔発明の概要〕 本発明はヒートシンク体となる金属片と電極分離のため
の絶縁体片をサンドウィッチ状に張り合わせ、半導体;
ぺ子の配列間隔に合わせたヒートシンク体のアレイを形
成し、しかる後それぞれのヒートシンク体にハンダ材を
用いて集積化半導体素子をup 5lde down 
でマウントを行うものである。
[Summary of the Invention] The present invention involves laminating a metal piece serving as a heat sink body and an insulating piece for electrode separation in a sandwich shape, and forming a semiconductor;
An array of heat sink bodies is formed in accordance with the arrangement spacing of the pens, and then an integrated semiconductor element is assembled using solder material on each heat sink body.
This is what you mount with.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体素子の!!積化は半導体基板上
で行うため配列精度か高く、またヒートシンク体は各素
子ごとに電気的分離が行われているため半導体素子を分
離することな(up−side−downのマウントを
行うことができる。かぐして本発明では配列精Kが高く
且つ半導体素子の放熱が良い集積化半導体装置を得るこ
とができる。
According to the present invention, the semiconductor element! ! Since the stacking is performed on the semiconductor substrate, the alignment accuracy is high, and since the heat sink body is electrically isolated for each element, there is no need to separate the semiconductor elements (up-side-down mounting is possible). According to the present invention, it is possible to obtain an integrated semiconductor device in which the arrangement precision K is high and the heat dissipation of the semiconductor elements is good.

〔発明の実施例〕[Embodiments of the invention]

以下図面を用いて本発明実施例の説明を行っていく。 Embodiments of the present invention will be explained below using the drawings.

第3図は本発明実施例の斜視図である。図中1はヒート
シンク体(放熱体)、5はヒートシンクの電気的分離の
ための絶縁体である。まずヒートシンク体lと絶縁体2
は、それぞれの厚さとろう材の合計が半導体素子の配列
間隔に等しくなるように選ぶ。そしてヒートシンク体重
と絶縁体2の接着を硬ろうを用いて行り。例えばヒート
シンク体に鋼(Cu) p絶縁体にアルミナ(A/、U
s)セラミック等を用い、硬ろうとしては銀ろう(Ag
(x)Cu(1−X))l金ろう(Au(x)Cu(+
−x) ) *を用いる。
FIG. 3 is a perspective view of an embodiment of the present invention. In the figure, 1 is a heat sink body (heat sink), and 5 is an insulator for electrically isolating the heat sink. First, heat sink body l and insulator 2
are selected so that the sum of their respective thicknesses and brazing filler metals is equal to the array spacing of the semiconductor elements. Then, the weight of the heat sink and the insulator 2 are bonded using hard solder. For example, the heat sink body is made of steel (Cu), the p insulator is made of alumina (A/, U
s) Ceramics etc. are used, and silver solder (Ag) is used as the hard solder.
(x)Cu(1-X))l Gold wax (Au(x)Cu(+
-x) ) * is used.

また、硬ろうを用いるかわりアルミナセラミック側Cニ
クロム(Cr) 、チタン(Ti )等を用いたメタラ
イズを施し、扁融点の軟ろう(ハンダ)を用いても良い
。次にヒートシンク体lζニインジウム(In) 、金
−スズ(Au(x)8n(+ −x)) 、金−シリコ
ン(Au(x)di(+−x))等(1,) ハンダ材
を選択蒸*、iy+等の手法を用いて形成する。しかる
後裔半導体素子間C二竜気的アインレーションを施した
半導体素子アレイをヒートシンク体の位随に合わせてマ
ウント固層させる。
Furthermore, instead of using hard solder, the alumina ceramic side may be metallized using carbon nichrome (Cr), titanium (Ti), etc., and soft solder (solder) having a low melting point may be used. Next, solder materials such as heat sink body lζnidium (In), gold-tin (Au(x)8n(+-x)), gold-silicon (Au(x)di(+-x)), etc. It is formed using methods such as selective vaporization* and iy+. The semiconductor element array, which has been subjected to C2 air inlation between the descendant semiconductor elements, is mounted and solidified in accordance with the position of the heat sink body.

こうし1第3図に示すごとく半導体素子アレイをup 
−s ide −downのマウントを行うことができ
る。
1 Upgrade the semiconductor element array as shown in Figure 3.
-side -down mounting is possible.

各半導体素子への電気的な接続は、各ヒートシンク体を
介して行えば良い。
Electrical connection to each semiconductor element may be made via each heat sink body.

本発明実施例によれば、6半導体素子の能動領域がヒー
トシンク体に半導体基板を介さず接しているためヒート
シンク体への放熱が良い。またこれにより庫流注入型の
半都体奏子、例えば半導体し〜ザ〜、Lgi)等の集積
化に有効である。
According to the embodiment of the present invention, the active regions of the six semiconductor elements are in contact with the heat sink body without intervening the semiconductor substrate, so that heat radiation to the heat sink body is good. Moreover, this is effective for the integration of storage and flow-injection type semi-conductor devices, such as semiconductor chips, LGI, and the like.

この他、半導体素子として隣接した素子からの熱影響が
問題となる場合にも本発明は有効である。
In addition, the present invention is also effective in cases where thermal influence from adjacent semiconductor devices is a problem.

例えは第2図従来例に用いたマウント方法に本発明を用
いる。この実施例を!44図に示す。この実施例の場合
、絶縁体5’l二は低熱伝導率を有する材料を用いる。
For example, the present invention is applied to the mounting method used in the conventional example shown in FIG. This example! It is shown in Figure 44. In this embodiment, the insulator 5'l2 is made of a material with low thermal conductivity.

こうすることにより第2図従来例との比較でも明らかな
ように、各半導体素子t′i電気的にはもちろん熱的に
も絶縁されることになる。
By doing this, as is clear from the comparison with the conventional example in FIG. 2, each semiconductor element t'i is electrically and thermally insulated.

以上述べてきたよう(二、本発明では半導体素子アレイ
をそのま1 up−side−downのマウントを行
うことができ、配列′n度が高く且つ放熱に優れた集積
牝牛導体装置を得ることができる。また、熱的絶縁を高
めた集積化半導体装置の作製も可能である。
As stated above, (2) the present invention provides an integrated conductor device that can directly mount a semiconductor element array up-side-down, has a high degree of arrangement, and has excellent heat dissipation. It is also possible to fabricate an integrated semiconductor device with improved thermal insulation.

本発明実施例では、各種材料等についてあ葦り多くは述
べていないが、これはそれぞれの応用に適した材料を選
べば良い。また1本発明実施例では各半導体素子に対す
る電極の接続について詳しく触れてい々いが、これは各
種技法の応用が可能であり、例えば電極形状に工夫して
コネクタ型とする等の応用が可能である。
In the embodiments of the present invention, various materials are not described in detail, but it is sufficient to select materials suitable for each application. In addition, in the embodiments of the present invention, the connection of electrodes to each semiconductor element will be described in detail, but various techniques can be applied to this, for example, the shape of the electrodes can be devised to form a connector type. be.

要するに本発明はその主旨、範囲を逸脱することなく各
種の応用が可能である。
In short, the present invention can be applied in various ways without departing from its spirit and scope.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来例を説明するための斜視図、第
3図及び第4図は本発明の詳細な説明するための斜視図
である。 l・・・・・・・・・ヒートシンク体。 2・・・・・・・・・半導体基板。 3・・・・・・・・・半導体素子の能動領域。 4.4′・・・・・・・・・半導体索子電極。 5.5′・・・・・・・・・絶縁体(熱抵抗体)。 代理人弁理士・則近憲佑(ほか1名) 第 1 図 第 2 図
1 and 2 are perspective views for explaining a conventional example, and FIGS. 3 and 4 are perspective views for explaining the present invention in detail. l・・・・・・Heat sink body. 2... Semiconductor substrate. 3... Active area of a semiconductor element. 4.4'・・・・・・Semiconductor cord electrode. 5.5'...Insulator (thermal resistor). Representative Patent Attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)、半導体素子をマウント固着せしめる所定の厚み
を有する金属片を、所定の厚みを有する絶縁体片を介し
てサンドウィッチ状に複数枚張り合せ固着した後、該金
属片の露出部の所望部に半4体素子をマウント固着する
ためのハンタ材を設け。 しかるl1erハンダ材を介して半導体素子をマウント
固着せしめることを特徴とする集積化半導体装置の製造
方法。
(1) After a plurality of metal pieces having a predetermined thickness for mounting and fixing a semiconductor element are bonded together in a sandwich shape through an insulator piece having a predetermined thickness, a desired portion of the exposed portion of the metal piece is fixed. A hunter material is provided to mount and secure the half-quad element. A method of manufacturing an integrated semiconductor device, which comprises mounting and fixing a semiconductor element through a suitable l1er solder material.
(2)、絶は棒片には隣接した半導体素子間に所望の熱
抵抗を与える低熱伝導率材料を用いることを特徴とする
特許請求の1α囲第1項記載の集積化半導体装はの製造
方法。
(2) Manufacture of an integrated semiconductor device according to item 1, subsection 1α of claim 1, characterized in that the rod piece is made of a low thermal conductivity material that provides a desired thermal resistance between adjacent semiconductor elements. Method.
JP59030182A 1984-02-22 1984-02-22 Manufacture of integrated semiconductor device Pending JPS60175476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59030182A JPS60175476A (en) 1984-02-22 1984-02-22 Manufacture of integrated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59030182A JPS60175476A (en) 1984-02-22 1984-02-22 Manufacture of integrated semiconductor device

Publications (1)

Publication Number Publication Date
JPS60175476A true JPS60175476A (en) 1985-09-09

Family

ID=12296615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59030182A Pending JPS60175476A (en) 1984-02-22 1984-02-22 Manufacture of integrated semiconductor device

Country Status (1)

Country Link
JP (1) JPS60175476A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5022035A (en) * 1989-03-28 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser device
JPH03136287A (en) * 1989-10-20 1991-06-11 Sanyo Electric Co Ltd Semiconductor laser
EP0590232A1 (en) * 1992-09-28 1994-04-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser array and mounting method
JPH07193315A (en) * 1993-12-27 1995-07-28 Nec Corp Semiconductor laser system and manufacture thereof
JP2003158330A (en) * 2001-11-21 2003-05-30 Opnext Japan Inc Semiconductor laser coupler
JP2004328011A (en) * 1998-12-22 2004-11-18 Sony Corp Method for manufacturing semiconductor light emitting device
JP2007180163A (en) * 2005-12-27 2007-07-12 Samsung Electronics Co Ltd Light emitting device module
JP2009009991A (en) * 2007-06-26 2009-01-15 Seiko Epson Corp Light source device, projector, monitor device
JP2012182482A (en) * 2008-04-17 2012-09-20 Samsung Led Co Ltd Sub-mount, light-emitting diode package, and manufacturing method of the same
WO2013118800A1 (en) * 2012-02-08 2013-08-15 ウシオ電機株式会社 Semiconductor device
WO2013146646A1 (en) * 2012-03-30 2013-10-03 ウシオ電機株式会社 Semiconductor laser device
CN103633549A (en) * 2012-08-30 2014-03-12 苏州长光华芯光电技术有限公司 Packaging method of semiconductor laser array single chip
JP2019212879A (en) * 2018-06-06 2019-12-12 海華科技股▲分▼有限公司 Flip chip type light emitting module

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5022035A (en) * 1989-03-28 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser device
JPH03136287A (en) * 1989-10-20 1991-06-11 Sanyo Electric Co Ltd Semiconductor laser
EP0590232A1 (en) * 1992-09-28 1994-04-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser array and mounting method
JPH07193315A (en) * 1993-12-27 1995-07-28 Nec Corp Semiconductor laser system and manufacture thereof
JP2004328011A (en) * 1998-12-22 2004-11-18 Sony Corp Method for manufacturing semiconductor light emitting device
JP2003158330A (en) * 2001-11-21 2003-05-30 Opnext Japan Inc Semiconductor laser coupler
JP2007180163A (en) * 2005-12-27 2007-07-12 Samsung Electronics Co Ltd Light emitting device module
JP2009009991A (en) * 2007-06-26 2009-01-15 Seiko Epson Corp Light source device, projector, monitor device
JP2012182482A (en) * 2008-04-17 2012-09-20 Samsung Led Co Ltd Sub-mount, light-emitting diode package, and manufacturing method of the same
WO2013118800A1 (en) * 2012-02-08 2013-08-15 ウシオ電機株式会社 Semiconductor device
WO2013146646A1 (en) * 2012-03-30 2013-10-03 ウシオ電機株式会社 Semiconductor laser device
CN103633549A (en) * 2012-08-30 2014-03-12 苏州长光华芯光电技术有限公司 Packaging method of semiconductor laser array single chip
JP2019212879A (en) * 2018-06-06 2019-12-12 海華科技股▲分▼有限公司 Flip chip type light emitting module
CN110571320A (en) * 2018-06-06 2019-12-13 海华科技股份有限公司 Flip chip type light emitting module
US11309471B2 (en) 2018-06-06 2022-04-19 Azurewave Technologies, Inc. Flip-chip light-emitting module

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