JPS6018028B2 - Electronic clock with alarm - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multi-alarm electronic clock that can set multiple times and issues a warning when the set time is reached. The present invention relates to a multi-alarm electronic watch that has the function of

The standard alarm clocks are generally electronic alarm clocks that issue a warning when the set time comes and then issue a warning again when the set time comes. This is convenient in the case of time, but if it is a one-time set time, it is necessary to manually clear the contents of the set time.

For electronic clocks with multi-alarms that can set multiple time settings, when the time settings set for a specific channel match, the content is automatically cleared and a warning is issued even if the set time is reached again. It would be more convenient to set up a channel that is not set, and it would be very convenient to be able to select the appropriate channel at the right time depending on the convenience. Watches have not yet been developed. Therefore, after issuing a warning, the match signal should be set to avoid issuing a warning again.
It detects whether it is a coincidence signal for a single alarm or a recurrence alarm, and if it is a coincidence signal for a single alarm, resets the memory circuit provided in the channel, Clear the contents of the set time.

The purpose of this invention is to increase the added value of the alarm electronic watch by providing an auto-clear channel, and at the same time to make it easier for the wearer to handle it. A counter 1, a recurrent alarm setting storage circuit 2, a recurrent alarm set storage circuit 20 that stores whether or not it is set, a single alarm storage circuit 3, a single alarm set storage circuit 21, a single alarm coincidence detection circuit 12, and a recurrent alarm storage circuit. A switch circuit 4 for time-divisionally transmitting the contents of the set time of the circuit 2 and the single-shot alarm storage circuit 3, a time and component force counter, and a match for checking whether the contents of the recurrent alarm storage circuit 2 and the single-shot alarm storage circuit match. It is composed of a circuit 5 and an alarm drive circuit 23.
Next, the operation of the present invention will be explained.

The oscillation output signal using a crystal oscillator is frequency-divided and the IHZ signal a is input to the second counter 6, and the output signal becomes a pulse signal 6 with a period of 1 minute and is converted to 50 seconds by the latch circuit 7.
The time is formed into a single pulse signal c having a pulse width of 0 milliseconds, and is inputted to a component force counter 1 to count the time.

Recurrence alarm memory circuit 2 for setting alarm time
The single-shot alarm memory circuit 3 can be configured by a counter circuit like the hour and force counter 1, and can be set to any desired time by inputting a clock signal to the IN-1 or IN-2 terminal, respectively. be able to. At the same time, the input signals IN-1 and IN-2 are input to the set terminals of the recurrent alarm set storage circuit 20 and the single alarm set storage circuit 21, respectively, so that the fact that the setting operation has been performed is stored here. Signal c is a sampling pulse signal for time-dividing the output signals of the recurrent alarm storage circuit 2 and the single alarm storage circuit 3, and is
This is the HZ output signal.

Further, the switch circuit 4 can be constituted by a NAND circuit or a transmission gate, and is a circuit for time-division transmission. Next, the output of the switch circuit 4 is inputted to the coincidence circuit 5 together with the output of the time and component force counter 1 in order to check whether the output matches the time and component force counter 1. The coincidence circuit 5 is constituted by an exclusive OR circuit, a NOR circuit, and a NAND circuit, and the coincidence circuit outputs only when a coincidence between the component output terminal 1 and the recurrent alarm storage circuit 2 or the single alarm storage circuit 3 is detected. becomes low level. In case of mismatch, the level is always high. The waveform of this signal is shown in FIG.

For example, at time To, when the set time of the single alarm memory circuit coincides with the time of the component force counter 1, the output of the toe number circuit 5 changes from a high level state to a low level, due to a mismatch in the recurrence alarm memory circuit. The high level results in a pulse signal f.

Here, the signal c is inverted by the inverter 10' to create the signal d, and the NOR circuit 11 uses the two inputs f and d to create a single pulse g with a narrower pulse width. This signal serves as a trigger signal for issuing an alarm and is sent to the alarm drive circuit 23 to issue an alarm. Next, in order to detect which of the contents of the recurrent alarm storage circuit 2 or the single alarm storage circuit 3 matches, the alarm trigger signal g is input to the single alarm coincidence detection circuit 12. Since the other input of the single alarm coincidence detection circuit 12 configured by an AND circuit is a signal obtained by inverting the sampling pulse signal c by the inverter 13, single alarm coincidence detection is performed only when the single alarm storage circuit 3 matches. The circuit 12 outputs one single pulse such as h. On the other hand, if the recurrent alarm storage circuit 2 matches, the single alarm match detection circuit 12
This can be determined because no output signal is generated. This signal h becomes a reset input of the single alarm set storage circuit 21. Since the output of the NOR circuit 30 is connected to the reset terminal of the single alarm memory circuit 3, the contents of the single alarm memory circuit 3 are cleared at 0:00 oq. On the other hand, the output of the NOR circuit 31 is specially provided in the switch circuit 4 to be inverted from high level to low level and held, and the output of the set detection circuit 13 is checked for coincidence in the single alarm storage circuit 3. When the signal is present, it is always at a high level, and since it is inverted by the NAND circuit 14, it is always at a low level. Therefore, the output f' of the matching circuit 5 is at a high level, and no alarm will be generated again after that. Further, even if the hour and component force counters reach 0:0, no alarm will be generated because the reset detection circuit 13 is provided and no coincidence signal is output. However, when a clock signal is again input to the input terminal 2 of the single-shot alarm storage circuit 3 to set an arbitrary time, the single-shot alarm set storage circuit 21 maintains the set state and drives the alarm at the set time. If it is desired to clear the contents of the recurrent alarm storage circuit, it is cleared by applying one pulse to the reset terminal R-1 of the single alarm set storage circuit 20 with a manual switch. If you want to manually reset a single alarm, use the reset terminal R.
If you put one pulse into -2 with the switch, it will be cleared.
As mentioned above, even though there are multiple channels, the set time set in a specific channel is checked in a time-sharing manner, and one matching circuit is shared. Therefore, the circuit could be simplified.

Furthermore, by using one AND circuit to check the synchronization of the sampling pulse signal and the alarm drive signal, it is very easy to determine whether it is a coincidence of a recurrent alarm or a coincidence of a single alarm. Ta. Furthermore, the present invention provides set storage circuits 20, 21 for each channel.
An R-S flip-flop such as the one shown in FIG. However, 0:0 Pigako has the great effect of not emitting an alarm.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a waveform diagram showing the operation. 1...Component force counter, 2...Recurrence alarm setting memory circuit, 3
...Single alarm memory circuit, 4...Switch circuit, 6...Second counter, 7...Latch circuit, 20...Recurrence alarm set memory circuit, 21...
. . . Single alarm set storage circuit, 23 . . . Alarm drive circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1 In a multi-channel electronic clock with an alarm that has a time reference signal generator, a time counting circuit for counting time, a memory circuit that can set multiple times, and a matching circuit, and that issues an alarm when the set time is reached. There is a single alarm channel that issues an alarm when the time comes and does not issue an alarm after that even if the set time comes.
A recurrent alarm channel is provided that issues an alarm every time a set time elapses, and the single alarm channel stores whether the set time is in a set state or a non-set state, and is set to a non-set state by a coincidence detection signal from the coincidence circuit. It is composed of a set memory circuit that stores the set state, and a set time memory circuit that inputs the output of the set memory circuit to a reset terminal and sets the set time, and the coincidence circuit stores the time count signal and the set memory. An electronic timepiece with an alarm, comprising a coincidence detection circuit that detects coincidence between the circuit and the set time storage circuit.