JPS6018148B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a diode-destructive programmable read-only memory.

In a diode-destructive programmable read-only memory, memory cells are arranged in a matrix in the center of a semiconductor chip, and decoders and other peripheral circuits are provided around the memory cells.

As shown in Figure 1, the memory cell is constructed by connecting the emitter E and collector C of a transistor TR between the X-line and Y-line, as if two diodes were connected between the The circuit configuration is connected in the direction.

When writing, a voltage above the breakdown voltage G input in the opposite direction is applied between the emitter base and the junction to destroy this junction. In order to facilitate this writing and to improve the characteristics after writing, each memory cell is required to have the following performance. That is, 1, collector-emitter reverse voltage Vc
2. The write current is small. 3. After writing, there is a complete ohmic contact between the emitter and base, and the reverse leakage current between the collector and base can be ignored. By the way, since these characteristics are different from those of transistors forming the peripheral circuit, in order to satisfy these performance characteristics, the memory cell may be manufactured in a process completely different from that for the transistors forming the peripheral circuit. However, if the peripheral circuit and the memory cell are made in separate processes, the number of man-hours increases and the cost of the semiconductor memory device increases. An object of the present invention is to provide a manufacturing method that can manufacture a peripheral circuit and a memory cell in the same process and provide the memory cell with the above-mentioned performance.

In order to achieve this objective, the method for manufacturing a semiconductor memory device of the present invention simultaneously forms a base diffusion region for a memory cell and a base diffusion region for a peripheral circuit on the same semiconductor substrate with an insulating layer covered thereon. a step of selectively forming an emitter diffusion region of a transistor constituting a peripheral circuit on the substrate; and a step of forming a window in an insulating material layer of an electrode portion of a transistor constituting the peripheral circuit and a transistor constituting a memory cell. a step of providing a polysilicon thin layer containing no impurities so as to be in contact with the base diffusion region through the window of the electrode portion of both transistors; forming an emitter region of a transistor constituting a memory cell by providing an impurity diffusion source only on the upper part of the emitter, and performing diffusion from the impurity diffusion source through a polysilicon thin layer in a raised window portion of the emitter; and a step of forming a conductive layer on the substrate and then patterning it to attach electrodes on the emitter region and base region of the transistor forming the peripheral circuit and the emitter region of the transistor forming the memory cell. It is characterized by including the following, and will be described in detail below based on examples.

In FIG. 2, 1 is a P-type silicon semiconductor substrate, 2 and 3 are buried layers, 4 and 5 are N-type epitaxial layers, 6 is a base diffusion region of a peripheral circuit transistor, and 7 is a memory cell transistor. In the base diffusion region, the two base diffusion regions are made in the same diffusion process.

8 is an insulating layer made of silicon dioxide (Si02).

Next, as shown in FIG. 3, an emitter diffusion window 9 is formed in the insulator layer 8 covering the base diffusion region 6 of the transistor for the peripheral circuit, and then the emitter of the transistor for the peripheral circuit is diffused to form the base as shown in FIG. N0 emitter diffusion regions 10 are created within the diffusion region 6.

Thereafter, as shown in FIG. 5, the emitter electrode window 11 of the peripheral circuit transistor is removed in the same process using one mask.
, the base electrode window 12 and the emitter electrode window 13 of the memory cell transistor are raised, and a non-doped polysilicon thin layer 14 is deposited on the entire surface as shown in FIG. Next, phosphor glass (PSG), which serves as an impurity diffusion source, is deposited on the polysilicon thin layer 14.
), the adjacent glass (target G) on the peripheral circuit transistor is removed, leaving the adjacent glass (target G) layer 15 only on the memory cell transistor. When the previous steps are completed, the back side of the silicon semiconductor substrate 1 is covered with gold (A
u) After attaching 16, heat it to perform gold diffusion. This gold diffusion reduces the lifetime of carriers and improves the switching characteristics of the transistor, and is a process that is always performed in the manufacture of switching transistors. Due to the heating in this gold diffusion step, phosphorus (P) is transferred from the phosphorus glass (Tori G) layer 15 to the polysilicon thin layer 14.
Through the base diffusion region 7 of the memory cell transistor
is diffused to form an emitter region 17.

Since this base diffusion is performed through the thin polysilicon layer 14, it forms a very shallow emitter region.Since it is performed through the emitter electrode window 13, which has a small area, the junction area is also small, and the parentheses are connected to the base. far away from the interface between the collectors. After the gold diffusion and the emitter diffusion of the memory cell as described above are completed, the adjacent glass layer 15 is washed out and removed.

During this washout, silicon dioxide (Si02) (generated by heating during the gold diffusion process) formed on the polysilicon stack 14 covering the peripheral circuit transistors is also removed at the same time. Thereafter, as shown in FIG. 7, an aluminum (A) layer 18 is deposited on the exposed polysilicon thin layer 14 and heated to perform aluminum (A)-silicon (Si) sintering. Through this sintering, the polysilicon thin layer 14 is alloyed by the penetration of aluminum (Al), and this alloyed region is further divided into the emitter diffusion region 10 of the peripheral circuit transistor, the base diffusion region 6, and the emitter diffusion region of the memory cell transistor. 17, aluminum (A〆) layer 1
A good ohmic contact is formed between 8 and these regions. However, the penetration of the alloyed region into these regions is very shallow due to the intervening thin polysilicon layer 14. Therefore, even if the emitter diffusion region 17 of the memory cell transistor is shallow and does not extend much laterally from the periphery of the emitter electrode window 13,
It does not reach the base diffusion region 7. Thereafter, the aluminum (A) layer 18 and the polysilicon thin layer 14 are each patterned by selective etching that is commonly performed, and as shown in FIG. The emitter electrode 21 of the cell transistor is formed, and then a cover glass (not shown) is attached to the surface, and the manufacture is completed through processes such as measuring characteristics and scraping.

As described in detail above, the present invention not only allows transistors for peripheral circuits and transistors for memory cells to be manufactured in almost the same process, but also enables a polysilicon layer to be interposed between the emitter diffusion region of the memory cell and the thin aluminum layer. Therefore, even if the emitter diffusion region is shallow, no short circuit occurs between the emitter and the base even after heat treatment in various manufacturing steps.

Furthermore, the base diffusion region and emitter diffusion region of transistors for peripheral circuits are not made in any special way and follow the usual method of manufacturing transistors for peripheral circuits, so not only are the characteristics of the device itself unchanged, but the emitter region of the memory cell Since the diffusion region is shallow and does not extend much laterally from the periphery of the emitter electrode window, the collector-emitter reverse voltage is high and the write current is also low. Also, even after writing, there is a large distance between the broken part of the emitter-base junction and the base-collector junction, so
In addition to the fact that the reverse leakage current between collector and base is almost negligible, the shallowness of the emitter diffusion region completely destroys it and forms a good ohmic contact, which almost satisfies the performance of memory cell transistors. The characteristics also improve dramatically.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a memory cell, and FIGS. 2 to 8 are process cross-sectional views showing an embodiment according to the present invention. In the figure, 1 is a silicon semiconductor substrate, 6 and 7 are base diffusion regions, 10 and 17 are emitter diffusion regions, 11 and 13 are emitter electrode windows, 12 is a base electrode window, 14 is a polysilicon thin layer, and 15 is a scale glass. layer, 18 is an aluminum layer, 19 and 21 are emitter electrodes, 20'
It is a ground electrode. Figure 'Figure 2 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 5

Claims (1)

[Claims] 1. A step of simultaneously forming a base diffusion region for a memory cell and a base diffusion region for a peripheral circuit on the same semiconductor substrate on which an insulator layer is deposited, and forming an emitter diffusion region of a transistor constituting the peripheral circuit on the substrate. a process of selectively forming a window in the insulator layer of the electrode part of the transistor constituting the peripheral circuit and a transistor constituting the memory cell; A step of providing a polysilicon thin layer containing no impurities so as to be in contact with the diffusion region, and providing an impurity diffusion source only on the polysilicon thin layer of the transistor constituting the memory cell, from the impurity diffusion source to the apertured portion of the emitter. A step of forming an emitter region of a transistor constituting a memory cell by performing diffusion through a thin layer of polysilicon, a step of removing the impurity diffusion source, and a step of forming a conductive layer on the substrate and then patterning it. 1. A method of manufacturing a semiconductor memory device, comprising the step of attaching electrodes to the emitter region and base region of a transistor constituting a peripheral circuit and the emitter region of a transistor constituting a memory cell.