JPS6018150B2 - Insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device, and particularly to a semiconductor device having an ultra-miniaturized one-transistor memory cell.

In conventional semiconductor devices of this type, the W (width) direction of the gate region of the insulated gate field effect transistor is not self-aligned with the W direction of the gate electrode, so a mask for forming the gate region and a charge transfer gate are formed. The mask has the disadvantage that it must have a margin for mask misalignment in the W (width) direction of the transistor. An object of the present invention is to provide an insulated gate field effect transistor whose gate can be self-aligned in the width direction as well. According to this invention, at least the film thickness of the field insulating film portion in contact with the width direction of the gate and the channel stopper impurity concentration of the channel stopper region formed therebelow are the same as those of the field insulating film portion formed in the other portions. It is possible to obtain an insulated gate field effect transistor characterized in that the film thickness of the desert part and the channel stopper impurity concentration of the channel stopper region formed thereunder are different.

That is, the present invention is characterized by a semiconductor substrate of one conductivity type, a bit line of opposite conductivity extending in one direction along the main surface of the semiconductor substrate, and a bit line in contact with one end of a partial region of the bit line. a gate portion, a capacitor portion that is in direct contact with the gate portion, and an end portion in the length direction that substantially coincides with one end portion of the partial region of the bit line in a planar shape, and the capacitor portion passes over the gate portion and the capacitor portion. a gate electrode having a uniform inside extending in a direction perpendicular to the one direction; a thick first field insulating film provided apart from a boundary in the width direction of the gate portion; a channel stopper region formed in self-alignment from the first field insulating film and in contact with the boundary in the width direction of the gate portion; The present invention provides an insulated gate field effect semiconductor device having a second field insulating film different from the insulating film.

In the insulated gate field effect transistor of the present invention, in the W (width) direction of the transistor, an impurity having the same conductivity type as the substrate and at a higher concentration than the substrate is introduced only in the portion that does not overlap with the gate electrode portion. Since it is changed to a stopper region, it becomes a self-aligned type in the W (width) direction as well, and a margin in the gate portion W (width) direction in a conventional insulated gate transistor is not required, and the degree of integration can be improved.

Further, since a partial region of the bit line, that is, one end of the source region (or drain region) coincides with the end of the gate electrode, the source region can be formed in self-alignment with the gate electrode. On the other hand, since the capacitive part is directly connected to the gate part (channel region), that is, there is no drain region (or source region), there is no need to consider self-alignment formation of this drain region, and the gate electrode and the gate electrode of the present invention do not need to be considered. You can. Next, in order to better understand the present invention, a case in which the present invention is applied to a semiconductor memory device will be described with reference to the drawings.

1A and 1B show a one-transistor type semiconductor memory device consisting of a conventional insulated gate type MOS transistor and an insulated gate type capacitor part.
Medium B formed between thick field oxide films 107
On the other hand, the gate electrode 103 has an (A
- It is necessary to provide some margin for B).

In addition, in FIGS. 1A and 1B, 108 is a P-type substrate, 106
For example, a P-type impurity region (channel stopper region) with a concentration of 1 and 2/2, 105 is an electrode of a capacitive part, 104 is a capacitive part, 101 is an N-type bit region and a field oxide film 10
The part surrounded by 7, 109, is in the gate oxide film. As described above, in the conventional technology, it is always necessary to form a wide gate electrode, which causes problems in the degree of integration.

\FIGS. 2A and 2B show an embodiment of the present invention, in which the gate portion 202 is composed of a gate electrode 203 having a center C narrower than a center D of a thick field oxide film 207. Using the gate electrode 203 as a mask, the gate oxide film 209 is removed, and then impurity regions 210 and 210' having the same conductivity type as the substrate and having a higher concentration than the substrate are formed from the surface of the substrate 208 using the gate electrode 203 as a mask.

These regions 210, 210' serve as channel stopper regions, and may be formed by ion implantation or diffusion. In the present application having such a configuration, the formation of the gate electrode 203 can be aligned with a margin of (D-C), while the regions 210 and 210' are formed from the field oxide film 207 and the gate electrode 203 in a self-aligned manner. Therefore, the degree of integration is improved and the accuracy is high.

In addition, in FIGS. 2A and 2B, 208 is a P-type substrate, 206
209 is a gate oxide film, and 211 is a field oxide film formed after forming regions 210 and 210' (the thickness is the same as that of the field oxide film 207 formed by a known method). Oxide film 20
7), 205 is the upper electrode of the capacitive part, 20
Reference numeral 4 designates a capacitor portion (thin, an oxide film portion, and the underlying substrate surface inversion layer serves as a lower electrode), and 201 represents an N-type bit region surrounded by a field oxide film 207.
As an example, in the case of a P-type substrate, P
The field part (channel stopper region 206 and field film 207) is formed by diffusing type impurities (1 and 2/2) and thermally oxidizing the area (31.2 peaks).
An inner field portion (second channel stopper regions 210, 210' and field film 211) is formed by impurity ion implantation (Mi 1 and 3/3) and subsequent oxidation (2000A). Therefore, both field portions have different values for both impurity concentration and oxide film thickness. In the case of a P-type substrate, when forming 210 and 210', boron ions are first implanted, and then the portion 201 is
The ion-implanted boron is canceled by the diffusion of phosphorus (31 and 9 to 2 o/ground), forming a diffusion layer portion.

After that, due to thermal oxidation, a thick oxide film is formed on the part 201 (ra 0.5 mountain), but the poron ions are implanted into the part 21.
Since the oxidation rate of the 0,210' portion is slow, only a thin oxide film is formed during the thermal oxidation process. (ra 0.1
Therefore, the impurity concentration below the second field must be higher than that in the first field. P
+-type channel stopper regions 210 and 210' are separated by 210 and 2 by the amount of misalignment with respect to the field oxide film.
The dimensions of 10' are different, and in the case of maximum misalignment, only one of regions 210 and 210' may be present. Note that when forming the bit region 201 after forming the regions 210 and 210', the region 21
If the process is reversed, an insulating film is provided on the bit region 201 and then the mustard regions 210, 210' are formed. Furthermore, in these steps, the pond region may be formed by covering with a photoresist film without providing an oxide film or an insulating film. Also, area 21
The formation of 0,21-0' may be performed through an oxide film, or the present invention can be applied even when an N-type substrate is used, contrary to this embodiment. It is also possible to convert the portions of the substrate and inverse guide rope type regions previously formed in the gate portion, which correspond to the regions 210 and 210' in FIG. 2, into the substrate and the same guide fin type.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1A is a plan view of a semiconductor device according to the prior art;
FIG. 1B is a cross-sectional view of FIG. 1A taken along cutting line b-M and viewed in the direction of the arrow. FIG. 2A is a plan view showing one embodiment of the present invention;
Figure B is a sectional view of Figure 2A taken along cutting line bb' and viewed in the direction of the arrow. In addition, in the figure, 101,2
01 is a bit line, 102, 202 is a gate part, 103,
203 is a gate electrode, 104 and 204 are capacitor parts, 105
, 205 are capacitive electrodes, 106, 206 are channel stoppers under the field oxide film, 107, 207 are field oxide films, 108, 208 are substrates 109, 209 are gate oxidation pus, 210, 210' are the same conductivity type as the substrate. A region 211 with a higher concentration than the substrate is an oxide film. Figure 1 Figure 2

Claims (1)

[Claims] 1 A semiconductor substrate of one conductivity type, a bit line of an opposite conductivity type extending in one direction along the main surface of the semiconductor substrate, a gate portion in contact with one end of a partial region of the bit line, and the gate A capacitive part is in direct contact with the capacitive part, and an end part in the length direction substantially coincides with one end part of the partial area of the bit line in plan view, and the capacitive part is perpendicular to the one direction, passing over the gate part and the capacitive part. a gate electrode having a uniform width and extending in a direction; a thick first field insulating film provided apart from a widthwise boundary of the gate portion;
is formed by self-alignment with the field insulating film of
a channel stopper region in contact with a boundary in the width direction of the gate portion; and a second field insulating film provided on the channel stopper region that is thinner than the first field insulating film and different from the gate insulating film. An insulated gate field effect semiconductor device comprising: