JPS6019020B2 - Digital circuit inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for automatically detecting failures in digital circuits, and particularly to a digital circuit inspection apparatus for efficiently inspecting the hardware of IC, LSI packages, and digital circuit mounting boards. be.

In recent years, the importance of inspection and maintenance has increased as digital devices such as digital computers have become larger and their design and production have become more automated. In particular, as circuit testing units become larger due to the shift to LSI, it has become difficult to detect failures using conventional methods, and the establishment of new testing methods is desired. Conventional testing methods are based on inputting a test data series into the circuit under test and comparing the output series with the output series of a normal circuit determined in advance. As a result, it has become less practical. The main reason for this is that there is no general method for creating input test data sequences for sequential logic circuits, and test sequences are determined by trial and error through logic simulations that assume possible failures. As the number increases, the calculation time for logical simulation increases, and furthermore, the test data series also becomes significantly longer. Furthermore, even if a test data series and a normal output series are obtained, a device for applying them to the circuit under test and comparing and discriminating the outputs also requires a large capacity memory, making it complicated and expensive. Furthermore, in this successive approximation method, if the circuit under test is a sequential logic circuit, it is necessary to set the initial internal state of the circuit under test to a predetermined state, but this also becomes a complicated procedure as the circuit size increases. often required. In recent years, as one of the testing methods that does not use such a successive approximation method, binary values (
A code string that takes logic 1 and 0) is added, and 2 is added to the output terminal.
the number of clocks at which one of the value signs (e.g. logical 1) appeared;
A type of statistical method has been proposed for testing digital circuits by counting the number of times the output sign changes and comparing it with the count value for a normal circuit, but it is not practical in terms of test reliability. However, it has not been widely used.

The present invention proposes a simple, inexpensive, and highly reliable digital circuit testing device based on a new testing method that does not use a successive approximation method but instead focuses on statistics representing the correlation between input and output of the circuit under test. be.

A digital circuit testing device according to the present invention includes a pattern generation section that generates a plurality of random binary code strings to be supplied to a plurality of inputs of a digital circuit to be tested, and an output binary code string supplied from the output of the digital circuit to be tested. a statistics calculation unit that calculates statistics based on the received data, and a judgment unit that compares the calculated statistics with statistics obtained when the digital circuit under test is normal and determines whether the digital circuit under test is correct or not. and a control unit that controls the operations of the pattern generation unit, the statistic calculation unit, and the determination unit, and makes a determination as to whether the digital circuit under test is correct based on the statistics calculated over a predetermined period. The circuit testing device is provided with a correlation calculation circuit connected to the output of the digital circuit to be tested or the output of the digital circuit to be tested and the output of the pattern generation unit to calculate the statistics representing the correlation in the statistics calculation unit. It is characterized by:

DESCRIPTION OF THE PREFERRED EMBODIMENTS The digital circuit testing device of the present invention will be explained in detail below with reference to the drawings.

The inspection device of the present invention mainly has the following features as shown in FIG.
A pattern generator 2 applies a random binary code string to the input terminals 1-1, 1-2, ..., 1 of the circuit under test 1, and a statistic representing the correlation between input and output (for example, autocorrelation of output ,
A statistics calculation unit 3 that calculates the input/output cross-correlation), a determination unit 4 that compares the calculated statistics with the case of a normal circuit and determines whether or not there is a failure in the circuit under test, and controls the entire system. The control section 5 is composed of four parts.

The principle and operation will be explained below based on a specific example. Here, as an example of the testing apparatus according to the present invention, a testing apparatus for sequential logic circuits, which is normally considered difficult, will be described. To simplify the explanation, the circuit to be tested is assumed to be a synchronous sequential logic circuit with one input and one output, but it goes without saying that the present invention is also effective for multi-output circuits and combinational logic circuits. FIG. 2 shows the configuration of a synchronous sequential logic circuit with one input and one output. In the same figure, 1 is the circuit under test, 1-1,
1-2, . . . , 1 represents an input terminal, 1-0 represents an output terminal, and 1-C represents a clock input terminal. A clock is supplied from a clock generator 7 in the control section 5 to each section of the apparatus and the circuit under test. 2 is a pattern generation section that applies random test input to the circuit under test, and in this example, M
Random 2 with probability 1/2 using a sequential shift register
Value codes are input to input terminals 1-1, . . . , 1-1. As shown in Fig. 2, the M-series shift register is composed of flip-flops F,...F,...Fr, and outputs 2-r from the final stage of the shift register, and outputs from appropriate intermediate stages. The exclusive OR or match with the output 2-i is taken by the logic circuit 2-a, and it is returned to the input of the first stage of the shift register. -C is obtained in synchronization with the clock supplied to C. The ratio of binary 1 and 0 in this binary code string is, when the logic circuit 21a is a BE alternative OR, 1 is Ura 10, 2, and o is ki - death? Therefore, when the logic circuit 2-a is assumed to be a match, ・ is Ge-Ota ≠;, o is Ura 10, and so on.
Therefore, if y is large enough, for example 33, then 2
Since r-1 is approximately 1 pio and the period is extremely long, it is practically acceptable to consider it as a random binary code with a probability of 1'2. Also, the appropriate stage from which to take output 2-i is determined by the number of stages y in the shift register. For example, if y = 33, if output 2-i is taken from the 1st stage. Good things have been mathematically proven. Since the present invention departs from the inspection of logic circuits, which is the main purpose of the present invention, further explanation will be omitted, and only points to be noted when using the M-sequence shift register in the present invention will be described. The first problem is the initial value. In other words, logic circuit 2
When exclusive OR is used for 1a, it is necessary to avoid setting all the states of each flip-flop to 0, and to avoid setting all the states of each flip-flop to 1 when 2-a is a match. By doing this, you will see that no matter how much you shift, it will not move to another state. If you start from a state other than the above, this will not happen from any state, so when the circuit enters a non-transition state such as when turning on the power, it is possible to move to another state (for example, , inverting the state of some flip-flops, etc.). Next, depending on the number of stages r of the shift register, it may be necessary to draw from two or more places instead of one from an intermediate stage; in this case, the logic circuit 2
1a may be combined in multiple stages to obtain the exclusive OR of the final stage output 21r and the outputs of a plurality of intermediate stages. The circuit under test 1 receives the random binary pattern generated in this way for each clock, and changes the state of the internal flip-flop by the clock input to the clock input terminal 11c. Generates a binary output at 0.

Therefore, the binary code string obtained at the output 1-0 is a random code string in which the input random pattern has been uniquely modulated by the circuit under test. This inspection device pays attention to this and calculates the output statistics using the statistics calculation unit 3.
This is to judge the circuit under test. The statistics calculation unit shown in 3 in FIG. 2 calculates three types of statistics. The first is the frequency z of occurrence of 1 in the output calculated by the circuit shown in FIG. 3-A. 3-A, a gate circuit 3-2 outputs a clock only when the output of the circuit under test is 1, and a binary counter 3-1 counts the output, and the frequency z of the output 1 is converted into a binary digital value. Find it as.

The second one corresponds to the autocorrelation of the output, and is
It is calculated by the autocorrelation calculation circuit of In 31B, 313 is a delay circuit that delays the output by one clock or more.

AND circuits 3-4 and 3-9 output a clock only when the output of the circuit under test is 1 and the delayed output is also 1, and 3-5 outputs a clock from gate circuit 3-9. This is a binary counter that counts the number of clocks. When the counter value is reset to 0 at time 0 and the device is operated for N clock hours, the final value Tt of the counter 3-5 is the binary output of the circuit under test at the clock generation instant t, which is expressed as y( t〉
When (y(t)=1 or 0) and the delay time by the delay circuit 3-3 is 7, it is expressed as follows. T
Ding. = Thing y(t)y(t-d.) [11t=1 Therefore, it can be seen that Td represents the autocorrelation of the output y(t) of the circuit under test.

The third statistic corresponds to the cross-correlation between the input and output of the circuit under test, and is calculated by the cross-correlation calculating circuit 3-C in FIG.

In 3-C, 3-6 is a delay circuit with an appropriate delay time 2, similar to 3-3, and is used to delay the input to the appropriately selected i-th input terminal of the circuit under test. .

Logic bond circuits 3-7 and 3-10 have an output of 1 when the output of the circuit under test is 1.
A clock is output only when the output of the delay circuit is also 1, and 3-8 are binary counters that count the clocks output from the gate circuits 3-10. When counting for N clock hours after resetting the counter to 0, the value R72,i of counters 3-8 indicates that the input of the i-th input terminal is x, (t), (xi (t) = 1 or 0)
, the output is y(t), then the following is obtained. ．． N R72,1= Z xi (t1cho2)y(t)■t:1
Therefore, R72,i is input x'(t) and output y(t
) can be seen to represent the cross-correlation.

In this way, in the statistics calculation section, the output frequency of occurrence of 1 Z, autocorrelation TT, and cross-correlation R2,i are input to the counters 3-1, 3-5, and 3-8 in binary digital form, respectively. Determined as a value. The value of each counter starts counting from the reset state ○, and stops its operation after an appropriately determined N clock time. This control is controlled by the control unit 5 through the reset terminals R-1, R -2, R-3
and through enable terminals E-1, E-2, and E-3. The enable terminal controls the operation of the counter in two ways.
This is a terminal that is controlled by a value sign, and if it is 1, it will be in a counting state, and if it is 0, it will be in a counting state. Since the final value of each counter may be at most N' when counting for N clocks, it goes without saying that a counter that can count N or more must be used. The delay times 7, , 2 may be appropriately selected depending on the target circuit. The determination unit 4 sends the test statistics Z, T, , R, and i obtained as binary digital values to the output terminals D-1, D-2, and D-3 of each counter of the statistics calculation unit. The quality of the circuit under test is determined by comparing it with the expected value of statistics of a normal circuit, which has been determined in advance.

In other words, if each of the obtained statistics is within the allowable error range, the circuit under test is considered normal, and Z, T7・, R↑2,
If any one of i is outside the allowable error range, the circuit under test is considered to have some kind of failure.
In the judgment unit 4 of FIG. 2, 4-2, 4-6, 4-10
are registers that store the allowable upper limit values of Z, Th, R72, and i, respectively, and 4-1, 4-5, and 4-9 are comparators, and when each statistic is smaller than the allowable upper limit value, Outputs 1 to the power terminals P-1, P-2, and P-3. Also, 4-4,
4-8, 4-12 are registers that store the allowable lower limit values of Z, T71, R72, and i, respectively, and 4-3, 4-7
, 4-11 are comparators that output 1 to output terminals P-4, P-5, and P-6 when each statistic is larger than the allowable lower limit value.
Logic circuit 4-13 takes the AND of all comparator outputs,
When all three types of test statistics Z, TT, , R72, and i are within the allowable value range, 1 is output. Furthermore, 4-14 represents a circuit that displays the determination result using a lamp or the like according to an instruction from the control section. The control circuit 5 shown in FIG. 2 resets each counter of the statistics calculation section at the same time as starting the chain test and puts it into operation, and the time counting circuit 5-1 stops each counter after N clocks and makes a judgment at that time. This command issues a command to display the results of the section.

The time counting circuit 5-1 keeps the enable terminal of each counter at 1 for N clock hours after the start of the test. In this device, the test is started when the terminal 51a is changed from 1 to 0.
The flip-flop 5-2 is for issuing a judgment display command one clock after the counter stops. Although it is obvious that the statistics of a normal circuit can be obtained by the statistics calculation section 3 of this device by inserting the normal circuit as the circuit to be tested, it is also possible to calculate the expected values of the statistics from the circuit diagram in advance. It is also possible.

The allowable error range is determined based on the expected value of the statistics of a normal circuit, and if it is wide, the test will be lenient, and if it is narrow, the test will be strict, but it should be set according to the purpose of use of the test equipment. . Inspection. The relationship between the number of blocks N and the error range will be described later. Next, using an actual circuit as an example, a calculation method for determining the expected value of test statistics from a circuit diagram will be explained, and it will be concretely shown that a faulty circuit can be determined based on these statistics.

FIG. 3 is an example of a sequential logic circuit having one D-flip-flop.

31-1 is a flip-flop, 31-2 and 31-3 are N
OT circuit, 3 1-4 are NOR circuits, 3 1-5 are AN
D circuit, 3 1-6 represents an EXC-LUSIVE-OR circuit.

311a and 31-b are input terminals, 311c is a clock input terminal, and 311d is an output terminal.

First, we calculate the expected value of the test statistics when no part of this circuit is faulty. Since the internal state of the sequential logic circuit shown in FIG. 3 is two states: the output Q of the flip-flop 31-1 is 0 or 1, the state S when Q=0 is
, Q=1 and state S2, this circuit is Q. For each clock, the internal state is changed according to the internal state and the binary pattern of the input terminals 311a and 311b. The output is
It can be seen that this is determined by the internal state and the value of the input terminal 31-b. This situation is shown in tables in FIGS. 4A and 4B. FIG. 4A is called a state transition table, in which the left column represents the current state and the upper row represents the current input pattern. In other words, 01 means that the input to the input terminal 31-a is 0, and the input to the input terminal 31-b is 1. The columns other than the leftmost column and the top row of Table 1 represent the destination of the state after the clock is turned on. For example, S2 in H-1 indicates that if the current state is S and the input pattern is 10, the next state will be S2. FIG. 4B is called an output table and shows the relationship between the status, input pattern, and output. The leftmost column and topmost row of the table represent the current state and input pattern, similar to FIG. 4A. The other parts are
It represents the current output. For example, 1 in H-2 means that if the state is S and the input pattern is 01, the output is 1.
That's it. means. It will be understood that FIGS. 4A and 4B can be easily obtained from the logic circuit diagram of FIG. 3 by comparing the signal flows in the table and the circuit diagram. Now, the input terminal 31-a of this circuit. Let us consider a case where a random binary code string is independently applied to each of the signals 311 and 311b.

First, let the probabilities that the signs of the input terminals 311a and 311b become 1 at each clock time be X, and X2, respectively, as shown in FIG. 4A.
Therefore, what was in state S, changes to state S at the next clock.
, is equal to the probability that the input pattern becomes 11, so it can be seen that X,,X2. Similarly, the probability of transitioning from S, to S2 is 1-X,,X2,S2
It can be seen that the probability of transitioning from S2 to S2 is X,,X2, and the probability of transitioning from S2 to S is 1-x,,X2. Generally, the above can be summarized in a mathematical formula for the case where the number of states is n as follows. First, the state probability vector whose element is the probability Wi of taking the state Si at time t is expressed as the vertical vector W
When t is a transition matrix whose element is the probability Pij of transitioning from state Si to state Sj after one clock, the following equation holds true. Wt+,=PWt
t3} In this way, a system in which the probability of a state is determined by the probability of the state one clock ago is called a Markov system, but if this system satisfies an appropriate condition (I think that the circuit handled in this invention generally satisfies it) ), the initial state W of the system.

It is known that a final state probability distribution W that does not depend on exists as a stationary probability distribution that satisfies the following equation. W
Rani PW ~ [4} In other words, the system will take each state with a certain probability determined by W raw.

This time series always has some state, so Wi=1. Next, the relationship between the state and the probability of output 1 is investigated based on FIG. 4B.

From FIG. 4B, state S. , the output is 1 when the input pattern is 01, 11, so the probability that the input pattern is 01 (1-X.)X2 and the probability that the input pattern is 11 X,
, X2, the output is 1. Further, in the case of S2, since there is no pattern in which the output becomes 1, it can be seen that the probability that the output becomes 1 is 0. In general, when the state Si is, let the output vector whose element is the probability bi that the output becomes 1 be the horizontal vector B, and when the state of the system is a stationary probability distribution W, etc.
The probability Zc that the output is 1 is given as follows. Z
[51Zc is the probability that the output becomes 1 at each clock, so the expected value of the output 1 during N clocks is NZc.

This becomes the expected value of Z in the test circuit. In the same way, the expected values of T,,R,2 can also be found. First, T-cho,
For, when the state is Si, the output is set to 1, and the conditional transition probability matrix Q whose elements are the probability of occurrence qij of an input pattern that causes the state to transition to Sj at the next clock is obtained from Figure 4 A and B. , the probability Tc7 that 1 will appear at the output and 1 will appear again after the ↑ clock is expressed by the following equation. TC Ding・NiBP(71-1)QW et al. If we find the conditional transition probability matrix Ri whose elements are the transition probabilities rij from to state Sj from the state transition table, the probability that the i-th input is 1 and the output after 72 clocks is 1 is Rc2,i. It is given by the following formula: RC D2,
Therefore, the expected value of the mutual correlation R2,i between N clocks is N
It can be seen that Rc72,i.

As described above, all the expected values of the statistics calculated by the statistics calculating section of the digital circuit testing device according to the present invention are calculated based on the stationary probability distribution W, etc., which does not depend on the initial state of the circuit under test. be done. Therefore, when using this testing device, there is no need to specify the initial state of the circuit to be tested, and a complicated procedure for determining the initial state unlike conventional testing devices is unnecessary. This is a great advantage of the digital circuit testing device according to the present invention, and is one of the reasons why the suspension device can be made simple and inexpensive. Next, a specific calculation example will be shown for the circuit under test shown in FIG. 3 according to the above method.

From Figure 4 A and B, B = [X2,0]
It can be seen that (11).

W et al. have the equation W, 1 W2=1
Solving (13), therefore, Zc is, and when 7,=1, Tc is also, for example, when 2=2,i:1, of R becomes.

In the example of the inspection device shown in Fig. 1, the input probabilities X,,X2
are both 1/2, so ZC=ki, Td=point 6, R ground・
The whiteness is (18), and the expected value of the test is obtained by considering the number of test clocks N for each.

In this way, we found that the expected value of the hanging statistics of a normal circuit can be found from the circuit diagram through relatively simple calculations. By simulation of statistics focusing on
These expected values can be found.

Next, using the circuit shown in FIG. 3, it will be specifically explained how these statistics change when there is some kind of failure in the test circuit.

First, assuming that elements 31-3 in Figure 3 are faulty and their output terminal A is always 0 regardless of the input, the transition matrix P and conditional transition matrix Ri of this faulty circuit are normal. The circuit is the same, but the output vector B and conditional transition matrix Q change so that B=[1,0], respectively.
(It becomes 1 go.

From this, using {4} formula '5' formula ■ formula {7} formula,
．． :X2: Calculating ZC, TC・, R ground・ in the case of tails, ZC=Kyo, TCI: Ki, RC2,1: Quantity (2・
), and it can be seen that all three types of statistics are different from Equation (18) in the case of a normal circuit, and that this device can distinguish abnormalities.

Next, let us consider a case where the NOT circuit shown at 31-2 in FIG. 3 has failed and the sign of its output shaft B is always 0.

In this case, B does not change, but P, Q, and R differ from those in a normal circuit as follows. As a result, Zc, Tc
,,Rc2,. When calculating, ZC=ki, TC. =・32
,RC2,. = point (25), and it can be seen that it is different from the case of a normal circuit and can be distinguished.

The above two examples are Zc. Tc,, Rc2, . All of these faults were different from normal circuits, but there are also faults that are detected only by the correlation calculation circuit that is a feature of the present invention.

For example, if the circuit described below is used to determine the failure rates X and X2, then heat and heat, respectively, the expected value of the output statistics when the circuit under test shown in FIG. 3 is normal is expressed by equation (15), ( 16) Equation, (
17) From formula, ZC=harm, Tq=ki, R substance=quantity
(26) However, if the NOT circuit in FIG. 31-2 fails and its output terminal B always outputs 0, the expected value of the statistics for the failed circuit is calculated using the calculation method described above. , ZC = word, Tq = rhombus 5, R thing. = poison (27).

Comparing this with the expected value (26) in the normal case, Zc
, Rc2,1 are equal and only Tc differs.
As described above, there are some faults that cannot be detected by the number of output clocks of 1, but can only be detected by the circuit that calculates the statistical amount representing the correlation, which is a feature of the digital circuit testing apparatus according to the present invention. This kind of example is not recommended if the circuit under test becomes complex.
There will be more. Therefore, it can be seen that the digital circuit testing device according to the present invention has a correlation calculation circuit, thereby greatly improving the reliability of testing. Next, the number N of inspection clocks will be explained. N is an important parameter that determines the reliability of the test. Naturally, if N is increased, the reliability will improve, but here we will discuss the approximate relationship between N and reliability. In the inspection device of the present invention, a random binary code string is added to the input end and the statistical richness of the random pulse train at the output end is observed. Therefore, the binary code string input to the counter for calculating each statistic is , it can be considered that there are random binary code strings that occur with a probability determined by the circuit.

t51 type, '6} type, and '71 type are respectively Z, T-cho,
, R72i, it can be said that this testing device estimates these probabilities by observing them for N clocks and compares them with the case of a normal circuit. Therefore, by allowing for the variance of these estimates, an indication of the reliability of the test can be obtained. For the sake of simplicity, let us consider a case where a binary code string synchronized with a clock with a probability of 1 of Xo and having no temporal correlation is input to the counter. When counting for N clocks, the values taken by the counter will be distributed with a probability given by the binomial distribution of the following equation. UN(1)=NC,F1(1-F)N-1
(28) Here, UN(1) represents the probability that the value of the counter after N clocks is 1.

From the above formula, the average value of 1 and the standardized variance.

When finding the angle, one
(29) 1=NX.

. Heron=X. (1-X.)/N (30). Hence the standard deviation of the estimate. N is. N=JX
. (Taifu) (31), and Fu=1/2
It can be seen that it is maximum when , and decreases in inverse proportion to N. If Xo=1/2 and equation (28) is approximated to a normal distribution, the estimated value will fall within a range of 30N before and after the correct value with a probability of 0.9974. For example, N=10.00
0, when Xo = 1/2, the force that is the skin Fshio) and the inspection clock number female lo・oo. When using this inspection device, if the allowable upper limit value is NXo00N and the allowable lower limit value is NXo00N, the reliability of the faulty circuit that is theoretically different from the normal one in the output statistics is 99.74%. It can be seen from the above that inspection is possible.

In this way, the number N of inspection clocks determines the rigor of the inspection, so if a rough inspection is to be performed over a long distance, N may be made smaller. The above is the principle of this inspection device,
Regarding the modification of the present device derived from the embodiment shown in FIG. 2, points considered to be important will be described below.

First, in the pattern generation section shown at 2 in FIG.
Although the random code string with probability 1'2 outputted from the M-sequence shift register is output as is, the probability of each binary code does not have to be '2, and can be any probability in principle.

Depending on the target circuit, it may be better to shift the occurrence probability from 1'2 to a value close to 1 or 0. FIG. 5 is an example of a random binary code string generator that generates 1 with an arbitrary probability X. In FIG. 5, 5-A is a binary random number generator,
Binary random numbers with a probability of 1/2 are independently outputted to the output terminals 51-1, . . . , 51-r in synchronization with the clock. Therefore, 51-1,.... If the output binary code of 51-r is viewed as a binary digital value R for each clock, it means that all values from 0 to 1 are generated as y-digit digital values with equal probability. 5-C is a switch or resistor, and its output terminal is set to output a y-digit binary digital value corresponding to the desired probability of occurrence x to 53-1, . . . , 53-y.

5-B is a digital comparator, which compares the output random number of the random number generator 5-A with the output setting value X of 5-C every clock,
If X is larger than the random number, the code 1 is output to the output terminal 52, and in other cases, 0 is output.

In this way, the code outputted to the output terminal 52 becomes a binary random code string in which the probability of becoming 1 is X with precision 2-y. Therefore, by placing the device shown in FIG. 5 in the section 2 in FIG. 2 for the number of its output terminals, a pattern with arbitrary probability can be generated, and furthermore, the setting of 51C in FIG. It is also possible to generate more complex test patterns by switching values. As a random value code source with a probability of 1/2, other generators than the M-sequence generator described here may be considered, but the M-sequence is superior in terms of high-speed reproducibility clock, etc. It should be clear from the previous explanation that even if the probability of the pattern generator is set to any value between 0 and 1 instead of 1/2, there will be no change in the calculation method for the output statistics of a normal circuit. .

Furthermore, a modification may be considered in which a correlation is established between input binary code strings for inspection. Next, regarding the statistics calculation section, in the example shown in Figure 2, the test statistics are the frequency of occurrence of 1 in the output Z, the autocorrelation of the output T7, and the correlation between the input and output, which has a clear mathematical meaning. Three types of cross-correlation are selected,
Various modifications of this part can be considered.

For example, even if exclusive OR or matching is used for the logical products 3-4 and 3-7 in FIG. 2, the meaning will hardly change. Furthermore, considering the principle of this inspection device, it can be seen that the characteristics of the inspection device remain unchanged no matter what statistics this statistic calculation section selects as inspection statistics. , In other words, a more general statistics calculation section can be written as shown in FIG. Here, 6-0 is a sequential logic circuit having input terminals 61-1,..., 61-f and output terminals 62-1,..., 62-Z, and 6-1,..., 62-Z as output terminals.・,6-Z
is a counter that counts the number of 1 clocks output from each output terminal of 610. If the output and input of the circuit under test are connected to the input terminals 61-1, . . . , 61-f, the counter 6-1
, ..., 6-Z can be regarded as the test chain statistics determined by the sequential logic circuit 610', and mathematically, they are the higher-order self-values of the input and output of the circuit under test. It is generally expressed as a combination of correlation and cross-correlation. As described above, the basic principle of the testing device according to the present invention is to apply a random binary code string to the circuit under test and test the statistics representing the correlation between the input and output of the circuit under test. The main effects are summarized as follows.

Since only the m statistics are considered, there is no need to store and check all the input/output series as in the past, and it is possible to simplify the size and reduce the production cost and inspection cost of the calendar.

[21] There is no need to significantly change the testing equipment depending on the period of the circuit to be tested.

{31 The reliability of the test depends only on the test time, and there is no need to change the test equipment to improve the reliability.

'41 There is no need to set the initial state of the circuit under test to a specific state. (2) Even when the circuit to be tested is actually used, by regarding the input signal as a random binary code, it becomes possible to perform fault testing during use, which was previously almost impossible.

'61 Since the principle is different from that of conventional testing equipment, a synergistic effect can be expected when using the conventional digital circuit testing equipment and the digital testing equipment of the present invention in parallel.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital style inspection device according to the present invention, FIG. 2 is a block diagram showing the configuration of a specific example of the digital circuit inspection device according to the present invention, and FIG. FIG. 4A is a circuit diagram showing an example of a circuit to be tested for explaining the principle of the digital circuit testing device according to the present invention.
5 is a block diagram showing an example of a circuit that generates a random binary code string with arbitrary probability; FIG. 6 is a block diagram for explaining the statistics calculation section of the digital circuit testing device according to the present invention. 1...Circuit under test, 2...Pattern generation section, 3...Statistics calculation section, 4...Judgment section, 5...・Control unit, 3-A...Output 1
frequency calculation circuit, 3-B...autocorrelation calculation circuit, 3
-C...Cross correlation calculation circuit, 5-1...Time counting circuit, 7...Clock generation section, 3-1,
3-5, 3-8, 6-1, 6-Z...Counter, 6-0
...Sequential logic circuit, S, . S2...Status of the circuit under test. Kul Bacteria Next Z Diagram O 3 Diagram Ota Style Gu' Diagram

Claims (1)

[Claims] 1. A pattern generating section that generates a plurality of random binary code strings to be supplied to a plurality of inputs of a digital circuit to be tested, and a pattern generator that receives an output binary code string supplied from an output of the digital circuit to be tested. a statistics calculation unit that calculates statistics; a determination unit that compares the calculated statistics with statistics obtained when the digital circuit to be tested is normal; and a determination unit that determines whether the digital circuit to be tested is correct; A digital circuit comprising: a control unit that controls the operations of the pattern generation unit, the statistics calculation unit, and the determination unit, and determines whether the digital circuit under test is correct or not based on statistics calculated over a predetermined period. In the testing device, a correlation connected to the statistics calculation unit to at least one of the outputs of the digital circuit to be tested, or to at least one of the outputs of the digital circuit to be tested and to at least one of the outputs of the pattern generation unit. 1. A digital circuit testing device characterized by comprising a correlation calculation circuit for calculating statistics representing . 2. A pattern generator that generates a plurality of random binary code strings to be supplied to a plurality of inputs of the digital circuit under test, and a pattern generating section that receives an output binary code string supplied from the output of the digital circuit under test and calculates statistics. a statistic calculation unit that compares the calculated statistic with a statistic obtained when the digital circuit under test is normal, and determines whether the digital circuit under test is correct; a pattern generation unit; A digital circuit testing device comprising: a control unit that controls the operation of the statistics calculation unit and the determination unit and makes a determination as to whether the digital circuit under test is correct based on the statistics calculated over a predetermined period; The statistics calculation section is provided with a plurality of statistics calculation circuits that calculate a plurality of different statistics, and at least one of these statistics calculation circuits is used to calculate the output of the digital circuit under test. A digital device characterized in that it is a correlation calculation circuit that calculates a statistic representing a correlation connected to at least one output of the digital circuit to be inspected or to at least one output of the pattern generating section. Circuit inspection equipment.