JPS6019175B2 - Clock phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock phase synchronization circuit that can be used in multiplexing PCM signals.

When multiplexing and transmitting PCM signals from multiple systems, it is necessary to synchronize the clock phases of each system.

For this purpose, pulse generators that operate with the clock of each system are provided, and the output pulse phase of each pulse generator is compared, and if they do not match, one of the pulse generators is shifted one bit at a time to generate an output pulse. The phases can be matched. In that case, the configuration shown in FIG. 1 can be considered.
That is, the clocks CLK1 and CLK2 of each system are added to the pulse generators POI and PG2 composed of ring counters, etc., and the output pulses JII of the pulse generators PG1 and PG2 are
The output pulse of a predetermined stage is added to MP to the phase comparator to determine whether the phases of ~gln,g21~sho2n match, and if the phases match, output "1" and shift. The pulse SHP is prevented from being output via the NOR circuit NR2. If the phases do not match, MP outputs "0" to the phase comparator, and the "0" shift pulse SHP is output to the NOR circuit NP2.
, the output of the NOR circuit NP2 becomes “1”
As a result, one bit of the clock CLKI applied to the pulse generator POI via the NOR circuit NPI is blocked. Therefore, a 1-bit shift type phase-locked loop is formed.
However, in the configuration shown in FIG.
output is “0” and the shift pulse SHP is “0” continuously.
”, the output of the NOR circuit NR2 becomes “1” continuously, so the clock CLKI is no longer applied to the pulse generator PGI via the NOR circuit NRI.

That is, the pulse generator PGI will stop operating.
There is a possibility that such shift pulse SHP becomes "0" continuously due to an initial setting failure when the power is turned on. The present invention improves the above-mentioned drawbacks, and its purpose is to automatically trigger when the pulse generator stops operating. Examples will be described in detail below. FIG. 2 is a block diagram of an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.

The OSC is a logical oscillator connected in a 1-bit shift type phase-locked loop, and is composed of, for example, a NOR circuit NR3 and a delay circuit DL. Of course, other configurations may be adopted. Also, mV is an inverter. As mentioned above, when the shift pulse SHP becomes "0" continuously, the logical oscillator LOSC
starts oscillating at a period corresponding to the delay time of the delay circuit DL, and stops oscillating when the shift pulse SHP becomes "1". Further, the delay time of the delay circuit DL is set to be longer than the period of the shift pulse SHP during normal operation so that oscillation does not occur with the normal shift pulse SHP of "0".
When the output of the phase comparator CMP is "0", that is, the phases of the output pulses of the pulse generators PG1 and PG2 do not match, and the shift pulse SHP becomes "0" continuously, the output of the NOR circuit NR2 becomes "1". ” However, the logical oscillator OSC starts oscillating, and the output of the NOR circuit NR2 repeats “1” and “0” according to the oscillation cycle.

Therefore, the clock CLK is intermittently supplied via the NOR circuit NRI.
Since I is applied to the pulse generator PGI, the pulse generator PGI can continue its phase locking action without stopping its operation. FIG. 3 shows a more detailed block diagram of FIG. 2, where the same reference numerals as in FIG. It has a ring counter configuration, and the output pulse JII~◇ln
, J21 to ◇2n, in the phase synchronization state, only one of them is "0" and the other is "1", and they circulate at an n-bit period.

The phase comparator CMP is composed of a circuit NR4 and a flip-flop FFA, and pulse generators PG1 and PG2.
In the embodiment, a case is shown in which the output pulses 01n and J2n of the final stage are compared. Is there an output pulse to the clock terminal CL of the flip-flop FFA/output of the circuit NR4, and an output pulse to the data terminal D? 2n is added, and if the output pulse 2n is "0" and matches the "0" of the output pulse 01n, the flip-flop F
Q terminal of FA becomes “1” and output pulse? 2n is “1”
”, if there is a mismatch, the Q terminal becomes “0”.The phase comparator CMP is configured so that the Q terminal of the flip-flop FFA is forcibly set to “0” when the power is turned on or the clock is turned off. When phase synchronization is not established and the shift pulse SHP is "1", the output of the NOR circuit NR2 becomes "0" and the pulse generator PGI performs a ring counter operation using the clock CLKI.

At this time, the phase comparator CMP outputs pulses 01n, 02n.
If they do not match, "0" is output. When the shift pulse SHP is "0", the NOR circuit NRI inhibits the clock CLKI by one bit and shifts the phase of the pulse generator POI by one bit. By repeating this operation, the output of the phase comparator CM circle becomes "1", that is, the output pulse ◇ln, J
When the phases of 2n match, the output of the NOR circuit NR2 is always "0" and a phase locked loop is established. If logical oscillator DOSC is not provided, shift pulse SH
When P is “0” and the output of the phase comparator CMP is “0”,
The output of NOR circuit NR2 becomes “1”, and NOR circuit NRI
Assuming that the clock CLKI is inhibited and the output pulse ◇1 (n-1) is "0" at this time, the operation of the pulse generator PGI is stopped.

In the present invention, by providing a logical oscillator LOSC, the shift pulse SHP oscillates at a period corresponding to the delay time of the delay circuit DL due to a series of "0"s, and sends "1" and "0" to the NOR circuit NR2. They will be added alternately. For example, if the shift pulse SHP is shown as a in FIG. It oscillates “1” and “0”, and even if the output of MP to the phase comparator is “0” and the shift pulse SHP is “0”, the output of NOR circuit NR2 is the output of logical oscillator LOSC. Since "1" and "0" are repeated by the oscillation output, the continuous inhibition of the clock CLKI by the NOR circuit NRI is eliminated, and the operation of the pulse generator POI is no longer stopped. In addition, if the shift pulse SHP normally becomes "0" with a period of n bits, the output of the logical oscillator LOSC is output from the delay circuit D.
Since the period is "0" which is less than the delay time of L, the output waveform is the same as that of the shift pulse SHP. As explained above, the present invention provides a logical oscillator LOSC in a 1-bit shift type phase-locked loop, and under logical conditions such that the pulse generator stops operating, for example, in the above embodiment, the phase comparator Under the conditions that the CMP output is “0” and the shift pulse SHP is “0”, the logical oscillator LOSC is configured to automatically oscillate, and the oscillation triggers a 1-bit shift type phase-locked loop. Thus, the phase synchronization effect can be continued.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a phase-locked circuit having a 1-bit shift type phase-locked loop, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of a phase-locked circuit having a 1-bit shift type phase-locked loop. A more detailed block diagram, FIG. 4, is an explanatory diagram of the operation of the logical oscillator. PG1 and PG2 are pulse generators, CMm' is a phase comparator, and UOSC is a logical oscillator. Figure 1 2
Figure 4Figure 3

Claims (1)

[Claims] 1. In a 1-bit shift type phase-locked loop that performs phase synchronization using the output pulse of a pulse generator as a shift pulse, the pulse generator automatically oscillates only when the operation of the pulse generator stops under the logical conditions of the phase-locked loop. 1. A clock phase-locked circuit comprising: a logical oscillator for triggering said phase-locked loop.