JPS6019240B2 - Stepping motor drive circuit - Google Patents
Stepping motor drive circuitInfo
- Publication number
- JPS6019240B2 JPS6019240B2 JP21434581A JP21434581A JPS6019240B2 JP S6019240 B2 JPS6019240 B2 JP S6019240B2 JP 21434581 A JP21434581 A JP 21434581A JP 21434581 A JP21434581 A JP 21434581A JP S6019240 B2 JPS6019240 B2 JP S6019240B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- circuit
- stepping motor
- output
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002441 reversible effect Effects 0.000 claims description 39
- 238000004804 winding Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 12
- 230000005284 excitation Effects 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P8/00—Arrangements for controlling dynamo-electric motors rotating step by step
- H02P8/14—Arrangements for controlling speed or speed and torque
- H02P8/20—Arrangements for controlling speed or speed and torque characterised by bidirectional operation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Stepping Motors (AREA)
Description
【発明の詳細な説明】
本発明は、ステッピングモータの正逆転を、乱調等が生
じないように行なわせるステツピングモータ駆動回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stepping motor drive circuit that rotates a stepping motor in forward and reverse directions without causing disturbances or the like.
ステッピングモータを駆動する為の励磁方式としては、
1相−2相,2相一2相,2相−3相等の各種の方式が
知られているが、ステップ動作を行なうものであるから
、本質的に振動を起す要因を含んでいるものである。The excitation method for driving a stepping motor is as follows:
Various methods are known, such as 1-phase-2-phase, 2-phase-2-phase, 2-phase-3-phase, etc., but since they involve step motion, they inherently include factors that cause vibration. be.
従って負荷との共振を生じたり、乱調等の異常現象を生
じる場合がある。又駆動パルス周波数が高い場合の起動
時には、回転子の回転遅れが生じる為に追従できないの
で、安定動作領域から逸脱することがある。これは負荷
トルク、負荷の慣性モーメント等に左右されるが、その
周波数の限界を自起動、停止周波数と称している。又、
ステッピングモータは正逆転駆動される場合が多く、低
速回転中の逆転駆動は殆んど問題はないが、パルス周波
数が高く高速回転中のときの逆転駆動に於いては、前述
の起動時よりも回転子の回転遅れが大きくなることによ
り乱調状態となる。Therefore, resonance with the load may occur or abnormal phenomena such as disturbance may occur. Furthermore, at startup when the drive pulse frequency is high, the rotation of the rotor is delayed and cannot be followed, which may deviate from the stable operating range. This depends on the load torque, moment of inertia of the load, etc., and the limit of this frequency is called the self-starting and stopping frequency. or,
Stepping motors are often driven in forward and reverse directions, and there is almost no problem with reverse drive during low-speed rotation, but when the pulse frequency is high and reverse drive is during high-speed rotation, it is more difficult than when starting up as described above. As the rotation delay of the rotor increases, a state of disturbance occurs.
従って逆転可能周波数は、一般に自起動・健ひ止周波数
の1/2に近い値となるが、その限界を求めるのは実際
には各種の要因により困難である。第1図は従来のステ
ッピングモータ駆動回路の要部ブロック線図であり、A
〜D相巻線を有する4相ステッピングモータ1を2相〜
2相励磁方式夕により駆動する場合についてのものであ
る。各相巻線は駆動増幅器2A〜2Dにより励磁される
もので、CMNは共通端子を示し、例えば接地されるも
のである。パルス分配回路3は、パルス発生器4からの
パルスaを正逆転指令回路5からの正0逆転信号bに基
いて順次分配するもので、例えば正逆転信号bが正転を
示すとき、駆動増幅器2A〜2Dの順次でパルス分配が
行なわれ、ステツピングモータ1の巻線は、A,B相,
B,C相,C,D相,D,A相の組合せ順次で2相−2
相励タ磁が行なわれる。又、正逆転信号bが逆転を示す
ときは、前述と反対の順次で励磁される。正逆転信号b
が、パルス発生器4と同期して出力される同期型と、非
同期で出力される非同期型とがあり、後者の非同期型の
動作を第2図を参照して簡単に説明する。Therefore, the reversible frequency is generally a value close to 1/2 of the self-starting/sustaining frequency, but it is actually difficult to determine its limit due to various factors. FIG. 1 is a block diagram of the main parts of a conventional stepping motor drive circuit, and A
~ 4-phase stepping motor 1 with D-phase winding to 2-phase ~
This is for the case of driving using a two-phase excitation method. Each phase winding is excited by drive amplifiers 2A to 2D, and CMN indicates a common terminal, which is grounded, for example. The pulse distribution circuit 3 sequentially distributes the pulses a from the pulse generator 4 based on the forward/reverse rotation signal b from the forward/reverse command circuit 5. For example, when the forward/reverse signal b indicates forward rotation, the pulse a from the drive amplifier Pulse distribution is performed in the order of 2A to 2D, and the windings of the stepping motor 1 are divided into phases A, B, and
2 phases-2 in the combination of B, C phase, C, D phase, D, A phase
Phase excitation is performed. Further, when the forward/reverse signal b indicates reverse rotation, the magnets are excited in the opposite order to that described above. Forward/reverse signal b
However, there are two types: a synchronous type in which the output is synchronous with the pulse generator 4, and an asynchronous type in which the output is asynchronously.The operation of the latter asynchronous type will be briefly explained with reference to FIG.
同図aをパルス発生器4からの周期Tのパルスa、同図
b′を正逆転指令回路5からの正逆転信号bとし、“0
”を正転,“1”を逆転として示す、駆動増幅器2A〜
2Dの出力は第2図c〜fに示すものとなる。時刻tl
に於いて正逆転信号bが“0”から“1”に反転したと
すると、A相巻線は励磁中で、B相巻線は励磁開始初期
で、第2図dに示すように、↑の時間のみ励磁されるこ
とにより、B相巻線についてみるすくTの如く短時間の
励磁の場合、過渡状態のとき励磁が遮断され、次にD相
巻線の励磁が行なわれので、脱調或は乱調の原因となる
。A in the figure is a pulse a with a period T from the pulse generator 4, b' in the figure is a forward/reverse signal b from the forward/reverse command circuit 5, and "0"
” indicates forward rotation and “1” indicates reverse rotation, drive amplifier 2A~
The 2D output will be as shown in Fig. 2c-f. Time tl
When the forward/reverse signal b is reversed from "0" to "1", the A-phase winding is being energized and the B-phase winding is at the beginning of excitation, as shown in Figure 2d. By being excited only for a time of Or it may cause disturbance.
第3図は同期型の動作説明図で、aはパルス発生器4か
らの周期Tのパルスa、bは正逆転信号b、c〜“ま駆
動増幅器2A〜20の出力を示し、時刻t2に正逆転信
号bが“0”から“1”に反転し、B相巻線は時間Tの
励磁が行なわれるもので、非同期型よりも安定性が改善
されることになる。FIG. 3 is an explanatory diagram of the operation of the synchronous type, where a indicates a pulse a with a period T from the pulse generator 4, b indicates a forward/reverse signal b, and c indicates the output of the drive amplifiers 2A to 20, and at time t2, The forward/reverse signal b is inverted from "0" to "1" and the B-phase winding is excited for a time T, resulting in improved stability compared to the asynchronous type.
しかし、自起動・停止周波数=1′2Tとした場合、前
述の正転から逆転への切換時に於けるTの励磁時間は充
分でなくなり、脱調或は乱調が生じる腐れがある。本発
明は、前述の如き従来の欠点を改善したもので、その目
的は簡単な構成により正逆転駆動を安定に行なわせるこ
とを目的とするものである。However, when the self-start/stop frequency is set to 1'2T, the excitation time of T during the above-mentioned switching from forward rotation to reverse rotation is not sufficient, and there is a possibility that step-out or disturbance occurs. The present invention has been made to improve the conventional drawbacks as described above, and its purpose is to stably perform forward and reverse driving with a simple configuration.
以下実施例について詳細に説明する。第4図は本発明の
実施例のブロック線図であり、第1図と同一符号は同一
部分を示し、6は反転処理回路である。Examples will be described in detail below. FIG. 4 is a block diagram of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts, and 6 is an inversion processing circuit.
この反転処理回路6は、正逆転信号bが“0”から“1
”又は“1”から“0”に反転してステッピングモータ
1の回転方向を反転させるときに、パルス発生器4から
のパルスを一定時間“1”又は“0”のレベルに固定し
、ステッピングモータ1に対しては一定時間停止させた
と同様にするものである。第5図は反転処理回路6の一
実施例のブ。This inversion processing circuit 6 is configured so that the forward/reverse signal b changes from “0” to “1”.
” or “1” to “0” to reverse the rotation direction of the stepping motor 1, the pulses from the pulse generator 4 are fixed at the “1” or “0” level for a certain period of time, and the stepping motor 1 is stopped for a certain period of time.FIG. 5 is a block diagram of one embodiment of the inversion processing circuit 6.
ツク線図であり、パルスaはフリツプフロツブFFIの
クロツク端子Cとアンド回路ANDとに加えられ、フリ
ップフロツプFFIのデータ端子Dには電圧ycが加え
られ、排他的オア回路EXORの出力がリセット端子R
に加えられているので、リセット端子Rが“1”が加え
られると、出力端子Qは“0”となり、アンド回路AN
Dは閉じられる。又アンド回路ANDの出力のパルスa
′はパルス分配回路3に加えられる。正逆転信号bは「
反転処理回路6からそのま)パルス分配回路3へ正逆転
信号b′として加えられらると共にバッファ回路BFを
介して抵抗R3とコンデンサCIとからなる積分回路に
、又排他的オア回路EXORにそれぞれ加えられる。The pulse a is applied to the clock terminal C of the flip-flop FFI and the AND circuit AND, the voltage yc is applied to the data terminal D of the flip-flop FFI, and the output of the exclusive OR circuit EXOR is applied to the reset terminal R.
Therefore, when "1" is added to the reset terminal R, the output terminal Q becomes "0", and the AND circuit AN
D is closed. Also, pulse a of the output of the AND circuit AND
' is added to the pulse distribution circuit 3. The forward/reverse signal b is “
It is directly applied from the inversion processing circuit 6 to the pulse distribution circuit 3 as a forward/reverse signal b', and is also applied via the buffer circuit BF to an integrating circuit consisting of a resistor R3 and a capacitor CI, and to an exclusive OR circuit EXOR, respectively. Added.
積分回路の出力は比較回路COMPに加えられ、電圧V
cを抵抗R1,R2で分圧した値と比較される。第6図
は動作説明図であり、同図aはパルス発生器4からの同
期Tのパルスa、bは正逆転信号bを示し、時刻t3に
正逆転信号bが“0”から“1”になると、その時点で
は比較回路にOMPの出力は“0”であるから排他的オ
ア回路EXORの出力は“1”となって、フリツプフロ
ツプFFIはリセットされる。そしてバッファ回路BF
の出力が積分回路で積分され「 CI,R3の時定数に
対応した時間後に、抵抗R1,R2による分圧電圧以上
に積分出力が増大すると、比較回路COM円の出力は“
1”となり、排他的オア回路EXORの出力“0”とな
る。従って排他的オア回路EXORの出力は第6図cの
71の時間“1”となるから、フリップフロップFFI
の出力端子Qか、第6図dに示すように時間71後のパ
ルスaによってセットされ、出力端子Qが“0”の時間
内の1個のパルスaは禁止され、パルス分配回路3には
第6図eに示すパルスa′が加えられることになる。又
時刻t4に正逆転信号bが“1”から“0”になると、
排他的オア回路EXORの出力は“1”となり、積分回
路の放電時定数に伴なつた時間丁2後に“0”となる。The output of the integrating circuit is added to the comparator circuit COMP, and the voltage V
It is compared with the value obtained by dividing c by resistors R1 and R2. FIG. 6 is an explanatory diagram of the operation, and the figure a shows the synchronized T pulse a from the pulse generator 4, and b shows the forward/reverse signal b. At time t3, the forward/reverse signal b changes from "0" to "1". At that time, since the output of OMP to the comparator circuit is "0", the output of exclusive OR circuit EXOR becomes "1", and flip-flop FFI is reset. and buffer circuit BF
The output of the comparator circuit COM is integrated, and after a time corresponding to the time constant of CI and R3, when the integrated output increases beyond the voltage divided by the resistors R1 and R2, the output of the comparator circuit COM becomes "
1", and the output of the exclusive OR circuit EXOR becomes "0". Therefore, the output of the exclusive OR circuit EXOR becomes "1" at time 71 in FIG.
The output terminal Q of the output terminal Q is set by the pulse a after time 71 as shown in FIG. A pulse a' shown in FIG. 6e will be applied. Also, when the forward/reverse signal b changes from "1" to "0" at time t4,
The output of the exclusive OR circuit EXOR becomes "1" and becomes "0" after a time interval of 2, which is associated with the discharging time constant of the integrating circuit.
従ってフリップフ。ツプFFIの出力端子Qは“0”に
なった後に時間?2のパルスaによりセットされて“1
”となりも1個のパルスaが禁止されたパルスa′がパ
ルス分配回路3に加えられる。第6図eに示すパルスa
′がパルス分配回路3に加えられることにより、駆動増
幅器2A〜2Dの出力は第6図f〜jに示すものとなり
、非同期型であっても、少なくともかのパルス幅でステ
ッピングモーターの各相巻線が励磁されるので、脱議或
は乱調が生じることはない。Hence Flipf. Is it time after the output terminal Q of the FFI becomes “0”? It is set by pulse a of 2 and becomes “1”.
"A pulse a' with one pulse a inhibited next to it is applied to the pulse distribution circuit 3. The pulse a shown in FIG.
' is applied to the pulse distribution circuit 3, the outputs of the drive amplifiers 2A to 2D become as shown in FIG. Since the line is energized, no decoupling or disturbances occur.
前述の実施例は正逆転切襖時に積分回路の時定数の設定
によって、1個のパルスを禁止する場合についてのもの
であるが、2個以上のパルスを禁止するように時間71
,ヶ2を設定することもできる。The above embodiment deals with the case where one pulse is inhibited by setting the time constant of the integrating circuit during forward/reverse switching.
, 2 can also be set.
又?1=丁2或はィキ↑2に設定することもできる。積
分回路及び比較回路COMPは、正逆転信号bの反転か
ら所定の時間、パルスaの出力を禁止する為のものであ
るから、正逆転信号bの反転でトリガされる単安定マル
チパイプレータを用いることもできる。第7図は反転処
理回路6の他の実施例のブロック線図を示し、第5図と
同一符号は同一部分を示し、ORはオア回路、FF2は
フリツプフロツプである。or? It can also be set to 1 = 2 or 2. Since the integration circuit and the comparison circuit COMP are for inhibiting the output of the pulse a for a predetermined period of time after the reversal of the forward/reverse signal b, a monostable multipipelator that is triggered by the reversal of the forward/reverse signal b is used. You can also do that. FIG. 7 shows a block diagram of another embodiment of the inversion processing circuit 6, in which the same symbols as in FIG. 5 indicate the same parts, OR is an OR circuit, and FF2 is a flip-flop.
比較回路COMPの出力をパルス分配回路3に加える正
逆転信号b′とし、フリツプフロツプFF2のデータ端
子Dに排他的オア回礎EXORの出力を加え、フリツプ
フロツプFF2の出力端子Qの出力をオア回路PRを介
してパルスaと共にパルス分配回路3に加えるパルスa
′とするものである。第8図は動作説明図であり、aは
パルスa、bは正逆転信号bを示し、反転処理回路の出
力のパルスa′は同図f、正逆転信号b′は同図cに示
すものとなる。The output of the comparison circuit COMP is used as the forward/reverse signal b' to be applied to the pulse distribution circuit 3, the output of the exclusive OR circuit EXOR is applied to the data terminal D of the flip-flop FF2, and the output of the output terminal Q of the flip-flop FF2 is applied to the OR circuit PR. Pulse a is applied to pulse distribution circuit 3 together with pulse a through
'. FIG. 8 is an explanatory diagram of the operation, where a shows the pulse a, b shows the forward/reverse signal b, the pulse a' output from the inversion processing circuit is shown in the figure f, and the forward/reverse signal b' is shown in the figure c. becomes.
又同図dは排他的オア回路EXORの出力、同図eはフ
リップフロップFF2の出力端子Qの出力を示す。従っ
て正逆転信号b′は73及び74の遅れを生じ、パルス
をは2パルス間を‘‘1”に保持したもとなる。又同図
g〜jはパルスa′及び正逆転信号b′によりパルス分
配回路3が動作し、駆動増幅器2A〜2Dから出力を示
し、この実施例に於いても、反転動作時に少なくともか
の時間の励弱が確保されることになる。以上説明したよ
うに、本発明は、正逆転信号bの反転時に、同期Tのパ
ルスaを少なくとも1パルス分“0”又は“1”に保持
してパルス分配回路3に加える反転処理回路6を設ける
ことにより、同期型は勿論、非同期型であっても、パル
スaに同期したnT(n=2以上の整数)の時間、ステ
ッピングモータ1の巻線の励磁を継続することができる
ので、自起動・停止周波数でステッピングモータを駆動
している状態で回転方向を反転させても、応答良く追従
することができ、脱調或は乱調を生じることがなくなる
。Further, d in the same figure shows the output of the exclusive OR circuit EXOR, and e in the same figure shows the output of the output terminal Q of the flip-flop FF2. Therefore, the forward/reverse signal b' is delayed by 73 and 74, and the pulse is held at ``1'' between the two pulses.Also, g to j in the same figure are caused by the pulse a' and the forward/reverse signal b'. The pulse distribution circuit 3 operates and outputs are shown from the drive amplifiers 2A to 2D, and in this embodiment as well, excitation/weakness for at least some time is ensured during the inversion operation.As explained above, The present invention provides a synchronous type by providing an inversion processing circuit 6 that holds the pulse a of the synchronous T at "0" or "1" for at least one pulse and applies it to the pulse distribution circuit 3 when the forward/reverse signal b is inverted. Of course, even if it is an asynchronous type, the winding of the stepping motor 1 can continue to be excited for a period of nT (n = an integer of 2 or more) synchronized with pulse a, so stepping at the self-start/stop frequency is possible. Even if the rotation direction is reversed while the motor is being driven, it can be followed with good response, and no synchronization or disturbance will occur.
なお前述の実施例か4相ステッピングモータを2相−2
相励磁方式で励磁する場合についてのものであるが、5
相,6相等の多相巻線を有するステッピングモータにつ
いても適用することができ、又1相−2相,2相−3相
等の励磁方式に対しても適用することができる。In addition, in the above-mentioned embodiment, the 4-phase stepping motor is replaced with 2-phase-2
This is for the case of excitation using the phase excitation method, but 5
The present invention can also be applied to stepping motors having polyphase windings such as 1-phase and 6-phase windings, and can also be applied to excitation systems such as 1-phase-2-phase and 2-phase-3-phase.
第1図は従来のステッピングモータの駆動回路のブロッ
ク線図、第2図及び第3図は従来の非同期型及び同期型
の動作説明図、第4図は本発明の実施例のブロック線図
、第5図及び第7図は反転処理回路のそれぞれ異なる実
施例のブロック線図、第6図及び第8図は、第5図及び
第7図のそれぞれ動作説明図である。
1はステッピングモ−夕、2A〜2Dは駆動増幅器、3
はパルス分配回路、4はパルス発生器、5は正逆転指令
回路、6は反転信理回路である。
第1図第2図
第3図
第4図
第5図
第6図
第7図
第8図FIG. 1 is a block diagram of a conventional stepping motor drive circuit, FIGS. 2 and 3 are operation explanatory diagrams of conventional asynchronous and synchronous types, and FIG. 4 is a block diagram of an embodiment of the present invention. FIGS. 5 and 7 are block diagrams of different embodiments of the inversion processing circuit, and FIGS. 6 and 8 are operation explanatory diagrams of FIGS. 5 and 7, respectively. 1 is a stepping motor, 2A to 2D are drive amplifiers, 3
4 is a pulse distribution circuit, 4 is a pulse generator, 5 is a forward/reverse command circuit, and 6 is an inversion belief circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
た順次でパルス分配を行なうパルス分配回路を備え、該
パルス分配回路の出力に従つて複数相巻線を有するステ
ツピングモータの各相巻線を励磁し、前記正逆転信号で
指定された回転方向に前記ステツピングモータを駆動す
るステツピングモータの駆動回路に於いて、前記正逆転
信号の反転時に前記所定の周期のパルスを少なくとも1
パルス分強制的に“0”又は“1”に保持して前記パル
ス分配回路に加える反転処理回路を設けたことを特徴と
するステツピングモータ駆動回路。1. Each phase winding of a stepping motor having multiple phase windings is equipped with a pulse distribution circuit to which pulses of a predetermined period are applied and the pulses are distributed sequentially according to a forward/reverse signal, and according to the output of the pulse distribution circuit, each phase winding is In a stepping motor drive circuit that excites a line and drives the stepping motor in the rotational direction specified by the forward/reverse signal, the stepper motor is configured to generate at least one pulse of the predetermined period when the forward/reverse signal is reversed.
A stepping motor drive circuit comprising an inversion processing circuit that forcibly holds a pulse at "0" or "1" and adds it to the pulse distribution circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21434581A JPS6019240B2 (en) | 1981-12-28 | 1981-12-28 | Stepping motor drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21434581A JPS6019240B2 (en) | 1981-12-28 | 1981-12-28 | Stepping motor drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58116099A JPS58116099A (en) | 1983-07-11 |
| JPS6019240B2 true JPS6019240B2 (en) | 1985-05-15 |
Family
ID=16654219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21434581A Expired JPS6019240B2 (en) | 1981-12-28 | 1981-12-28 | Stepping motor drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6019240B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2621633B2 (en) * | 1990-10-17 | 1997-06-18 | 日本電気株式会社 | Stepping motor control circuit |
-
1981
- 1981-12-28 JP JP21434581A patent/JPS6019240B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58116099A (en) | 1983-07-11 |
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