JPS6019527B2 - auto clear circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to an auto clear circuit.

In digital control circuits such as electronic desktop calculators,
The auto clear circuit includes various memory circuits such as flip-flop circuits, and automatically sets these memory circuits to initial values when the power is turned on.

This auto-clear circuit inverts the clear signal formed with the rise of the power supply voltage by the output of a pulse counting circuit that receives a predetermined timing pulse, such as a word pulse, formed based on the oscillation output of an oscillation circuit. , it is conceivable to cancel the clearing.

In CR type oscillation circuits, an abnormal oscillation phenomenon occurs in which the oscillation frequency increases when the power supply voltage is below the stable operating voltage of the oscillation circuit, so when the power supply voltage rises slowly, this abnormal oscillation period becomes longer.

In addition, crystal oscillator circuits have an overtone (overtone) that oscillates at harmonics of the natural frequency when the power is turned on.
(ne) Oscillation may occur. Since the above-mentioned timing pulse is formed based on these harmonic oscillation outputs, the clear release operation is performed at an early timing.As a result, in the auto clear circuit of the above method, the clear It has been found that there is a problem in that the operation is not performed reliably. The present invention was made in order to provide an auto-clear circuit that can perform a reliable clearing operation that is not affected by abnormal oscillation operations in an oscillation circuit.

In one embodiment of the present invention, it is detected that the oscillation output of the oscillation circuit has a predetermined stable oscillation frequency, and based on this detection output, a pulse counting operation for clearing release operation is performed. It is something.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

o l is an oscillation circuit, which is an example of a crystal oscillation circuit using a crystal resonator x.

This circuit is an inverter circuit NO. ,
Bias resistance Ro, crystal oscillator x and capacitor CO.
,C. 2 and an inverter circuit No. 2 which serves as a waveform shaping circuit.

2 is a frequency detection circuit, which is a p-channel controlled by Co3 of the CR integration circuit R which inputs the output of the oscillation circuit 1, an inverter circuit No 3 which inputs this integral output A, and this inverter output B. MISFET (Insulated Gate Field Effect Transistor Q,) and this skin SFE
The capacitor Co4 is charged through the capacitor TQ and the capacitor Co4.

Inverter circuit No.4 inputs the output of this capacitor Co4, and NAN controlled by this inverter output A.
The A gate circuit controls the transmission of the oscillation output OSC to the frequency dividing circuit 3. The frequency dividing circuit 3 is, for example, 2
The timing pulse generation circuit 4 is constructed of a ring counter circuit or the like that receives the clock pulses as input.
It forms various timing pulses such as bit pulses, digit pulses, and word pulses. 5a, 5
b, 5b' are pulse counting circuits for forming the clear signal ACL.

This embodiment circuit is composed of a complementary MIS logic circuit (C-MIS) composed of a combination of a p-channel MISFET and an n-channel MISFET. with an arrow pointing in the opposite direction to the electrode, e.g.
MISFETQ,. , Q, 3, etc. are p-channel MISF
ET with an arrow pointing toward the gate electrode in the channel region, for example, MISFETQ, 2, Q
, 4, etc. are n-channel MISFETs. Of each circuit 5a, 5b, 5b' that constitutes the pulse counting circuit 5,
Since circuits 5b and 5b' are the same circuit, 5b' is omitted.

The difference between the first stage circuit 5a and the next stage circuit 5b is that the MISFET Q2o in the circuit 5b is 5
It's just not in circuit a. Since this MISFETQ2o is controlled by the output of the previous stage circuit,
It is unnecessary for the first stage circuit 5a.

3 first stage circuit 5a is MISF
ETQ,. and a series circuit consisting of a capacitor C, and a MISFET Q,4 whose input is the output of this capacitor C.
A circuit consisting of parallel MISFETs Q, 5, Q, 6 connected in series, a depletion type MISFET Q, 3 as a load of this logic block, and a MISFET Q, 7 whose input is the output of this logic circuit. ,Q,8
and an inverter circuit composed of the M1sFETQ, . is the inverted signal ◇W of the timing pulse to be counted, and MISFETQ, 5 of the logic circuit is
The output of the output inverter circuit is applied to the timing pulses W to be counted and the skin SFETs Q and 6, respectively. Note that the enhancement type skin SFET Q,2 provided between the output of the series circuit and the power supply voltage terminal is for discharging the capacitor C, when the power is cut off.
It is desirable to provide the same MISFET between the outputs of the output inverter circuits Q, 7, Q, and 6 and the power supply voltage terminals (not shown).

The second stage circuit 5b includes a MISFET Q2 controlled by the output E of the previous stage in a series circuit.

is the series circuit Q2. , Q2, , C2, and the rest is the same as the first stage circuit, so the explanation thereof will be omitted. Since the output stage 5b'' is the same as this circuit 5b, the specific circuit and its explanation will be omitted. Next, with reference to the operating waveform diagram shown in FIG.
Explain the operation of the gate circuit and the gate circuit.Due to abnormal oscillation when the power is turned on, the integral output A when the oscillation frequency is high will not exceed the logic threshold voltage VT of inverter circuit No. 3 because the charging period is shortened. It simply repeats charging and discharging without rising.

In other words, the time constant of the tantalum integrator circuit is set in this way. On the other hand, even if the time constant is the same as in the above case, the integral output A due to the stable oscillation frequency has a longer charging period, so there is a period in which the logic threshold voltage VT of inverter circuit No. 3 is exceeded, and the output B is inverted and the MISFET false ，
This will turn on the . This allows capacitor Co4
is charged, increases its charge level, and controls the opening of the gate circuit. From this point on, the oscillation output OSC is transmitted to the frequency dividing circuit 3, and a frequency dividing operation and a timing pulse generation operation are performed. On the other hand, as shown in the operating waveform diagram of FIG.
5c sets its output to low level when the power is turned on.

In other words, the load of the logic circuit in each circuit is the depression type MISFET Q, 3, Q prisoner...
...and the series circuit capacitors C,,C
2...........MISFET to which the output is applied
This is because since Q, 4, Q24, . . . are off, the / . level is input to the output inverter circuit. A clearing operation is performed by using the output of this final stage circuit 5b' as an auto clear signal ACL. However, it goes without saying that this clearing operation is executed from the time when the power supply voltage V reaches the lower limit voltage for operation of various memory circuits. Then, the frequency detection circuit 2 opens the gate circuit and the timing pulse generation circuit 4 operates, and the first arriving word pulse JW causes the MISFETQ, . is turned on, capacitor C, is charged up, and MISFETQ,
4 turns on.

At this time, since the MISFETs Q and 5 are off, the inputs of the output inverter circuits Q, 7, Q, and 8 remain at high level. When the word pulse Jw changes to high level "0" and MISFET Q,5 is turned on, that is, the inputs of the output inverter circuits Q, 7, Q, 8 change to low level due to the back edge of the word pulse. , its output E changes to /·i level. Once the output E of this inverter circuit becomes high level, the MISFETs Q and 6 of the logic circuit on the input side are turned on.
The output E of the first stage circuit 5a maintains the /.I level regardless of whether Q and Q5 are on/off. By changing the output E of the first stage circuit 5a to the /.i level, the MISFE of the next stage
TQ2o teaches. Therefore, with the arrival of the next word pulse generator W, the capacitor C2 of the next stage circuit is charged up, and at the back edge of this pulse generator W,
The output F of this circuit 5b changes to high level. The final stage circuit 5b' is similarly inverted by the third word pulse OW, and its output ACL is set to the /.-- level, thereby being cleared. According to this embodiment circuit, the timing pulse is formed by the oscillation output after the oscillation circuit has stably operated, and clearing is performed. Therefore, the time necessary for the clearing operation can be secured. Malfunctions as described above are prevented.

The present invention is not limited to the embodiments described above, and, for example, the output of the frequency detection circuit may be used to control the transmission of the output of the frequency dividing circuit or the timing pulse generation circuit instead of the output of the oscillation circuit.

Alternatively, MISFETQ, . The counter operation may be directly controlled by providing a series skin SFET and controlling this. 5 Furthermore, the pulse counting circuit may be of any type.

However, the circuit can be simplified if the clear signal can be generated by the output of the counter circuit itself, as in the circuit of the embodiment. Furthermore, although the frequency detection circuit can use a low-pass filter 0 or the like, it is preferable to use elements that can be built into a monolithic integrated circuit.

The oscillation circuit can be applied to any type of oscillation circuit, such as a CR type oscillation circuit or a crystal oscillation circuit, which tends to oscillate abnormally at a high frequency when the power is turned on. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are operational waveform diagrams thereof.

1... Oscillation circuit, 2... Frequency detection circuit, 3... Frequency dividing circuit, 4... Timing pulse generation circuit, 05a to 5b'... ...Pulse counting circuit.

Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 An auto-clear circuit that releases a clear signal formed at the rise of the power supply voltage by the output of a counting circuit that receives a predetermined timing pulse formed based on the output signal of a timing pulse forming circuit. An auto clear circuit characterized in that it is provided with a detection circuit that detects that the output signal of the timing pulse forming circuit has a predetermined frequency, and causes the counting circuit to perform a counting operation based on this detection output. .