JPS6019595B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device that uses complementary insulated gate field effect transistors (hereinafter referred to as CMOS transistors) and achieves low power consumption.

In general, memory devices using CMOS transistors are characterized by low power consumption and wide operating margins.
In order to compensate for the shortcomings of volatile memory, it has established itself as a backup memory with low power supply voltage.

However, when configuring a system using this memory device, as the memory capacity expands, the CM
At present, if an attempt is made to achieve sufficient reduction in power consumption in an OS memory, external troublesomeness inevitably accompanies it. FIG. 1 shows a typical example of a memory system having a matrix configuration of m rows and Xn columns.

In FIG. 1, an input signal A such as an address input is commonly connected to all memory devices M, and a memory device selection signal CS is commonly supplied to each column. That is, the selection signal CS, is the memory device M.・、
From M. Similarly, the selection signal CSm is input to memory devices Mm., to Mm.n.
Further, the output signal line D is commonly connected to each row, that is, the output signal line D is connected to the memory device M.・、From Mm・
, and similarly, the output signal line Dn is connected to the memory device M.・n・ is connected to Mm・n.

Now, in the memory system shown in FIG.
If up to n are selected and memory devices in other columns are in a non-selected state, only the selection signal CS2 becomes low level and the other selection signals become high level.

At this time, an input signal A such as an address input is commonly supplied to all memory devices M, and an attempt is made to drive the input circuit of each memory device, but the memory output that is in a non-selected state becomes a floating state. Information on the selected memory device locations . . . . to M2.n is output to the output signal lines D, to Dm.

FIG. 2 shows the first stage of a conventional CMOS input circuit used in each memory device M of the memory system shown in FIG.

This FIG. 2 shows a CMOS basic inverter consisting of a P-channel transistor QI and an N-channel transistor Q2, which are individually prepared for each input terminal of the memory device M. Power supply voltage VI is applied to the source of transistor QI, and the source of transistor Q2 is grounded.

The gates of the two transistors Q1 and Q2 are coupled together so that the input signal A is supplied to the input point PI through the input signal line. Also, transistor Q1
, Q2 are also coupled to form an output point P2 for the internal circuits after the first stage. Here, the threshold value of the P-channel transistor QI is VTP, the threshold value of the N-channel transistor Q2 is VTN,
The input voltage at input point PI is VTN, and the output voltage at output point P2 is V. Assuming UT, the power supply current 1 consumed in the input circuit in Fig. 2 is the minimum (i.e., 0 excluding leakage).
) is the condition for transistor QI or Q2 to be cut off: V...>V, -VTp or V,N<
VTN...denoted by (1}.

In addition, when the input circuit requires logic conversion at the TTL level, the high level of the input signal is V...>2.0V, and the low level is V,N<0.8V, and the output voltage V at the output point P2 .

The B ratio (current amplification factor ratio) of transistors Q1 and Q2 must be set so that the UT guarantees the logic level of the internal signal from the next stage. The logic amplitude of the TTL level is extremely narrow compared to the condition of the above formula {1},
Worst case of input level, e.g. VTN=2.0V
Or, when V, N = 0.8V, as a matter of course, a power supply current 1 flows through the input circuit in FIG.

Now, a memory device M having an input circuit similar to that shown in FIG. level, or from low level to high level, when the input signal A changes, that is, the input voltages V and N are VTN<VIN<V
While in I-VTP, power supply current 1 flows through the input circuit,
Despite the non-selected state, the advantage of low power consumption, which is a feature of CMOS memory, is lost.

On the other hand, when backing up the stored information of a memory device M having an input circuit similar to that shown in FIG. ~3V), but at this time,
If the input point PI to which the input signal A is supplied is in a floating state and does not satisfy the condition of formula '1}, both transistors QI and Q2 are conductive, and power supply current 1 flows through the input circuit. A large negative voltage is applied to the voltage source that backs up the memory device M.

Therefore, during backup at low supply voltage,
The input points PI of all the input circuits of the memory device M must be forcibly fixed to a high level or a low level so that the condition of Equation 11 is satisfied.

As a result, the conventional basic CMO as shown in Figure 2
In a memory device with an S input circuit, when other memory devices are being driven, even when the memory is not selected, current consumption in the input circuit cannot be avoided. When attempting to back up stored information, in order to achieve a sufficiently low power consumption, each input device of the memory device must be controlled by an external peripheral circuit, which causes trouble in use.

Next, FIGS. 3a and 3b show the conventional improved CM
The OS input circuit is shown.

In both FIG. 3a and FIG. 3b, the input circuit section 1 (or 1') is controlled by the control signal c (or ?c).
and a CS input circuit section 2 (or 2') for generating a control signal Jc (or Jc) from the selection signal CS of the memory device M. Of these, Figure 3a
In the case of , the input circuit section 1 is configured by a NAND circuit of input signal A and control bond gc, and transistors QII to QI4 are used, and transistors QII and Q
13 is a P channel transistor, transistor Q
12 and Q14 are N-channel transistors.

The gates of transistors QII and Q12 are coupled together,
The connection point serves as an input point PII, and the input signal A is inputted through the signal input line.

Further, the gates of transistors Q13 and Q14 are also coupled together, and a control signal ◇o is input to the joint point. The sources of transistors QII and Q13 are coupled to each other so that power supply voltage VI is applied thereto.

Further, the drains of the transistors QII and Q13 are also coupled together, and together with the drain of the transistor Q14, serve as an output point P12 to the next stage. The source of transistor Q12 is grounded, and its drain is connected to the source of transistor Q14. On the other hand, the CS input circuit section 2 has P
The inverter includes a channel transistor Q15 and an N-channel transistor Q16, and the source of the transistor Q15 is applied with the power supply voltage V1, and the source of the transistor Q16 is grounded.

The selection signal CS of the memory device M is input to the gates of the two transistors Q15 and Q16, and the drains are connected to each other, and the control signal ? It is designed to output c. Now, if the memory device M having the input circuit shown in FIG. Become.

Therefore, in the input circuit section 1, the P-channel transistor Q13 is non-conductive, and the N-channel transistor Q14 is conductive.If the input signal A is at a high level, the inverter circuit consisting of transistors QII and Q12 will cause The output point P12 becomes a low level. Furthermore, if the input signal A is at a low level, the output point P12 becomes a high level, and the input circuit 1 outputs a signal that is an inversion of the input signal A. On the other hand, if this memory device M is in a non-selected state, that is, the selection signal CS is at a high level, the control signal Gc from the CS input circuit section 2 is at a low level.

As a result, in the input circuit section 1, the P-channel transistor Q13 becomes conductive, the N-channel transistor Q14 becomes non-conductive, and the output point P2 shows a high level regardless of the voltage level of the input signal A. At this time,
Since the transistor Q14 is non-conductive, the power supply current 1 does not flow in the input circuit section 1, and the power consumption becomes 0.

On the other hand, in the case of FIG. 3b, the input circuit section 1' is constituted by a NOR circuit of the input signal A and the control signal Jc.
It is composed of transistors Q21 to Q24, transistors Q21 and Q23 are P-channel transistors, and transistors Q22 and Q24 are N-channel transistors.

The driving method of the input circuit is exactly the same as that in Figure 3a, but since the circuit is configured in a NOR system, the CS input circuit section 2' for the control signal c is a P-channel transistor Q25. It is constituted by a two-stage inverter circuit consisting of Q27 and N-channel transistors Q26 and Q28.

Now, suppose that the memory device M having the input circuit shown in FIG. transistor Q23 is conductive and N
Channel transistor Q24 becomes non-conducting,
An inverter circuit including transistors Q21 and Q22 causes the output point P22 to invert the input signal A and indicate the output state.

On the other hand, if this memory device M is in a non-selected state and the selection signal CS is at a high level, the control signal Mac is also at a high level, the P-channel transistor Q23 is non-conductive, and the N-channel transistor Q23 is non-conductive. Q24 is conductive, and output point P22 shows a low level regardless of the voltage level of input signal A.

At this time, since the transistor Q23 is non-conductive, the power supply current 1 does not flow in this input circuit section 1', and the power consumption becomes 0.

Therefore, the conventional improved input circuit shown in FIGS. 3a and 3b can reduce power consumption to zero in the input circuit section when the memory device is not selected.

By the way, in general, one CS input circuit section 2 (or two
Since it is possible to control a plurality of input circuit units 1 (or 1') using the input circuit 1'), it is possible to significantly reduce power consumption.

However, even with this conventional improved input circuit, when attempting to back up stored information at a low power supply voltage, the input signal (here, the selection signal CS)
is in a state such as floaty sog, and the '1' mentioned above
}If the condition of the formula is not satisfied, the CS input circuit section 2 (
or 2'), the power supply current flows.

In addition, sometimes the control signal mec (or guc) may also be at an intermediate level, and in this case, the input circuit section 1
(or 1') also flows a large amount of current.

Therefore, in order to achieve low power consumption, the input terminal (here, the selection signal) of the memory device must be forcibly controlled to a non-selected state by an external peripheral circuit.

This invention was made to eliminate the above-mentioned conventional drawbacks, and minimizes power consumption without depending on input signal levels such as addresses when memory is not selected.
In addition, power consumption can be minimized regardless of the input signal level even when backing up stored information with a low power supply voltage, and there is no need for an external peripheral circuit for the input terminal, and when the memory is not selected or the power supply voltage is low. An object of the present invention is to provide an easy-to-use semiconductor memory device that can achieve sufficiently low power consumption during backup.

Embodiments of the semiconductor memory device of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram of one embodiment. FIG. 4 shows the signal input circuit 11 controlled by the control signal ◇c generated from the selection signal CS for the memory device M, and the control voltage V
2 (hereinafter referred to as a signal input circuit) 12, and a power supply potential detection circuit 113 built into the memory device M that outputs a control voltage V2. First, the configuration of the signal input circuit 11 will be described.

This signal input circuit 11 receives input signal A and control signal? It is configured by a NAND circuit with transistor Q3.
1 to Q34. Transistor Q31
and Q33 are P-channel transistors, and transistors Q32 and Q34 are N-channel transistors. The gates of transistors Q31 and Q32 are coupled, and input signal A is introduced through the signal input line using the coupling point as input point P31.
Furthermore, the gates of transistors Q33 and Q34 are coupled to each other, and a control signal gc is introduced thereto. The sources of transistors Q31 and Q33 are coupled and connected to the power supply voltage V
I is applied.

The drains of this transistor Q31 and Q33 are also connected together, and together with the drain of the transistor Q34, it becomes an output point P32 to the next stage. And transistor Q3
The source of transistor Q34 is grounded, and its drain is connected to the source of transistor Q34. On the other hand, the signal input circuit 12 is constituted by a NOR circuit of the memory selection signal CS and the control voltage V2, and includes transistors Q37 and Q35.
is a P channel transistor, transistor Q36, Q
38 is an N-channel transistor.

A selection signal C is applied to the gates of transistors Q35 and Q36.
S is input, and a control voltage V2 is applied to the gates of transistors Q37 and Q38.

The power supply voltage VI is 0 at the source of the transistor Q37.
Its drain is connected to the source of transistor Q35. The sources of transistors Q36 and Q38 are coupled together and grounded, and the drains of transistors Q36 and Q38 are coupled together to receive the control signal ? It is designed to output c. Further, the power supply potential detection circuit 13 is for monitoring the level of the power supply voltage VI and outputting a control voltage V2, and is composed of transistors Q39 to Q43 and load resistors R1 and R2. Transistors Q39 to Q42 are all N
Channel transistor, transistor Q39
A power supply voltage VI is applied to the drain of the circuit through a load resistor RI. The source of transistor Q39 is grounded. Further, the connection point between the drain of the transistor Q39 and the load resistor RI is configured to output a control voltage V2.

Transistor Q40 has its drain and gate coupled, and is configured to be supplied with power supply voltage VI. Transistor Q41 connects the drain and gate, and transistor Q4
0 source. The drain and gate of transistor Q42 are connected to each other and the source of transistor Q41. The source of transistor Q42 is grounded through load resistor R2, and its node P34 is connected to the gate of transistor Q39, which is a driver transistor in the next stage.

Note that, in order to reduce the power consumption of the power supply potential detection circuit 13, it is desirable that the load resistors R1 and R2 have a high resistance of about several MQ.

This can be easily produced using high-resistance polysilicon production technology using ion implantation, which has been widely used recently. Next, the operation of the semiconductor memory device of the present invention configured as described above will be explained.

Now, when the memory device M having the circuit shown in FIG. 4 is in a normal state and the power supply voltage VI is at a high level, the potential of the node P34 level-shifted by the transistors Q40 to Q42 is shifted to that of the transistor Q39. becomes higher than the threshold voltage. As a result, the transistor Q39 becomes conductive, and the control voltage V2 becomes a low level, that is, a ground level. At this time, the P-channel transistor Q37 in the signal input circuit 12 becomes conductive, and the N-channel transistor Q38 becomes non-conductive, so the transistors Q35 and Q
The control signal Jc, which is the inverter output from 36, outputs an inverted level to the selection signal line of the memory chip that transfers the memory selection signal CS.

If the memory device M is selected and the selection signal CS is at a low level, the control signal Jc is at a high level, and the P-channel transistor Q33 in the signal input circuit 11
is non-conductive, N-channel transistor Q34 is conductive, and an output having an inverted level of input signal A appears at output point 32, which is an inverter output formed by transistors Q31 and Q32.

If memory device M is in a non-selected state and selection signal C
If S is at a high level, is it a control signal? c becomes a low level, the P-channel transistor Q33 in the signal input circuit 11 becomes conductive, and the N-channel transistor Q3 becomes conductive.
4 becomes non-conductive, and the output point P2 becomes high level regardless of the input signal A.

At this time, since the transistor Q34 is non-conductive, the power consumption in the signal input circuit 11 is zero.

On the other hand, when the memory device M having the circuit shown in FIG. 4 enters the storage information retention mode and the power supply voltage VI becomes a low power supply voltage level, the potential at the node P34, which is level-shifted by the transistors Q40 to Q42, reaches the threshold of the transistor Q39. However, the value will be lower than the voltage.

As a result, transistor Q39 becomes non-conductive, and control voltage V2 becomes high level, that is, the same level as power supply voltage VI. Therefore, the P-channel transistor Q37 in the signal input circuit 12 is non-conductive, and the N-channel transistor Q38 is conductive.

Therefore, the control signal ◇c becomes low level regardless of the memory selection signal CS. As a result, the P-channel transistor Q33 in the signal input circuit 11 becomes conductive, the N-channel transistor Q34 becomes non-conductive, and the output point P32 becomes high level regardless of the input signal A.

At this time, transistor Q34 and transistor Q3
Since both circuits 7 are non-conductive, power supply current 1 does not flow through both signal input circuits 11 and 12, and power consumption is minimized.

As explained above, the memory device having the circuit shown in FIG. 4 includes the power supply potential detection circuit 13 that can control the signal input circuit according to the level of the memory power supply voltage VI. Therefore, when backing up stored information using a low power supply voltage, power consumption can be minimized without being affected by the input level of the memory selection signal CS or the input signal A.

Further, even in normal use, it is possible to achieve low power consumption in the input circuit without being affected by changes in the input signal level when the memory IJ is not selected.

This greatly simplifies the system clock that handles the memory device, and also realizes the advantage of low power consumption of CMOS memory through external control. Generally, switching of the power supply voltage to the storage information mode and returning to the normal operation mode occurs instantaneously, but the change follows a gentle curve due to the stray capacitance of the power supply line on the system.

In the embodiment shown in FIG. 4, the followability of the control voltage V2 to the power supply voltage VI is very good, and even when returning to the normal operation mode, it is sufficient to allow for several seconds.

Note that the present invention can be applied not only to memory devices but also to all logical BIs that include a built-in memory, such as a CMOS microcomputer with backup means. As described above, according to the semiconductor memory device of the present invention, the control voltage that can indicate a binary value, that is, the added power supply voltage level or the ground level, depending on the change in the power supply voltage, and the selection for the memory device. A control signal is created by logic with the signal, and a signal input circuit is configured by the logic of this control signal and input signal, so the logic circuit method can be freely selected according to the next stage circuit method. In addition, it is possible to achieve low power consumption during backup due to the low power supply voltage, which is a feature of CMOS memory, and low power consumption when memory is not selected, without the hassle of external control over input signals. .

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional memory system with m rows and Xn columns matrix configuration, Fig. 2 is a circuit diagram showing a subordinate CMOS input circuit, and Figs. FIG. 4 is a circuit diagram showing the structure of an embodiment of the semiconductor memory device of the present invention. 11, 12... Signal input circuit, 13...
・Power supply potential detection circuit, Q31 to Q42...Transistor, R1, R2...Load resistance, M...
...Memory device. [Traditional] Figure 2 Figure 3 Figure '01 3rd illustration] Figure 4

Claims (1)

[Claims] 1. A power supply potential detection circuit that detects a change in power supply potential and inverts the output potential level; An inverted signal of the selection signal potential level of the selection signal line is output, and when the output potential level of the power supply potential detection circuit is at the second potential level, the ground potential level or the power supply potential level is set regardless of the selection signal potential level. A first signal input circuit that outputs an inverted signal of the potential level of the signal input line while the first signal input circuit is coupled to the signal input line and outputs an inverted signal of the selected signal potential level. and if the first signal input circuit is outputting the ground potential level or the power supply potential level, the second signal input circuit outputs the power supply potential level or the ground potential level regardless of the potential level of the signal input line. A semiconductor memory device comprising a signal input circuit.