JPS6020779B2 - Composite computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite computer system comprised of a plurality of computer systems.

Conventionally, in a composite computer system using a plurality of computer systems, there has been a problem in exchanging information to mutually know the status of each computer system.

FIG. 1 shows central processing control units 11, 21, main storage device 1,
2, 22, interrupt control devices 13, 23, input/output devices 14 such as a programmer, process input/output device, auxiliary storage device, etc.
Two complex electronic computer systems 1 consisting of 24.
Indicates 0,20. The mutual interrupt control devices 13 and 23 are connected. If a failure occurs in the central processing control unit 11, main storage 12, input/output device 14, etc. of the composite computer system 10, it is important to notify the other computer system 2 of the failure. An interrupt signal is sent from the interrupt control device 13 to the interrupt control device 23.

In this case, whether the content of the failure is the central processing control unit 11,
Is it the main storage device 12 or the input/output device 14?
For example, is the input/output device 14 an auxiliary storage device?
If it is necessary to distinguish between five layers of process input/output equipment, etc., a plurality of interrupt signal lines are required to correspond to the distinction. In addition, the side receiving the interrupt also receives the following information for each interrupt signal:
There are drawbacks such as the need for software to process the interrupt signal, which increases the size of the software. The present invention provides a composite computer system with a shared memory,
By storing information on the status of each computer system's components in a shared memory, without relying on individual interrupts,
The object of the present invention is to provide a composite electronic computer system that allows the status of other electronic computer systems to be easily known.

The details of the present invention will be explained below with reference to illustrated embodiments.

In FIG. 2, the same numbers as in FIG. 1 indicate the same parts.

3. Shared memory and complex electronic computer system 10
, 20.

The AI address in the shared memory 30 is the computer system 1
This is an address that stores the state of 0, and when the contents of the AI address change, an interrupt is generated to the computer system 20. Address A2 in the shared memory 30 is an address that stores the state of the computer system 20,
When the contents of address A2 change, the computer system 10
It is configured so that an interrupt is generated. The shared memory 30 can be accessed from either of the computer systems 10 and 20 by being connected to the central processing control units 11 and 21 via a memory bus, for example. , the input/output devices 14 and 24 can also be connected by direct memory access, and since this is a common practice in current computer technology, it will not be discussed here. In FIG. 3, one word of the shared memory 30 is composed of 16 bits. Each bit of the AI address stores the state of a component of the computer system 10. For example, the content 16 of the 0 bit stores information about the power supply of the computer system 10, and is 0 when the power is not turned on.
, and when it is in, it is 1.

The content 16 of the 0 bit is set to 1 or 0 by direct memory access from the power source.

The 1-bit content 17 is 1 if the main memory pupil 12 is normal, and 0 if it is malfunctioning, and is stored as 1 or 0 by a parity detection circuit or the like.

For example, the 2-bit content 18 in the input/output device 14 is
If the typewriter is normal, it will be 1, if it is malfunctioning, it will be 0.
When this state is detected by the program of the computer system 10, it is written by the program.

The remaining bits 3 to 15 are also associated with the states of the remaining components of the computer system 10. In addition, the A2 address also has the same configuration as the AI address,
The states of the components of the computer system 20 are stored.

In FIG. 2, it is assumed that a parity error occurs in the main storage device 12 of the computer system 10, causing a failure.

The content 17 of 1 bit at the AI address of the shared memory 30, which was previously 1 in the normal state, is rewritten to 0, and an interrupt occurs in the computer system 20. When this interrupt occurs, the program of the computer system 20 reads the contents of the AI address and detects that the 1-bit contents 17 are in a failure state. Even in the case of a failure in the computer system 20, it can be detected on the computer system 10 side in the same manner. According to the conventional method, in order to notify the other party of the current status of each component of a computer system, as many interrupts as there are components are required, but according to the present invention, the interrupts are Just one,
The status of the components of the other party's computer system can be known, and processing such as backing up the functions of the other party's computer system becomes easier than in the past.

Needless to say, what has been described above is applicable not only to the case where there are two computer systems, but also to the case where there are three or more computer systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional compound computer system, FIG. 2 is a block diagram of a compound computer system according to an embodiment of the present invention, and FIG. 3 is an AI of the shared memory in FIG.
It is a figure showing the contents of an address. 10,20...Electronic computer system, 11,2
1... Central processing control unit, 12, 22...
...Main storage device, 13, 23... Interrupt control device, 14, 24... Input/output device, 30...
- Shared memory, 16, 17, 18... Status bits of the components of the computer system 10. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 Consisting of a plurality of computer systems each having an interrupt control device and a shared memory that can be accessed from each of the computer systems, the interrupt control device of each of the computer systems is connected to the interrupt control device of the other computer system. a specific part allocated to each of the computer systems is provided in the shared memory, and each of the computer systems detects the state of its components, and comprising means for writing to a specific part, and means for generating an interrupt signal to another of the computer systems via the interrupt control device when a failure of the component is detected;
Further, each of the computer systems includes means for receiving the interrupt signal and reading out contents stored in the specific portion of the shared memory allocated to the computer system that generated the interrupt signal. Features: Composite computer system.