JPS6020931B2 - timer circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to timer circuits.

The timer circuit of the present invention outputs a pulse signal indicating that a predetermined time has elapsed after the arrival of an input signal, and sends out a safe output signal in response to a certain type of failure in the circuit. be.

Further, the predetermined time can be selectively defined from the outside, and it has a function that prevents dangerous malfunctions.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the timer circuit of the present invention, in which F/FA to F/FF are D-type flip-flop circuits that operate at the rising edge of a clock pulse, mVI and INV2 are inverters, GI is a NAND gate, G2
is an AND gate, TP is a terminal to which a logic signal that selectively defines the timer time is given, F/FA to F/FD are directly connected in cascade, and the output of F/FD is connected to the inverter INV.
2 to one input terminal of the NAND gate GI.

The other input terminal of NAND gate GI is connected to terminal TP, and the output of NAND gate GI is led to the input of F/FE. F/FE and F/FF are directly connected in cascade, and F/FE and F/FF are directly connected in cascade.
A clock signal is given to FA, F/FC and F/FE via an inverter mVI, and on the other hand, a clock signal is given to FA, F/FC and F/FE.
The above clock signal is applied as is to the FD and F/FF.

The initial values of these F/Fs are set to "1" by an initial setting signal from the set input terminal. Each output signal of these F/FA to F/FF is connected to the input of AND gate G2. The operation of the timer circuit having such a configuration will be explained next with reference to FIG.

Figure 2 shows the waveforms at each point of the timer circuit in Figure 1.The clock input terminal of the timer circuit has the waveform shown in Figure 2.
A clock pulse of a predetermined period as shown in "CLOCK" is always applied.

F/FA, F/TC and F/FE are equipped with inverter I.
Since this clock pulse is applied through the NVI, these flip-flops have the waveform “clock” in Figure 2.
Operates at the falling edge of . Therefore, when the input signal shown in the waveform "input" in FIG. 2 arrives, the F/FA changes from logic "1" to logic "0" at the first falling edge of the subsequent clock pulse.
Changes to

Then, at the falling edge of the first clock pulse after the input signal returns to its original state, the logic returns from logic "0" to logic "1".

Similarly, F/FB to F/FD operate sequentially, and the respective output waveforms become as shown in F/FB to F/FD in FIG.

Now, when logic "1" is applied to the terminal TP, the output of the F/FD is inverted by the inverter INV2, and further the NAND gate G
As a result of inversion at I, it becomes the same as if it were directly connected to the input of F/FE, and the output waveforms of F/FE and F/FF are F/F
Following D, the operation is performed sequentially, and the waveforms F/FE and F/FF in FIG. 2 become as shown by solid lines.

As a result, the output of this timer circuit obtained from the AND gate G2 is T as shown by the solid line in the waveform "output" in FIG.
This becomes a pulse signal with a time width of WI.

Next, the case where logic "0" is applied to the terminal TP will be described.

At this time, the operations from F/FA to F/FD are completely unchanged from those described above. However, since the output of the NAND gate GI is fixed at logic "1", the outputs of F/FE and F/FF both remain at logic "1", and the waveform F/FE in FIG.
, as shown by the broken line F/FF.

Therefore, the output of the AND gate G2 becomes a pulse signal with a time width of TW2, as shown by the broken line in the waveform "output" in FIG. In this manner, the time required for the output of the timer circuit to return to logic "1" after the input signal arrives can be selected by the logic selectively applied to the terminal TP.

Next, FIG. 3 shows an embodiment of a NAND gate which is suitable for use as the NAND gate GI of the timer circuit of FIG. 1, and a case where this is used will be described.

In FIG. 3, one input terminal is connected to the base of a transistor QI via an input resistor RA, and its collector is connected to a voltage source EC via a resistor RI, as well as to the base of a transistor Q2. .

The outside collector of the transistor Q2 is directly connected to the base of the transistor Q3, and is also connected to the other input terminal Tj, which is connected to the dedicated terminal TP, via an input resistor RB. The collector of the transistor Q3 is connected to the voltage source C via the resistor R2, and also to the output terminal of this gate, and the emitters of these transistors are grounded.

0 When such a NAND gate is used, the output of the timer circuit in FIG. , the gate output becomes "1". On the other hand, set “1” to this dedicated terminal TP.
is applied, the output of the gate becomes an inversion of the logic applied to the input terminal IN', and the overall operation of the timer circuit becomes as shown in FIG. Here, we will describe the effect of 0 by using the NAND gate shown in Figure 3.
When "1" is given to the dedicated terminal TP in order to make the elapsed time after the arrival of the input signal transparent over a long period of time, if this signal is not transmitted to the transistor Q3 due to poor contact or disconnection, etc., it will be ignored regardless of the input to the terminal IN. In other words, transistor Q2 becomes short-circuited or open-circuited depending on the input voltage at terminal IN, but in either case, the signal does not turn on transistor Q3, so the gate output is always "1" and a short period of time must be selected. <The result is the same as when "0" is given to the dedicated terminal.

0 In this way, the application of the input signal to the Ti terminal will not be interrupted by the application of a "1" signal due to transmission failure, so the longer time setting can be made shorter, and the longer time setting can be made shorter. What happens may happen, but the reverse does not occur.

Therefore, even if it is applied to applications where output representing an elapsed time longer than the set time should not be sent out, it is safe because dangerous side malfunctions can be avoided.

In the above explanation, the set output of the F/FD is inverted using the inverter INV2, but the F/FD
If you use the reset output of , inverter 2 is not needed.
In addition, as a NAND gate GI, the logic of the input terminal “
Open and short circuit signals are obtained in response to inputs of “1” and “0”,
Various modifications other than those shown in FIG. 3 may be considered as long as the above-mentioned logic function signal can be obtained as an output in response to the combination of this and the logic "1" and "0" of the input terminal Ti.

Also, D-F/F increases or decreases according to the required time setting,
Any time can be set.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 shows an embodiment of a timer circuit according to the present invention,
FIG. 2 is a timing diagram for explaining the operation of the timer circuit of FIG. 1, and FIG. 3 is a NAND gate suitable for use in the timer circuit according to the present invention. F/FA~F/FF...D-type flip-flop circuit, GI...NAND gate, G2...AND gate,
Melon V1, elbow V2...inverter. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. An input terminal, a plurality of D-type flip-flop circuits, a dedicated terminal for time selection, and a gate circuit receiving at its input a signal from the dedicated terminal and a signal from the flip-flop circuit; a logic circuit that obtains a logical function signal of the output of each of the flip-flop circuits, some of the flip-flop circuits are connected directly in series, and some of the flip-flop circuits are connected in series via the gate circuit, and the flip-flop circuits are connected in series to each other, and each of the flip-flop circuits is connected in series with the clock of the adjacent flip-flop circuit. The signals are mutually inverted and applied, and the input terminal to which an input pulse having a width of one cycle or more of the clock signal is applied is connected to the first stage of the series-connected flip-flop circuit, and is input to the dedicated terminal. 1. A timer circuit characterized in that the time width of the output pulse signal of the logic circuit is selectively obtained at a predetermined value depending on the logic to be used. 2. The timer according to item 1, wherein the gate circuit sends out a logic signal by a combination of a short circuit or open signal obtained from an input from a flip-flop circuit and an input signal via a dedicated terminal. circuit.