JPS6020934B2 - timer circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a timer circuit that utilizes the charging time of a current to a capacitor, and in particular, a timer circuit that also connects a discharge path that operates selectively to produce a repetitive operation. It is related to circuits.

Generally, a timer circuit used in a dimming circuit for a light lamp or a switching circuit for a plurality of illumination lights is built into the dimming control circuit or switching control circuit. In this case, the typical timer circuit configuration used is one that utilizes the charging and discharging of a capacitor, and the charging current for a certain period of time is used to operate a relay for a certain period of time by a driver element, or to control the terminal voltage. Achieves low to high voltage. For example, in the dimming circuit of a pre-determined fluorescent lamp, it is effective to advance the trigger phase as much as possible for a while after the power is turned on due to the child heat of the filament (however, when dimming is performed by phase angle control using a thyristor). , by using a timer circuit whose output voltage changes high and low, and some other elements,
Such a change in trigger phase can be easily performed.

Furthermore, the operation of the relay for a certain period of time is very simply configured with a timer circuit using a transistor. Figure 1 shows the latter, a conventional timer circuit using transistors, and the second
The figure shows the former, a conventional timer circuit that changes the output voltage.

0 In these figures, A and B constitute a charging path and a discharging resistor, respectively. In Figure 1, transistor 3 is ON for a time determined by the time constant of capacitor 1 and charging resistor 2, that is, relay 4 is activated. Similarly, in FIG. 2, the N-gate thyristor 7 conducts after a delay for a time determined by the time constants of the capacitor 5 and the charging resistor 6.
The output voltage Vo decreases to the Zener voltage Vz determined by the Zener diode 8.

In this way, the conventional timer circuit can operate a relay for a certain period of time or reduce the output voltage with a relatively simple zero configuration.

However, since the discharge path is simply constructed by connecting the discharge resistors 9 and 10 in parallel to the capacitors 1 and 5, the resistors 9 and 10 are connected in parallel to the capacitors 1 and 5. must be considerably larger than the charging resistors 2 and 6. That is, the circuit shown in Figure 1 is designed to prevent simultaneous discharging and bypassing of the base current of transistor 3 during charging, and the circuit shown in Figure 2 is designed to increase the impedance of the circuit itself and minimize leakage current. Therefore, it was necessary to increase the values of the discharge resistors 9 and 10. As a result, the discharge time becomes very long, and if the timer is operated again in a state where the battery has not been sufficiently discharged, the transistor 3 and the thyristor 7 conduct quickly and the battery cannot function as an accurate timer.

In other words, since such a timer needs to be used repeatedly, it is necessary to provide a discharge path, but the resistance that makes up the discharge path must be increased, so that the discharge cannot be stopped. This method has a drawback in terms of repeatability, in that the time taken is very long and the timer cannot be restarted at a relatively early timing. Therefore, it is an object of the present invention to provide a circuit that has no adverse effect on the circuit, has a discharge strategy that immediately discharges the charge during discharge, and has a timer that always operates at an accurate time regardless of the interval between repeated operations. It is about providing. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a timer circuit according to a first embodiment of the invention.

The configuration is different from the timer circuit shown in FIG. 1 in that an N-gate thyristor 11 is connected to the capacitor 1' in the forward direction instead of the discharging resistor 9, and the gate of the thyristor 11 is connected to the charging path A'. The structure is the same except that diodes 12 are connected between the anodes in all directions.

Next, to explain the operation of this circuit, now capacitor 1'
If the switch 13' is closed when there is no charge at all, a charging current flows to the capacitor 1', and this capacitor 1
′ and the time constant of the charging resistor 2′, the transistor 3′ is on for a certain period of time, and during that time the current terminator 4 is turned on.
' to operate the timer. When the transistor 3' is in the on state and in the off state after a certain period of time, the diode 1 is connected between the gate and the electrode of the thyristor 11.
Due to the voltage drop caused by 2, the thyristor 11 is reverse biased and therefore remains in the off state. If the switch 13' is closed in this state, a directional current will flow between the anode and the gate due to the charging capacity of the capacitor 1' via the leakage resistance between the gate and cathode of the thyristor 11. 'Let's turn on and get used to it.' Therefore, immediately after that, the charged wing charges are rapidly discharged in the fin path B' of the anode and cathode paths, and the capacitor 1' returns to its original state again. At the same time, the thyristor 11 also shifts to the off state. In this manner, the timer operation is performed by closing the switch 13', and immediately after opening the switch 13', the discharge is completed and the initial state can be restored.

Therefore, when the timer is used repeatedly, the timer can always be activated for an accurate time. Next, FIG. 4 shows a timer circuit which is another embodiment of the invention.

The difference in configuration from FIG. 2 is that the discharge resistor 10 is removed and an N-gate thyristor 14 is connected in parallel to the capacitor 5'.
is connected in the forward direction, and further connected to the charging path A' and to the thyristor 1.
The only difference is that a diode 15 is connected in all directions between the gate and anode of No. 4, and other aspects are basically the same.

Next, to explain the operation of this circuit, now capacitor 5
DC voltage V is applied to terminals a and b when there is no charge and noisy load at
If o is applied, a charging current flows to the capacitor 5', and the thyristor 7' turns on after a certain period of time determined by the time constant of the capacitor 5' and the charging resistor 6'. A timer operation is performed to reduce the voltage to approximately the Zener voltage Vz.

When the thyristor 7' is in the on state and in the off state after a certain period of time, there is a reverse bias between the gate and anode of the thyristor 14 due to the drop fin pressure caused by the diode 15, and the thyristor 14 maintains the off state. . In this state, if the voltage supply to the terminals a and b is stopped, a large amount of the capacitor 5' will be charged between the anode and the gate of the thyristor 14 through the leakage resistance between the gate and the cathode of the thyristor 14. A forward current flows through the thyristor 14, and as a result, the thyristor 14 is turned on and conductive. Immediately thereafter, therefore, the charged charges are rapidly discharged in the discharge path 8 of the anode-cathode path of the thyristor 14, and the capacitor 5' returns to its original state again. At the same time, the thyristor 14 also shifts to the off state. In this way, the fly pressure V is applied to terminals a and b.
By applying o, a timer operation is performed to reduce the voltage Vo to the voltage Vz for a certain period of time, and by stopping the voltage application, the discharge can be immediately completed and the initial state can be restored.

Therefore, when repeatedly performing the timer operation, it is possible to always perform the timer operation accurately. As explained above, in short. According to the invention, the resistance of the discharge path is reduced to an almost negligible level, and the discharging operation is completely separated from the charging operation and performed selectively, so the time required for discharging is extremely short. As a result,
It is possible to use a timer circuit that always outputs only the correct time.

Therefore, the timer circuit according to the present invention is particularly suitable for application to a dimming circuit or the like that is used repeatedly.

[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 and 2 show slave timer circuits;
FIG. 4 shows an embodiment of a timer circuit according to the present invention. 1, 5, 1', 5'...Capacitor, 2, 6, 2', 6
'...Charging resistor, 11, 14...N-gate thyristor, 12, 15...diode. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A timer circuit comprising a capacitor, a charging path connected in series to the capacitor, and a discharging path connected in parallel to the capacitor, and capable of repeatedly charging and discharging by selectively operating the charging path and the discharging path. . A timer circuit in which the discharging path is configured with an N-gate thyristor connected in parallel to the capacitor in a forward direction, and a diode is connected in the charging path in a forward direction between the gate of the thyristor and an anode.