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JPS6021402B2 - video to video dubbing equipment - Google Patents
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JPS6021402B2 - video to video dubbing equipment - Google Patents

video to video dubbing equipment

Info

Publication number
JPS6021402B2
JPS6021402B2 JP52107234A JP10723477A JPS6021402B2 JP S6021402 B2 JPS6021402 B2 JP S6021402B2 JP 52107234 A JP52107234 A JP 52107234A JP 10723477 A JP10723477 A JP 10723477A JP S6021402 B2 JPS6021402 B2 JP S6021402B2
Authority
JP
Japan
Prior art keywords
video
modulators
dubbing
signals
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52107234A
Other languages
Japanese (ja)
Other versions
JPS5441125A (en
Inventor
稔治 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP52107234A priority Critical patent/JPS6021402B2/en
Publication of JPS5441125A publication Critical patent/JPS5441125A/en
Publication of JPS6021402B2 publication Critical patent/JPS6021402B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はビデオ信号のダビング袋鷹に関し、より詳細に
は、ビデオ対ビデオの高速ダビングの際に使用できる再
生画のフリツカを防止するための装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal dubbing system, and more particularly to an apparatus for preventing flicker in a reproduced picture that can be used during high-speed video-to-video dubbing.

マスタ及びスレープの両ビデオテープレコーダ(VTR
)を用い、マス夕側からの再生信号をスレーブ側のVT
Rでダビングを行なうに当り、マスタ及びスレーブ側N
TRの回転ビデオヘッド数を通常のVTRのm倍(例え
ば4倍)としかつその回転速度をn倍(例えば5倍)と
し、そしてキャプスタンのテープ送り速度を(mxn)
倍とすることによって、ダビング速度を通常の(mxn
)倍例えば2ぴ部こ上げることを可能とした高速ダビン
グ方式が提案されている。
Both master and slave video tape recorders (VTRs)
) is used to transmit the playback signal from the master side to the slave side VT.
When dubbing on R, the master and slave side N
The number of rotating video heads of the TR is m times (for example, 4 times) that of a normal VTR, the rotation speed is n times (for example, 5 times), and the tape feeding speed of the capstan is (m x n).
By making the dubbing speed twice the normal speed (mxn
) A high-speed dubbing method has been proposed that enables the recording to be doubled, for example, by 2 times.

この場合、ダビングをビデオ対ビデオで行なうと、複数
のデモジュレータ及びモジュレータが必要となり、この
ためモジユレータのキャリアのレベルが正確に合ってい
なければ、再生画にフリツカが生じることになる。本発
明は、複数のモジュレータのキャリアのレベルを正確に
かつ安定に合わせることを目的とする。
In this case, when dubbing is performed video-to-video, a plurality of demodulators and modulators are required, and if the carrier levels of the modulators are not accurately matched, flickering will occur in the reproduced picture. An object of the present invention is to accurately and stably match the carrier levels of a plurality of modulators.

図はこの目的を達成する本発明一実施例回路図であり、
端子10及び1 2にはマスタVTRのヘッド1及び2
から再生されたビデオ信号1及び2が与えられる。
The figure is a circuit diagram of one embodiment of the present invention that achieves this purpose,
Heads 1 and 2 of the master VTR are connected to terminals 10 and 12.
Video signals 1 and 2 reproduced from are provided.

これはそれぞれ増中器14,16及びモジユレー夕18
及び20を介してスレープVTRの各ヘッドに対する記
録増中器に接続される端子22及び24に与えられる。
このような態様でビデオ対ビデオのダビングを行なうと
、上述したようにモジユレータ18,20のキヤリアの
レベルが正確に合っていなければ、ダビングしたビデオ
の再生画にフリッカが生じることになる。そこで、本発
明によれば、少なくとも一方の増中器14,16の直流
レベルを制御し、モジュレータ18,20のキャリアの
レベルを正確にかつ安定に合わせるものである。モジュ
レータ18,20の出力はそれぞれ第1のゲート及び第
2のゲート26及び28に与えられる。
These are intensifiers 14, 16 and module 18, respectively.
and 20 to terminals 22 and 24 which are connected to recording intensifiers for each head of the slave VTR.
If video-to-video dubbing is performed in this manner, flickering will occur in the reproduced image of the dubbed video unless the carrier levels of the modulators 18 and 20 are accurately matched as described above. Therefore, according to the present invention, the DC level of at least one of the intensifiers 14 and 16 is controlled, and the carrier levels of the modulators 18 and 20 are adjusted accurately and stably. The outputs of modulators 18 and 20 are provided to first and second gates 26 and 28, respectively.

それぞれのゲート26,28を制御するゲート制御信号
は端子30,32に与えられる第1及び第2のビデオ信
号のプランキング又はべディスタルバルスのような一定
レベルの基準位置となる信号によって与えられる。ゲー
ト26,28からの信号は加算点34を介してデモジュ
レータ(LPF、ェンベロープ検出器等であってもよい
。)36に与えられて復調され、次いで第3のゲート3
8、第4のゲート40に与えられる。これらゲート38
,40もそれぞれ上述した端子30,32からの信号を
受け、その後ゲート38,40からの信号はホールド回
路42,44で保持され、次いで差鰯増中器46に与え
られ、誤隻葦電圧が取出される。この誤差電圧は例えば
一方の増中器16に与えられ、その直流レベルを制御す
るように使用される。この構成を持ってすれば、多系統
のモジュレー夕のキャリアの違いを検出し、得られた誤
差信号がモジユレータにフィードバックされて、モジユ
レータのキャリアが自動的かつ安定に合せられる。
The gate control signals controlling the respective gates 26, 28 are provided by constant level reference signals, such as blanking or bedside pulses, of the first and second video signals applied to terminals 30, 32. The signals from the gates 26 and 28 are applied to a demodulator (which may be an LPF, an envelope detector, etc.) 36 via a summing point 34 to be demodulated, and then to a third gate 3
8, applied to the fourth gate 40. These gates 38
, 40 also receive signals from the above-mentioned terminals 30, 32, respectively, and then the signals from the gates 38, 40 are held in hold circuits 42, 44, and then given to the differential sardine intensifier 46 to increase the voltage of the sardines. taken out. This error voltage is applied to one of the intensifiers 16, for example, and is used to control its DC level. With this configuration, differences in the carriers of multiple modulators are detected, the obtained error signal is fed back to the modulator, and the carriers of the modulators are automatically and stably adjusted.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例回路図であり、14,16は増中
器、18,20はモジュレー夕、26,28,38,4
0はゲート、36はデモジユレータ、42,44はホー
ルド回路、46は叢勤増中器を示す。
The figure is a circuit diagram of an embodiment of the present invention, in which 14 and 16 are multipliers, 18 and 20 are modulators, and 26, 28, 38, 4
0 is a gate, 36 is a demodulator, 42 and 44 are hold circuits, and 46 is a multiplier.

Claims (1)

【特許請求の範囲】[Claims] 1 ビデオ対ビデオでダビングを行なう装置の各再生ビ
デオヘツドのモジユレータのキヤリアのレベルを合わせ
るための装置に於いて、 各上記モジユレータの出力を
関連入力ビデオ信号の一定レベル位置でゲートする手段
と、これらゲート出力をレベル検出するための手段と、
その出力をそれぞれの上記レベル位置に於いて比較する
ための手段と、これからの誤差信号を各上記モジユレー
タにフイードバツクする手段とよりなるダビング装置。
1. In a device for matching the carrier levels of modulators of each playback video head of an apparatus for video-to-video dubbing, means for gating the output of each of the modulators at a fixed level position of the associated input video signal; means for level detecting the gate output;
A dubbing device comprising means for comparing the outputs at each of the above-mentioned level positions, and means for feeding back an error signal from this to each of the above-mentioned modulators.
JP52107234A 1977-09-08 1977-09-08 video to video dubbing equipment Expired JPS6021402B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52107234A JPS6021402B2 (en) 1977-09-08 1977-09-08 video to video dubbing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52107234A JPS6021402B2 (en) 1977-09-08 1977-09-08 video to video dubbing equipment

Publications (2)

Publication Number Publication Date
JPS5441125A JPS5441125A (en) 1979-04-02
JPS6021402B2 true JPS6021402B2 (en) 1985-05-27

Family

ID=14453878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52107234A Expired JPS6021402B2 (en) 1977-09-08 1977-09-08 video to video dubbing equipment

Country Status (1)

Country Link
JP (1) JPS6021402B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034142Y2 (en) * 1979-10-18 1985-10-11 オリンパス光学工業株式会社 FM recording device

Also Published As

Publication number Publication date
JPS5441125A (en) 1979-04-02

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