JPS6021437B2 - Memory storage area display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory storage area display method for graphically displaying the remaining storage capacity of a memory used in an electronic computer or the like.

In electronic computers, for example, when a user is inputting data, he or she may want to check how much free space there is in the memory area where the data should be stored.

To confirm this, the computer is equipped with a "size" key, for example, and by operating that key, the remaining capacity after subtracting the capacity that has already been used from the total capacity of the memory is displayed as a number, such as "N bytes." It was thought to do. However, with a system that only displays the remaining storage capacity numerically, the ratio between the capacity that has been stored up to now and the capacity that will be stored in the future is unclear. It is difficult to immediately know how long a program to be created can be memorized.

This invention was stolen due to the above-mentioned circumstances, and allows users of electronic computers to know how much memory space remains and how much memory space has been used. It is an object of the present invention to provide a memory storage area display method that can be recognized at a glance.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the circuit configuration of an electronic computer according to the present invention, and the keyboard 12 includes letters, letters, etc., although details are not shown.
It is equipped with input keys for symbols, numerical values, etc., and is further equipped with a size J key 11 for recognizing the storage area.The input signal line of this keyboard 12 is a 1/0 size J key 11 that functions as an interface with peripheral devices. It is connected to the board 13.A mutually directional data bus DB and a control bus CB are taken out from the central processing unit (hereinafter abbreviated as CPU), and the data bus DB is connected to the 1/0
It is connected to a refresh memory 17 via a boat 13, a memory 15, and a bus buffer 16 to transfer data signals. Further, the control bus CB is connected to the first port 13, the memory 15, and the refresh memory 17 to provide control signals. Further, a unidirectional address bus AB is taken out from the CPU 14, and an address command is given to the refresh memory 17 via the one-node port 13, the memory 15, and the multiplexer 18. The above IJ
The signal from the fresh memory 17 is sent to the synchronous control circuit 20.
The signal is converted into serial data by the shift register 19 using the timing signal from the synchronous control circuit 20, is combined with the control signal from the synchronous control circuit 20 in the synthesis circuit 21, and is displayed on the CRT display section 22 by the synchronous signal from the synchronous control circuit 20. Ru.

Further, from the synchronous control circuit 20, an address bus AB' for specifying an address for reading data from the refresh memory 17 is connected to the multiplexer 18.
An address for reading refresh memory 17 is selected.

Note that the memory 15 is equipped with four memory cassettes each having a storage capacity of 4 kbytes, and each memory cassette is detachably installed.

In the above configuration, when the power is turned on, the operation according to the flow shown in FIG. 2A is executed.

First, in step S, the start address of the memory 15 is stored in the register D in the CPU 14. Next, in step S2, the start address of the empty area of the memory 15 is
14 is stored in register A. Furthermore, in step S3, the final address of the memory 15 is set to register B in the CPU 14.
is stored in

Next, in step S4, other control systems are initialized,
In step S6, the computer enters a state of waiting for input from the keyboard 12, and when a key operation is performed, a processing operation corresponding to the input state is executed in step S6. Next, after a predetermined program setting key is operated, when a key for storing this key code in the memory 15 is operated, the operation shown in the flowchart of FIG. 2B is executed.

First, in step S7, the length of the key code is converted into the number of addresses and stored in register C within the CPU 14. Then, in step S3, the first address of the empty area stored in register A is added to the number of addresses stored in register C, and the addition result is added to register A.
is stored in Then, in step S9, the number of addresses in this register A is compared with the final address of the memory 15 stored in the register B. For example, the key code is written into the memory 15 in step SM. Further, in the state of B≦A, it is impossible to write the above key code into the memory 15, so step S,
．． will output an overflow message, requesting replacement of new memory, for example. In such a storage process, if the user wants to know the state of the remaining free space in the storage area of the memory 15, the size key 11 of the keyboard 12 is operated. At this time, the operation shown in C of FIG. 2 is executed. First, in step S, 2, the entire storage area of the memory 15 is derived by calculating B-D, and this is divided into 4
Divide by k bytes and store the result in register C. That is, the calculation result indicates how many blocks are set in the 4-kbyte memory cassette. In step S, 3, this block number is supplied to the refresh memory 17 as block frame data and stored therein, and is displayed on the display section 22 in the form of a frame, for example, as shown in FIG. 3A.

Next, in step S, 4, register D, which stores the start address of the memory, is subtracted from register A, which stores the start address of the empty area, and the result is divided by 4 kbytes. Then, the integer part of the division result is transferred to register B.
The remainder is stored in register F. Next step S, 51
At this time, block diagram data for filling in blocks of the number of blocks stored in register E is written to refresh memory 17. Furthermore, the remaining number of addresses stored in register F is calculated as a 4K byte ratio, and the number of used addresses is displayed in the next block frame according to this ratio, and as shown in FIG. It graphically displays the memorized part. In the above embodiment, the usage status of each block of the removably used memory cassettes is displayed graphically, so you can see at a glance which memory cassette is empty, and you can remove the empty memory cassette. However, the present invention is not limited to this, and the memory cassette does not necessarily have to be removable.

As described above, by providing the memory storage area display method as described above, the following effects are achieved.

A. When multiple memory cassettes are removable, the currently installed memory capacity is displayed graphically, allowing you to see at a glance the status of memory installation/removal/expansion.

B Memo The area occupied by the written data is displayed graphically, so you can see the memory usage status at a glance.

C. Since the written capacity relative to the writable capacity of the memory is graphically displayed, data can be written to the remaining memory area effectively.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIGS. 2A, B, and C are flowcharts for explaining the operation of the above circuit configuration, and FIGS. 3A, B and C are diagrams illustrating the display state of the display unit. 11... "Size" key, 12... Keyboard, 14.
...CPU, 1 5...Memory, 1 7...
...Refresh memory, 22...CRT display section. 〆1 prisoner *3 meat o 24

Claims (1)

[Scope of Claims] 1. An electronic computer capable of expanding memory, characterized by comprising means for storing the capacity of a storage area of the memory, and means for graphically displaying the storage area. Storage area display method. 2. A memory storage device characterized by comprising means for accumulating the storage capacity occupied by data each time data is written into the memory, and means for graphically displaying an area corresponding to the accumulated storage capacity. Area display method. 3 means for storing the capacity of the storage area of the memory; means for accumulating the storage capacity occupied by data each time data is written to the memory; and means for graphically displaying the area corresponding to the capacity of the storage area. and means for graphically distinguishing and displaying a portion corresponding to the cumulative result in association with the graphically displayed area.