JPS6021490B2 - timer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer device that can independently preset timer times using a plurality of variable resistors. This aims to minimize the variation in each setting time due to variation in the resistance value of the variable resistors, eliminate the need to compensate for variation in the resistance value of these variable resistors, and simplify adjustment and correction of the entire circuit during the manufacturing process. thing.

■ It is possible to relatively easily set the change characteristics of the set time with respect to the rotation angle (or slide position) of these variable resistors for time setting, and to obtain the characteristics with high precision. '3' Use a single small-capacity capacitor so that the setting time can be varied within a sufficiently wide range (for example, from several seconds to one hour).

■ It should be easy to configure and can be realized at low cost.

The purpose of the present invention is to provide a long-term timer device that is excellent in various aspects.

Conventionally, in long-term timer devices that can set time using a variable resistor, a fixed resistor or semi-fixed resistor is connected in series or in parallel with the variable resistor in order to compensate for variations in the resistance value of the variable resistor. Then, the combined resistance value is adjusted to a predetermined value, or the voltage at the terminal that provides the reference voltage is adjusted.

However, when trying to configure a timer device that can independently set the time in advance using multiple variable resistors, the adjustment is difficult.
It is necessary to perform this for each variable resistor, which is troublesome and furthermore, the circuit configuration becomes complicated. Further, due to variations in the variable resistor, variations may occur in the minimum set time, or variation may occur in the change characteristics of the timer time with respect to the rotation angle of the variable resistor, resulting in an inconsistent set time. Further, the method of adjusting the reference voltage can be used for a single variable resistor, but cannot be used for a plurality of variable resistors. In addition, in a conventional long-time timer that uses an oscillator circuit and a counter that utilizes the charging and discharging of a capacitor, when setting the timer time by changing the resistance value of a variable resistor to charge the charging current to the capacitor, it is necessary to Since the current during discharge changes significantly depending on the timer time set, when accuracy is required, the range of change in the timer time is narrow.

As described above, the conventional long-time timer devices have drawbacks in terms of accuracy and versatility, and when attempting to configure a device that can preset the timer time with multiple variable resistors, the characteristics are non-uniform. Variation in setting time due to
A problem arises in that costs increase due to the necessity of adjustment and correction processes and the complexity of the configuration.

SUMMARY OF THE INVENTION Therefore, the present invention aims to solve the various problems mentioned above and provide a timer device that is comprehensively superior in terms of characteristics, cost, mass productivity, etc.

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows an embodiment of a timer device (for long time use) based on the present invention.

In FIG. 1, 1 is a DC power supply and 2 is a power switch.

A is a charging/discharging circuit, which is composed of a resistor 3, a semi-fixed resistor 4 for correcting characteristics, and a charging/discharging capacitor 5, which outputs a charging/discharging voltage Vc. B is a voltage setting circuit,
Fixed resistors 6, 7, 8, 9, variable resistors 10a, 10b
, 10c and a selection switch 27, and a variable resistor 10.
One of the fin pressures applied by the sliding terminals a to 10c is outputted as a high set voltage Vd via the selection switch 27, and a low set voltage Vi is outputted from the connection point of the resistors 8 and 9. The variable resistors 10a to 10c are each connected in parallel to the fixed resistor 7 through two terminal terminals that give a total resistance value, and the sliding terminal is selected so that the resistance value of the two terminal terminals does not change. It is designed to be selected by a switch 27. C is a voltage comparison circuit, consisting of two comparators 11 and 12, comparator 11 inputs charging/discharging voltage Vc and high setting voltage Vd, comparator 12 inputting charging/discharging voltage Vc and low setting voltage V
It takes i as an input and emits a predetermined output according to each input state. D is a latch circuit, which includes an R-S flip-flop 13, an inverter buffer 14, and resistors 15 and 1.
6 and a transistor 17, the R-S flip-flop 13 uses the outputs of the two comparators 11 and 12 as a set input S and a reset input R, respectively, and generates an output Q. While the output Q is at low level, transistor 1
7 is turned on to discharge the capacitor 5. E is a counter, which is made up of a multistage flip-flop 18, a count control circuit 19, and an inverter buffer 21. Then, the output Qn becomes higher level than low level. The count control circuit 19 stops the counter operation of the multi-stage flip-flop 18 and holds the output Qn at a high level after the output Qn reaches the /. level, and when the reset signal Re becomes a low level, the multi-stage flip-flop 18 This functions to set the counting operation to the initial state (state where the count number is zero). F is a drive circuit, which is made up of resistors 22, 23, transistors 24, relays 25, and diodes 26. When the force counter E counts up (the output Qn is at the no level), the relay 25 turns off and controls the This is to stop power supply to the target load (not shown). Next, the operation will be explained.

If the current high setting voltage yd is set to an appropriate value between the voltage VH at the connection point of resistors 6 and 7 and the voltage VL at the connection point of resistors 7 and 8, and the power switch 2 is turned on at time to, the charging/discharging voltage yc will be As shown in FIG. 2a, it increases exponentially with respect to the power supply voltage Vcc.

When this charging/discharging voltage Vc reaches the high set voltage Vd at time t, the output of the comparator 11, that is, the set input S of the R-S flip-flop 13 changes from the high level to the low level as shown in FIG. 2b. As a result, the output Q of the R-S flip-flop 13 changes from a high level to a low level as shown in FIG. 2d, turning on the transistor 17 and discharging the capacitor 5. Even if the charge/discharge voltage Vc becomes lower than the high setting voltage yd due to the discharge of the capacitor 5 and the output of the comparator 11 becomes a high level, the output Q remains at a low level, so the charge/discharge voltage Vc becomes lower. ,
At this time, the low set voltage Vi is reached. Then, the output of the comparator 12, that is, the reset input R of the R-S flip-flop 13 is inverted from the /-I level to the low level as shown in FIG. Even though the capacitor 5 is in a charging operation and the charging/discharging voltage Vc is higher than the low set voltage Vj and the output of the comparator 12 is at a high level, the output Q does not change and remains at a high level.
The charging/discharging voltage Vc increases and returns to the high set voltage V at time t3.
After reaching d, the same operation as described above is repeated. That is, in this operation, the output Q of the R-S flip-flop 13 becomes low level only from the time when the set input S changes from high level to low level until the reset input R changes from high level to low level. Since the capacitor 5 discharges rapidly, this operation is performed in an extremely short time and is negligible compared to the time it takes for the charging/discharging voltage Vc to reach the low set voltage Vd. This is the high setting voltage yd
=Vi, the charging/discharging voltage Vc has the characteristic VcL of Fig. 2a.
The same applies to the case where The oscillation operation is performed as described above, and the R-S flip-flop 13 outputs Q.
This output Q is input to a multi-stage flip-flop 18, and its input pulses P are counted. If this multi-stage flip-flop has n stages, the 2n-1st input pulse P causes the final stage flip-flop to output a high level output Qn. As a result, the output Qn is converted to a low level by the inverter buffer 21, turning off the transistor 24 and turning off the relay 25. Now, if the period of the charging/discharging voltage Vc is Ts, then from FIG. 2a, Ts=t3-t. The time for the counter E to count up, that is, the timer time T, is approximately T=2n-1・
It is given by Ts.

After all, after turning on the power switch 2 at time t=a,
As shown in b, the charging/discharging voltage Vc repeats the oscillation operation as shown in the figure, and the time t=to+ when the number of oscillations reaches 2n-1.
Counter E counts up at T, relay 25 is turned off by output Qn, and timer time T ends. As explained above, when the output Qn reaches a high level from a low level, the count control circuit 19 does not perform any counting operation and the output Qn goes to a high level, regardless of the oscillation operation of the charging/discharging voltage Vc. Retained. According to the above explanation, the timer time T is determined by the cycle Ts of the charge/discharge voltage Vc, and the cycle Ts is determined by the time it takes for the charge/discharge voltage Vc to charge from the low set voltage Vi to the high negotiated voltage yd. has become clear.

Next, the relationship between the period Ts and the high setting voltage Vd will be explained using FIG. 4.

In the figure, when the high setting voltage Vd is the maximum 4, that is, Vd=
When VL, the period Ts=TsL, and the high setting voltage V
When d is maximum, that is, when Vd=VH, the period Ts=
It becomes TsH. When the high set voltage Vd is between VL and VH, the period rs takes a value between TsL and TsH. By the way, the value of this high setting voltage Vd is determined by the variable resistors 10a, 10b,
This is given by one of the sliding terminals of the variable resistors 10a, 10b, and 10c, and the resistance value change characteristics with respect to the rotation angle 0 (slide position in the case of a sliding type) are expressed in a linear form (B characteristic). ), the high set voltage Vd changes linearly with respect to the rotation angle 8, and as shown in Figure 4, when 8 = 0%, Vd = VL, and when 8 = 100%, Vd
=VH. Therefore, as is clear from FIG. 4, the period Ts is uniquely given by the rotation angle, and since the timer time T is proportional to the period Ts, the rotation angle is 8.
On the other hand, the timer time T has a relationship as shown in FIG.

Although this relationship is not linear, it is uniquely given,
This shows that the timer time T is determined by giving a rotation angle of 0. Next, fixed resistors 6, 7, 8.9 in voltage setting circuit B and three variable resistors 10a
, 10b, and 10c will be explained.

The fixed resistors 6, 7, 8, and 9 are usually selected to have a small permissible variation in resistance value, for example, about 1% or 2% resistance. On the other hand, variable resistor 10
a, 10b, and 10c are used whose tolerance for resistance variation is ±20% (or 10%) of the normal resistance value, and their resistance values are the same and relative to the resistance value of fixed resistor 7. The value is sufficiently large. With such a configuration, the resistance values of the variable resistors 10a, 10b, and 10c are set to, for example, 2.
Even if 0% variation occurs, the variation in the combined resistance value with the fixed resistor 7 will be a sufficiently small value, and as a result, the variation in the voltages VL, VL and the low set voltage Vi will be sufficiently small. Therefore, now three variable resistors 10a, 10
The resistance value of b, 10c is Rv (Q), the allowable variation thereof is Kv (%), and the resistance value of the fixed resistor 7 is RF (
Q), the allowable value of the variation is KF (%), and these relationships are as follows: By selecting to satisfy the variable resistor 1
When 0a, 10b, and 10c are all in the same direction with maximum variation of the allowable value, the variation of voltages VL, VH, etc. is the voltage VL, VH when the resistance value of fixed resistor 7 is variation. Therefore, due to the characteristics, such a configuration can significantly reduce the variation in the resistance values of the variable resistors 10a, 10b, and 10c.

That is, as is clear from the above description, it is possible to construct an extremely highly accurate configuration while using the low-cost ordinary variable resistors 10a, 10b, and 10c. Note that although it is usually appropriate to use resistors 6, 8, and 9 with the same tolerance value, they may not necessarily be the same depending on the ratio of voltages VH, VL, and low setting voltage Vi. Also good.

In other words, the voltages VL and VH caused by these variations
It can be said that it is a rational design that the degree of variation is uniform, for example, even if fixed resistors 8 and 9 are used with low-cost resistors with a tolerance of 5% variation, due to the characteristics There may be no problem, so it is desirable to select and use it appropriately. Also, in this voltage setting circuit B, a fixed resistor 8
functions to give the minimum value of the timer time T, but if its resistance value is extremely small or OQ, in terms of the offset voltage and response speed of the comparators 11 and 12,
Since oscillation operation may become impossible or normal timer time may not be obtained, it is necessary to design in an area where these problems do not occur.

So far, we have searched for a method to minimize the variations in the voltages VL, VH, and low setting voltage Vi in the voltage setting circuit B, but some variations still occur and the charging/discharging circuit A
In particular, due to variations in the capacitance of the capacitor 5,
Variations in the charging/discharging voltage Vc over time, especially during charging, cause variations in the timer time T, but the function of the semi-fixed resistor 4 is to jointly correct these variations. .

Note that this semi-fixed resistor 4 has some drawbacks in terms of manufacturing process and reliability.
It is also possible to insert a suitable fixed resistor during adjustment.
20%), the semi-fixed resistor 4 can be omitted if acceptable accuracy can be obtained as a whole because there is little variation in the timer time T due to other parts. Next, another embodiment will be described.

FIG. 6 shows another embodiment of the voltage setting circuit, in which fixed resistors 7a, 7b, 7c and variable resistors 10a, 10b, . 10c are connected in parallel. The voltage at the sliding terminal of the variable resistor 10a is arbitrarily applied from the voltage VL across the fixed resistor 7a to V, depending on the circuit angle oa. The variable resistors 7b and 7c are also arbitrarily given a voltage between V and V2 and between V2 and VH, respectively, depending on their rotation angles 0b and oc. Therefore, from the operation explained in Fig. 1, the timer time T is 8 rotation angles.
The characteristics shown in FIG. 7 are given for a, ob, and 8c. Let the timer time T be TL=1 minute, r,=4 minutes, L=7
If L=1 minutes, the timer time T is 1 to 4 minutes by the variable resistor 10a, and 4 to 7 minutes by the variable resistor 10b.
The selection switch 27 selects between 7 and 1 minute using the variable resistor 10c.
The relationship between the fixed resistors 7a, 7b, and 7c and the variable resistors 10a, 10b, and 10c connected in parallel with them, respectively, is determined according to the above-mentioned formula (1).・By selecting the resistance value and tolerance value of variation so as to satisfy the disc relationship, the three variable resistors 10a, 10b,
This will greatly reduce the variation in the resistance value of 10c.

Furthermore, FIG. 8 shows another embodiment of the voltage setting circuit, in which variable resistors 10a and 10b are connected in parallel to a fixed resistor 7a,
The variable resistor 10c is connected in parallel to the fixed resistors 7a and 7c.

In this case, the voltage at the connection point of fixed resistors 7a and 7c is set to VM
If the timer time T corresponding to this voltage is TN, then from the above operation, the timer time T and the variable resistor 10
Rotation angles 8a, 8b, respectively of a, 10b, 10c,
The relationship with oc is as shown in FIG. Variable resistor 10a
, 10b, 10c and the fixed resistors 7a, 7c can be selected according to the above-mentioned formulas (1) and (0), thereby greatly reducing variations in the resistance values of the variable resistors 10a, 10b, 10c. It becomes a scale.

That is, for example, for the fixed resistor 7a, the variable resistor 1
Among the resistance values of 0a and 10b and the variable resistor 10c, (V
By considering the combined resistance value of the resistance value corresponding to the ratio of (VM.VL) to (VM.VL) as the resistance value of the variable resistor in formula (0), formula (0) is satisfied. It can be achieved. Next, still another embodiment is shown in FIG.

In the figure, A' is a charging/discharging circuit, with resistors 28 and 30.
, 3, consists of a diode 29 for temperature compensation, a semi-fixed resistor 4 for compensation of variations, a transistor 31, and a capacitor 5, and uses the action of the transistor 31 to configure a constant current circuit, so that the capacitor always maintains a -constant current. 5 is charged.

8 is a voltage comparison circuit, variable resistors 10a and 1ob are fixed resistors 7a, and variable resistors 10c are fixed resistors 7a.
and 7b, respectively, and in particular, the variable resistor 7c.
has a center tap 32, which is connected to fixed resistors 7a,
It is connected to the connection point 7b.

Furthermore, fixed resistors 7a and 7b have the same resistance value. The rest is the same as in FIG. D' is a latch circuit,
It is composed of an R-S flip-flop 13, a NAND gate 33, resistors 15 and 16, and a transistor 17.
The R-S flip-flop 13 operates in the same manner as shown in FIG. 1, and the NAND gate 33 turns on the transistor 7 and turns on the capacitor 5 when one or both of its two inputs becomes low level. It causes discharge. E' is a counter, 34 is a multistage flip-flop, and 35 is the output Q. of the first stage flip-flop of the multistage flip-flop 34. 36 is the terminal of the reset input Re of the multi-stage flip-flop 34. 21 is an inverter buffer.

C and F are the same voltage comparison circuit and drive circuit as in FIG.

Next, the operation will be explained.

Since the output of the inverter buffer 21 is at a high level until the counter E' counts up after the operation switch 2 is turned on, the NAND gate 33 of the latch circuit 0 is R.
Since the transistor 17 is turned on only while the output Q of the 1S flip-flop 13 is at a low level, the oscillation operation is performed in the same manner as in FIG.

Since the charging/discharging circuit A' charges the capacitor 5 with a constant flow, the charging/discharging voltage Vc becomes as shown in FIG. 11. That is, when the high setting voltage Vd=VH, the charging/discharging voltage Vc
is VcH as shown in the figure, and when Vd=VM, VcN,
When Vd=V, it becomes VcL. That is, the charging/discharging voltage Vc
is a characteristic in which the voltage change during charging is proportional to time. Also, the time when the charge/discharge pressure Vc is discharged, for example (t2-
t, ) is extremely short as described in the explanation of Fig. 1, so the oscillation period s (t3-t, t4-L, etc. in the figure) is a value almost proportional to the high setting voltage Vd. becomes. The relationship between the rotation angles 8a, ob, 8c of the variable resistors 10a, 10b, 10c and the voltage is the 12th
It will be as shown in the figure.

Now, as this oscillation operation is repeated, the counter E
When the output Qn of the multi-stage flip-flop 34 becomes high level, the output of the inverter buffer 21 becomes low level, so the output of the NAND gate 33 becomes high level, the transistor 7 is turned on, and the capacitor 5 is turned on. Discharge.

Regardless of the state of the output Q of the R-S flip-flop 13, the output of the NAND gate 33 is at the /. The operation will be maintained in a stopped state. Therefore, as described above, since the timer time T is proportional to the oscillation period Ts mentioned above, the timer time T and the variable resistor 10a, 10b,1
The relationship between rotation angles 8a, hib, and 8c of 0c is as shown in FIG. 12.

As shown in the figure, the timer time T is given in a linear relationship with respect to the rotation angle 0, etc. The function of the center tap 32 of the variable resistor 10c is to reduce variations in the timer time T when variations occur in the linearity of the resistance value change characteristics with respect to the rotation angle 8c of the variable resistor 10c. The high setting voltage Vd from the sliding wheel at the position of the center tap 32 (rotation angle 8c=50%) is fixed to the voltage VM. The relationship between fixed resistors 7a, 7c and variable resistors 10a, 10b, 10c is that for fixed resistor 7a, variable resistors 108, 1
0b and 1/2 of the resistance value of the variable resistor 10c is set as the resistance value Rv of the variable resistor, and the fixed resistor 7c is set so that the above formula (0) is satisfied. On the other hand, if Rv is set to 1/2 of the resistance value of the variable resistor 10c and it is selected so that formula (n) is satisfied, the variable resistor 10c
Variations in the timer time T due to variations in the resistance values of a, 10b, and 10c can be significantly reduced.

The timer time T of the entire circuit is corrected using semi-fixed resistor 4.
In this case, the timer time T can be corrected in a short time by measuring the period (twice the oscillation period) of the output Q of the first stage flip-flop of the multi-stage flip-flop 34. I can do it.

Of course, the oscillation period of the charging/discharging pressure Vc of the capacitor 5 may be directly measured by a high impedance measuring device.
Next, FIG. 13 shows an applied embodiment of the long time timer device of the present invention.

In Fig. 13, 37 is a commercial power supply, 38 is a push-button power switch, 39 is a regular contact of the relay 25, and 40 is a load, which in the case of a cooking machine is an electric heater, a high-frequency generator, and an electromagnetic generator for gas control. A heat source such as a valve or a heat source control device.

41 is a low voltage transformer, 42 is a rectifying diode, 43 is a capacitor, 44 is a resistor, and 45 is a Zener diode, both ends of which generate a DC voltage Vcc.

46 is a circuit consisting of a charging/discharging circuit, a voltage setting circuit, a latch circuit, and a counter, and its output operates the relay 25 of the drive circuit.

In this configuration, when the power switch 38 is first turned on, the relay 25 is turned on and its normally open contact 39 is closed, and even if the power switch 38 is subsequently released, the load 40 and the low voltage transformer 41 are energized.

When the timer time T elapses, the counter counts up, the transistor 24 turns on, and the relay 2
5 is also turned off, its contact 39 is opened, and power supply to the load 40 is stopped. At the same time, the power supply to the low voltage transformer 41 is also stopped, so the relay 25 is completely turned off thereafter. In this example, after the operation of the count control circuit 19 and the NAND gate 33 explained in FIG. 1 and FIG.
The function of holding the output state No. 4 is not necessarily necessary, and can be omitted if there is no problem such as malfunction.

The long-time timer device according to the present invention has been described above with reference to embodiments, but in addition to the embodiments described above, '1] The relay 25 of the drive circuit F is turned on after the timer time T has elapsed, and is turned off before then. can also be done easily.

'21 The variable resistor may be a rotary type or a rotary type, and its resistance change characteristics may be selected as necessary.

In addition, the number is not three as in the embodiment, but any number of two or more can be configured. If the functions of the leg force count control circuit 19 and the NANO gate 33 are eliminated and the circuit is configured to count repeatedly, it can be easily used as an oscillation circuit with a long period of time, rather than as a timer function.

As is clear from the above description, the long-time timer device according to the present invention can: (1) Preset a plurality of timer times and easily select a desired timer time;
By adopting a configuration that can minimize variations in timer time due to variations in resistance values of a plurality of variable resistors used for presetting, it is possible to improve characteristics and simplify adjustments in the manufacturing process.

■ The variable range of the timer time is sufficiently wide, and the setting scale of the variable resistor can be selected relatively freely, improving versatility and operability. It can exhibit excellent effects in terms of accuracy, cost, and usage, and is extremely useful industrially.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is an electric circuit diagram of a timer device according to an embodiment of the present invention, FIGS. FIG. 5 is a characteristic diagram of the same device, FIGS. 6 to 8 are electric circuit diagrams showing other embodiments of the voltage setting circuit portion of the present invention, and FIG. 9 is a characteristic diagram of the voltage setting circuit of FIG. Fig. 10 is an electric circuit diagram showing another embodiment of the timer device of the present invention, Figs. 11 and 12 are characteristic diagrams of the timer device of Fig. 10, and Fig. 13 is an electric circuit diagram showing another embodiment of the timer device of the present invention. It is an applied electric circuit diagram. A: Charge/discharge circuit, B: Voltage setting circuit,
C...Voltage comparison circuit, D...Latch circuit, E...Counter, F...Drive circuit, 1...
DC power supply, 10a, 10b, 10c...variable resistor, 27...selection switch, 11, 12...
Comparator, 13...R-S flip. 18...Multi-stage flip flop, 19...
Count control circuit, 25...Relay, 32...Center tap, 40...Load. Figure 1 Figure 3 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13

Claims (1)

[Claims] 1. A DC power supply, an oscillation circuit that uses charging and discharging of a capacitor charged by the DC power supply, a counter that receives pulses output from the oscillation circuit, and a counter that receives pulses output from the counter. a drive circuit that drives a load such as a relay according to the output;
A plurality of fixed resistors are connected in series to the DC power supply, a low set voltage is output from one of the connection points, and two or more variable resistors are connected to at least one of the fixed resistors. A selection switch selects the respective output voltages from the sliding terminals of the respective variable resistors connected in parallel through two terminal terminals that give a total resistance value of each of the variable resistors, and which does not change the resistance value of the two terminal terminals. a first voltage comparison circuit that compares the high set voltage with the output voltage of the electric charge/discharge circuit; After the output of the second voltage comparison circuit that compares the output voltage of the discharge circuit and the first voltage comparison circuit is inverted, and until the output of the second voltage comparison circuit is inverted, the capacitor is What is claimed is: 1. A timer device comprising a latch circuit that discharges the battery and generates a pulse output. 2. After the counter emits a predetermined output, the oscillation circuit stops the oscillation operation, or the counter stops counting the input pulses from the oscillation operation. A timer device according to scope 1. 3. The timer device according to claim 1, wherein the voltage setting circuit is configured by connecting two or more variable resistors in parallel to one fixed resistor. 4. The timer device according to claim 1, wherein the voltage setting circuit is constructed by connecting variable resistors in parallel to separate fixed resistors. 5. The latch circuit includes an R-S flip-flop which has the output of the first voltage comparator circuit as a set input and the output of the second voltage comparator circuit as a reset input, and when the output of this R-S flip-flop is at a predetermined level, 2. The timer device according to claim 1, wherein the timer device comprises a switching element that discharges the charge of a capacitor in a charging/discharging circuit.