JPS6022368B2 - switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switch circuit, and particularly to control of a switch circuit that is effective when applied to an auto-clear circuit used in a digital control circuit composed of MISFETs (insulated gate field effect transistors). It is.

Hereinafter, a case where the present invention is applied to an auto clear circuit will be explained as an example. In this application, the output terminal of an FET refers to the source or drain or both. The digital control circuit is composed of a logic circuit including various storage circuits, and its operation is performed in synchronization with clock pulses. When the power is turned on, it is uncertain in which state the information in the memory circuit will be stabilized, so a clearing operation is required to set it to an initial value. The auto clear circuit attempts to do this automatically when the power is turned on.

The present invention can be incorporated into a MIS semiconductor integrated circuit, and
The present invention aims to provide a switch circuit with a simple circuit configuration.

The present invention extracts a plurality of clock pulses from the output from an oscillation circuit using a frequency dividing circuit, and divides them between two switches and one clock pulse.
It is used to drive a switch circuit consisting of two capacitors, devices that act as capacitors, or other devices or wiring.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram of an auto clear circuit devised by the inventor.

This circuit shows an example of an auto-clear circuit in a digital control circuit such as an electronic desktop calculator configured with a C-Skin S (complementary MIS) logic circuit.

In this circuit, MISFETs Q, Q2 are n-channel type transmission gate skin SFETs configured in a p-type well region formed on an n-type substrate.

The MISFETs Q, , Q2 are connected in series, and capacitors C, , C2 are provided on each output side, and a clock pulse?・，? Control with 2. These clock pulses ◇・, ◇2 have different phases from each other as shown in FIG.
Since it is T, it is a two-phase clock pulse formed so that the reference potential level) does not overlap. On the input side of the transmission gate MISFETQ, there is a current limiting p
It is assumed that a channel type skin SFET Q3 is provided, and a power supply voltage -Vss is applied through this.

A reference potential is applied to the p-type well region where the n-channel skin SFETs Q, , Q2 are configured.
The power supply voltage -Vss is applied as a bias voltage for electrically isolating the mold substrate from the mold substrate.

The above capacitances C, , C2 have a predetermined capacitance ratio, C2>
Set to select C.

This will be understood from the explanation of the operation described below. The output of the inverter circuit IN which inputs the accumulated voltage of the capacitor C2 is used as the auto clear signal cL.

The reason why an auto-clear signal can be generated by this circuit will be explained next with reference to the operating waveform diagram shown in FIG.

First, when the power is turned on, the power supply voltage -Vss falls. At this time, until the oscillation circuit starts the oscillation operation and the clock pulse ◇・, J2 of a predetermined level is formed, the transmission gate skin SFETs Q,, Q2 are connected to the n-channel type M
Because they are ISFETs, both are in the on state, so the capacitance C,...
C2 is charged. Therefore, in order to prevent this, the current limiting MISFET Q3 is provided. That is, this MISFETQ is connected to the power supply voltage -Vss
Even if the voltage falls, the gate voltage will not turn on unless it becomes higher than the value voltage, and this operation can be controlled by the time constant of the gate capacitance and the resistor R. This resistor R also functions to protect the gate of MISFETQ3. This is because the direct gate is connected to the terminal outside the monolithic integrated circuit. Therefore, clock pulse J
,, Until the transmission gate skin SFETQ,, Q2 performs normal on/off operation by means 2, the above MISFETQ
3 prevents the charging operation to the capacitors C, , C2, especially the output side capacitor C2.

Therefore, the output of the inverter circuit IN is the power supply voltage -V
Clear signal that falls with the fall of ss◇＾cL
form.

As a result, a predetermined memory circuit performs a clearing operation using this clear signal J^cL when its power supply voltage reaches a predetermined operating voltage. Next, clock pulse? ,,02,
Since the transmission gates MSFETs Q, , Q2 are turned on alternately, each time the charge stored in the capacitor C is transferred to the capacitor C2, the charging voltage level of the capacitor C2 gradually increases. A quantitative explanation of this is as follows.
First, in order to simplify the explanation, the explanation will be made while omitting the voltage loss due to the false threshold voltage of MISFETQ.

The amount of charge q, which is applied to the capacitor C by turning on the skin SFET Q, is determined by Equation '1'.

q,=C,Vss...'
If the accumulation level due to charge transfer due to turning on of 1' MISFET Q2 is Vx, then the following equation (2) can be obtained.

C, VSS = (C, 10C2) VX, ......■
Set the accumulation level by the next clock pulse to Vx
2, the following equation '3} is obtained. C, (VS8-
VX, ) + (C, ten C2) VX, = (C, ten C2) Vx
2......{31 or less In the same aircraft, if the accumulation level due to the nth clock pulses 01 and 02 is Vxn, the following relational expression (4) is obtained. C, (Vss
−Vxn−, )+(C, 10C2)Vxn−, 2(CI0C2)VXn ………[4, Therefore, when Vxn>VL (VL is the logic threshold voltage of the inverter circuit), the inverter circuit IN is reversed to cancel the clear operation.

By appropriately selecting the capacitance ratio (C, /C2) in consideration of the cycles of the clock pulses J, , J2, it is possible to obtain the clear signal J^cL that is generated for a predetermined period when the power is turned on.

In general, digital control circuits such as electronic desk calculators do not require a special clock generation circuit because they advance the operation sequence according to clock pulses. In addition, it can be configured with transmission gates MISFETQ, .about.Q3, capacitors C, .about.C2, and inverter circuit m, resulting in an extremely simple circuit.

In addition, in this circuit, by using n-channel type MISFETs formed in a p-type well region as the transmission gates MISFETs Q, , Q2, the pn junction D. ~D
3 can be used to construct a discharge path for the capacitors C, C2 when the power is turned off, which is useful for simplifying the circuit.

Note that when a clock pulse is generated almost simultaneously with power-on, and for example, the transmission gate MISFETQ,
, Q2, the transmission gate MISFET
When the active level of is on the power supply voltage side level, the current limiting MISFETQ is not necessary, but instead it is necessary to specially create a diode for discharging when the power is turned off.

Further, in the above example, a transmission gate MISFET is provided in which the charge of the capacitor C2 is controlled by a small clock pulse,
A circuit with three or more stages may be used, such as one in which charges are transferred over three stages.

FIG. 3 is a circuit diagram of a switch circuit according to an embodiment of the present invention. For electronic digital watches that do not use clock pulses and have a single oscillation circuit and a frequency dividing circuit,
As shown in FIG. 3, among the frequency dividing circuits for forming time pulses, a clock pulse similar to that described above is formed by gate circuits G, ○2 which receive predetermined frequency divided outputs F4 to F6 as inputs. Bye. In other words, the divided outputs F4Q to F6Q
The gate circuit ○2 is a NOR circuit whose input is a NOR circuit, the gate circuit ○ is a NAND circuit whose input is a frequency divider circuit F4Q, F5Q, F6Q, and an inverter circuit m for obtaining its inverted output. Gate output G shown in
,,○2 can be obtained.

In addition, in this embodiment, the storage level of the capacitor C2 is input to a latch circuit consisting of NOR circuits G3 and G4, and when the power is turned on, a high level of 1" as shown in FIG.
...Positive logic) Even with signal C, latch output Q is set to "1"
Set to .

Then, by inverting the latch circuits G3 and G4 with the key input signal after the signal C becomes low level ("0"), the clearing operation is attempted to be canceled. In the case of a clock, the clear operation resets various counters and sets them to a specific time, such as AMI childhood 00 minutes or
This is to make it appear as a 0:0 whisker.

The circuit that performs this clearing is the key switch input terminals MD and HM and the reference voltage terminal Vo. p-channel MISFETQ, which constitutes a pull-up resistor provided between
Q, inverter circuits m2 to IN5 for shaping the waveforms of these key input signals, latch circuits ○5 and G6 that receive these waveform shaping outputs as inputs, and a NOR circuit G7 that receives these latch outputs as inputs. , and an inverter circuit for forming the inverted signal. The latch circuits G5 and G6 are provided to prevent chattering and double pressing of the switch. As mentioned above, when one of the switches is turned on, a low level (1 Vss level) signal is input to the N through the latch circuits ○5 and G6.
When one of the inputs of the OR circuit G7 becomes "1", the output via the inverter circuit IN6 becomes "1", inverting the latch circuits G3 and G4 that hold the clear output, and canceling the clearing. Let's do it.

Note that these key input circuits are not only for canceling the clear operation, but rather for system control corresponding to each key switch, and are used as the clear cancel circuit. .

The present invention is not limited to the above-mentioned embodiments, and in addition to the C-skin S circuit, p-channel MISFET or n-channel MIS
It may also be incorporated into a monolithic integrated circuit comprised of single channel MISFETs.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an auto clear circuit devised by this inventor, Figure 2 is its operating waveform diagram, Figure 3 is a circuit diagram showing an embodiment of the invention, and Figure 4 is one of the circuit diagrams. FIG. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 (a) A frequency dividing circuit that receives the output of the oscillation circuit and outputs a plurality of clock pulses, and (b) first and second FEs that receive the above clock pulses on their respective gate electrodes.
(c) a first capacitor means having one terminal connected to a common connection point of one output terminal of the first and second FETs and the other terminal connected to a power supply terminal; d)
a second capacitor means having one terminal connected to the other output terminal of the first or second FET and the other terminal connected to the power supply terminal;
ET is a switch circuit characterized in that it is alternately made conductive by the above-mentioned clock pulses.