JPS6022382B2 - bus controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control device in a data processing device having a serial circuit priority determination method.

There are various conventional bus usage priority determination methods, but the priorities are generally arranged in series from high-priority devices to low-priority devices via cables, printed circuit boards, etc. The rankings are determined in order from lowest to highest. At this time, the device with the lowest priority (referred to as the lowest priority device) must generate a bus use request signal and confirm that all higher-level devices are not generating bus use request signals. . That is, in response to a bus use request signal from the lowest priority device, the device with the highest priority (hereinafter referred to as the highest priority device)
A return bus use permission signal is sequentially transmitted to devices with lower priorities, and only when the device reaches the user's seat is the bus use permitted. In this method, the time until bus use is approved is delayed due to bus line delays and the like. This delay time is approximately determined by the transmission path from the user's seat to the highest priority device. In general, most of the lowest moat priority devices are processing units such as central processing units, and in execution, even if the priority is low, it is desirable that the time from bus usage request to bus usage permission, that is, bus access time, be quick.

However, as mentioned above, the drawback is that the bus access time for the lowest priority device is longer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bus control device that eliminates the above-mentioned drawbacks.

The bus control device of the present invention provides a data processing system in which a processing device, a main storage device, an input/output control device, etc. are connected to a common bus, and the priority order given to each device is In a bus control device that determines the priority order of common bus use, each of the devices constituting the high priority device group other than the device with the lowest priority among the devices is placed in the first order of priority. The device is connected in series via a bus permission signal line to the device having the highest priority of this device group via the first bus permission signal line, and is connected to the device having the lowest priority through the first bus permission signal line. It is connected via a second bus use permission signal line and a second bus use request signal line, and is connected to each device of the high priority device group via a first bus use request line common to each device. until a predetermined judgment time elapses after a bus use request prohibition synchronization signal is sent to the bus use request prohibition synchronization signal line when a bus use request signal is sent from one of the above-mentioned devices. The device with the highest priority among the devices that sent the bus use request signal is permitted to use the common bus, and the sending of the bus use permission signal to the device with the lowest priority is the second bus use. The configuration is such that direct support is provided via the permission signal line.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a follow-up using a serial priority determination scheme.

Reference numeral 10 indicates a central processing unit which is a processing unit.

Reference numerals 20, 30 and 40 indicate input/output controllers A, B and C connected to the common bus line. Reference numeral 50 indicates a main memory, and the priority of this common bus is that the main memory 50 has the highest priority, and sequentially from device 40 to device 3.
The priority level decreases from 0 to device 20 to device 10. Reference number 1 is a signal line through which a common bus use request signal is sent;
Reference numerals 2, 2', 2'' and 2... indicate signal lines to which use permission signals are sent, and reference numeral 3 indicates the actual bus use line.The central processing unit 10, that is, the lowest priority device is the highest priority device. It waits until bus use permission signals from groups 20, 30, 40 and 50 are transmitted via signal line 2''', and then sends a bus use request signal to signal line 1.This waiting time is , (delay time from central processing unit 10 to main storage device 50) x 20Q (delay in common circuit).In addition to lower priority devices having lower priority than higher priority devices, The access time for bus use is also long. This access time increases as the line length of the bus increases. FIG. 2 is a diagram showing an embodiment of the present invention.

Reference numeral 100 indicates a central processing unit, which is a processing unit;
Reference numerals 200 and 300 indicate input/output controllers.
Main memory 400 is the highest priority device. Reference numeral 500 is the bus usage control device of the present invention. Bus control device 500 receives bus use request signals from lower priority device 100 and bus use request signals from higher priority device groups 200 to 400 via signal lines 11 and 12, respectively. Reference numeral 14 is a signal line through which a bus use permission signal for the lowest priority device group 100' is sent, and reference numerals 13, 13' and 13'' are busses for the highest priority device group 200-400'. This is the signal line through which the usage permission signal is sent.Reference number 15 is the actual bus usage line.Reference number 16 is the signal line where the bus usage request is sent to the lowest priority device 1.
00 or any one of the high priority device groups 200 to 400, this signal line is used to send a signal that prohibits further bus use requests. Here, the difference from the conventional method is that the bus control device 500 has the lowest priority of 100.
This is the point where the highest priority device is located next, and the priority level decreases in order. 12 are each distinct.

For example, when a bus use request is generated from one of the high-priority device groups 200 to 300, the bus control device 500 generates a bus use prohibition synchronization signal on the signal line 6 in response to the request, and prohibit requests to use the bus.
At this time, it takes a certain amount of time D (judgment time) for this bus use request prohibition synchronization signal to reach each high priority device.
During this period, a bus use request may be issued from a higher priority device 200 to 300 other than the device that issued the bus use request. At this time, use of the bus is granted according to the priority order from among the devices that have issued bus use requests, and bus use permission signals are sent to signal lines 13 and 1.
3' and 13'' from the bus control device 500. In response, the bus use signal becomes true and cancels the bus use request prohibition synchronization signal.
When there is no bus use request from devices 0 to 400 and there is only a bus use request from the lowest priority device 100, the bus control device 500 generates a bus use request prohibition synchronization signal as described above.

At this time, since there is only one lowest priority device 100, the bus control device 500 sends a bus use permission signal to the lowest priority device 100 via the signal line 14, and I will not send anything for this.
However, if a bus use request is sent from the high-priority devices 200 to 400 during the judgment time D after sending the bus use prohibition synchronization signal, the priority order is determined during the judgment time ○, and the After a certain period of time, a bus use permission signal is sent via the signal line 14 or 13. In this way, the permission signal for the lowest priority device 100 can be directly received without going through any device on the bus, thereby reducing bus access time. Furthermore, the system is not affected by failures in relay circuits of high-priority devices. Figure 3a
〜This is a time relationship diagram of this embodiment, in which a shows a bus use request signal from the lowest priority device, b shows a bus use request signal from a group of high priority devices, and c shows a bus use request signal from a group of high priority devices. The bus use request prohibition synchronization signal, d in the same figure, the bus use permission signal sent to the signal line 14, the figure e, the bus use permission signal sent to the signal line 13, and the figure f, the bus use signal.

In addition, in the figure, the part indicated by the reference alphabet A is an example in which permission to use the lowest priority device 1001 was granted because the bus use request signal did not arrive via the signal line 12 within the judgment time ○. , the part indicated by the reference alphabetic character B is an example in which a bus use request signal arrives via the signal line 12 within the determination time D, so that a high priority device is granted permission to use the bus. FIG. 4 is a circuit diagram showing an example of the configuration of the bus control device 500. This device includes an inverter 501 that inverts and outputs signals from signal lines 15, 12, and 11, respectively.
502 and 503, and an inverter 5 at one input terminal.
AND gate 504 given the output of 02
, an AND gate 505 to which the output of the inverter 503 is given to one input terminal, and an AND gate 505 to which the output of the inverter 503 is given to one input terminal.
04 and the other input terminal is given the output of gate 505, the input terminal ○ is grounded, the clock terminal CP is given the output of gate 501, and the master set terminal is given the output of NOR gate 506. A delay type flip-flop 512 whose input terminal D is supplied with the output of the gate 502 and whose clock terminal CP is supplied with the output from the output terminal Q of the flip-flop 507;
A delay type flip-flop 514 is provided with the output of 03 and the output from the output terminal Q of the flip-flop 507 is given to the clock terminal CP, and a driver that increases the output from the output terminal Q of the flip-flop 507 and outputs it to the signal line 16. 508, a delay circuit 509 having first and second output terminals that delay and output the output from the output terminal Q of the flip-flop 507 by times D and (D1W), respectively; An inverter 510 that inverts and outputs the output of the second output terminal, and an AND circuit in which the output of the inverter 510 is given to one input terminal and the output from the first output terminal of the circuit 509 is given to the other input terminal. AND gate 51 which performs the logical product of the output from the output terminal Q of the flip-flop 512 and the output of the gate 511, and outputs the result to the signal line 13.
3, the output of gate 511 and flip-flop 512
The output from the output terminal Q of the flip-flop 514 is ANDed with the output from the output terminal Q of the flip-flop 514, and the result is sent to the signal line 14.
and an AND gate 515 that outputs to In flip-flop 507, when a pulse is applied to the master set terminal, its output terminals Q and Q are set to logic "1" and "0", respectively. As described above, the present invention has the advantage that it is possible to reduce the bus access time for bus use by the lowest priority device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional example, FIG. 2 is a diagram showing an embodiment of the present invention, FIGS. 3 a to f are time relationship diagrams for explaining the operation of this embodiment, and FIG. 4 is a bus FIG. 2 is a circuit diagram showing an example of a configuration of a control device. In the figure, 1, 11, 12... bus use request signal lines, 2, 2', 2'', 2''', 13, 13', 1
3r, 14... Bus use permission signal line, 3, 15
...Bus use signal line, 16...Bus use request prohibition synchronization signal line, 10-50, 100-500...
... Directly from the bag. powder 3 boxes 4 herons chrysanthemums z group

Claims (1)

[Claims] 1. Determining the priority order of use of the common bus for each device based on the priority order given to each device of a data processing system in which a processing device, a main storage device, an input/output control device, etc. are connected to a common bus. a bus control device located between a lowest priority device and a group of high priority devices, the high priority device group being connected in a manner such that a first bus use permission signal is connected to the bus control device; The devices in the high priority device group are connected via a second bus permission signal line and a second bus request signal line, and each device in the high priority device group receives a first bus use request common to each device. connected via wire,
When a first or second bus request signal sent from one of the devices via the first or second bus request line is detected, a bus request prohibition synchronization signal is sent to the bus. If the first bus use request signal arrives before a predetermined determination time elapses after sending the synchronization signal to the use request prohibition synchronization signal line, the first bus use request signal is sent to the use request prohibition synchronization signal line. Permitting use of the common bus from a device with a higher priority among the devices, and if the first bus use request signal does not arrive within the determination time, allowing the device with the lowest priority to use the bus. A bus control device characterized in that a signal is directly transmitted via a second bus use permission signal line.