JPS6022538B2 - Single band frequency division multiplex signal modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a single sideband frequency division multiplexing signal modulation device for converting between a single sideband frequency division multiplexed (hereinafter abbreviated as SSB-FDM) signal and a baseband signal by digital signal processing. Regarding.

Conventionally, an analog balance leveler and an analog belt pass filter have been used to convert a predetermined number of baseband signals into SSB-FDM signals, or conversely to demodulate a predetermined number of baseband signals from an SSB-FDM signal. This is done using On the other hand, in recent years, attempts have been made to realize modulation and demodulation of SSB-FDM signals using digital signal processing.

The following are typical known methods for implementing modulation and demodulation of SSB-FDM signals through this digital signal processing.

'11 Publication "ME" published in the United States in December 1971
ETRANS ACTIONS ON
C○MMUTICATION TECHNODOGY,
V○LCOM-19 No. 6” page 1050-1
Paper 'SystemsAnal$is' published on page 059
of a TDM-FDMTranslab/Dig
itaI A-TypeChannel already nk” (Reference 1).

{2) Publication “MEE” published in the United States in September 1974
TRANSACTIONS ○NC
OMMUNICATIONS, VOL. COM-
22, NO. 9, pages 1199 to 1205 of the paper “TDM-FDM
r；Digital Polyphase and FFT”
(Reference 2).

By modulating and demodulating SSB-FDM signals using such digital signal processing, it is possible to improve and make the transmission characteristics uniform, to make the equipment more compact and economical, and to simplify the manufacturing and maintenance of the equipment. SSB-FD
It is expected that mutual conversion between M signals and time division multiplexed (abbreviated as TDM) signals will become possible with high quality and economically. By the way, SS by digital signal processing
In the B-FDM signal modulation/demodulation method, the equipment scale and, in turn, the equipment price are almost determined by the number of multiplications required per unit time. Therefore, in order to realize the above expectations, it is necessary to It is required to obtain a modulation/demodulation method that requires essentially fewer multiplications.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single sideband frequency division multiplex signal modulation device using novel digital signal processing, which requires fewer multiplications per unit time than conventional systems.

Another object of the present invention is to provide a single sideband frequency division multiplexing signal modulation device that can improve transmission characteristics and is easy to downsize and simplify manufacturing and maintenance.

Another object of the present invention is to provide a single sideband frequency division multiplex signal modulation device that can convert between FDM and TDM signals with high quality and economically.

The single sideband frequency division multiplexing signal modulation device of the present invention modulates a predetermined number of baseband signals (hereinafter referred to as N channels) with a frequency that satisfies the Nyquist sampling theorem.
Basically, an N-channel real sample value series sampled at Hz (the unit Hz is omitted hereafter) is subjected to offset discrete Fourier processing and arithmetic operations using a digital filter while maintaining the sampling frequency of ``S''. The frequency N.N. of the SSB-FDM signal is obtained by obtaining a real sample value series, adding and synthesizing it with a delay of a predetermined integer multiple whose minimum unit is 1/(N.〆S). It is characterized by obtaining 9 sample value series.

Next, the principle and configuration of the single sideband frequency division multiplex signal modulation device of the present invention will be explained in detail with reference to the drawings.

In the following description, it is assumed that the sample value sequence generally means a sequence of digitized code words. This digitized codeword sequence is converted into an analog sample value sequence, that is, a PAM (Pulse Amplitude MeModule) by a digital-to-analog converter.
ation) signal and can be further passed through a filter to convert it into a continuous analog waveform. In addition, conversely, the continuous analog waveform is sampled and the PA
It can be converted into an M signal and further converted into a digitized sample value sequence by an analog-to-digital converter. Since the conversion between the analog waveform and the digitized sample value series can be easily performed in this way, the following explanation will be limited to the conversion process between the digitized sample value series. The generality of this is not to be disputed. FIG. 1 is a diagram showing an embodiment of a single sideband frequency division multiplexing signal modulation device according to the present invention, and FIG. 2 is a diagram showing frequency spectra of signals in various parts of FIG. 1.

In FIG. 1, input terminals 201, 202, . ...'2
0N has an N-channel frequency spectrum with a periodic structure that repeats at a frequency of S as shown in Figure 2A, obtained by sampling a baseband signal with a band width of less than 3/2 at a frequency of 3. A baseband signal sample value series is given, and an SSB-FDM signal sample value series having a frequency spectrum as shown in FIG. 2 is output from the output terminal 261.

For predetermined N/2 sequences among the N-channel baseband signal sample value sequences, the preprocessing circuit 200 performs a multiplication operation of (1)n, as shown in FIG. 2B. Inverts the spectrum (however,
n is the time index).

The output of the preprocessing circuit 200 is output from terminals 211, 212,...21.
An offset discrete Fourier processing circuit 210' is provided through N. In addition to this, the offset discrete Fourier processing circuit 210 has terminals 21N', 21N'-, ..., 212'.
, 21,' are also supplied with N inputs, but these N
The contents of the inputs may be all 0 inputs, but the terminals 21N', 21N'-, ..., 212', 21,' are connected to the terminals 21N, 21N-. . . , 212, 21, which can be obtained by commonly connecting terminals with corresponding numbers.
There may be multiple inputs.

Here, let Z be a lead time operator equal to one sample period of the SSB-FDM signal sample value series defined by Z=exp{j2takena/(N.naS)}, and the terminals 21, 2
12,..., 21N, 21N'..., 212',
21,′ is the Z transformation of the sample value series given to Xk(
ZN), and the Z transformation of the SSB-FDM signal sample value series appearing at the terminal 261 is assumed to be Y(Z).

The arithmetic operations performed in the embodiment of FIG. 1 are according to the following equation. '1] In the equation, Gi (-Z2N) is the Z transfer function of the real digital band filter, and A, (ZN
) is the output of the offset discrete Fourier processing circuit 210.

This offset discrete image processing circuit 210 performs the operation of formula {2-> on the input Xk (ZN) (k=0, 1, . . . , -1) to obtain the output Ai. (ZN)
This is a circuit that generates (i=0, 1,..., zu-1). Expression■
If the phase offset exp (i2 汀i/4N) is extracted from , the remainder becomes the discrete Fourier inverse transform equation of the state point.

Also, in equation '2), instead of (2k+1) -(2
k+1), the phase offset of ekp(-i2<i/4N) becomes the discrete Fourier transform equation of the point. In this case, the same results can be expected. In short, there is no essential difference whether it is a discrete Fourier transform or an inverse transform, and therefore, in the present invention, these are generally referred to as offset discrete Fourier processing. At every sampling period of 1/s, the number of inputs (actually N) of inputs Xk (ZN
) is given, the offset discrete Fourier processing circuit 2
10, the calculation of equation (2) is performed to generate outputs A, (ZN) for each 1/NaS.

The output Ai(Z
The real part Re{A, (ZN)} of N) is then real digital filter filter (hereinafter referred to as RDBPF) 22M
=0, 1, ..., S-1).

This RDBPF 22M is a filter circuit that causes only a phase shift without changing the amplitude, such that the amplitude frequency characteristics are the same for all i, and only the phase frequency characteristics differ by an amount proportional to i.

Filter circuits having such characteristics will be collectively referred to as polyphase circuits hereinafter. According to Shikikawa, if a delay of Z-i is given to a signal passing through the RDBPF22 river having a Z transfer function Gi (-Z2N), and these delayed signals are added for all i, SSB-FDM is obtained. This shows that signal Y(Z) is obtained.

To perform this operation, delay circuits 23, 232,...,
23N, adders 24, 242, . . . , 24N, and a parallel-to-serial converter 250. Delay circuit 23.
,232,. ．． ．． , 23N give Z-N, that is, a delay of one sample in the sample value series of sampling frequency 〆S. The parallel-to-serial converter 250 time-division multiplexes N sample value sequences of sampling frequency 〆S and converts them to sampling frequency N. It is equivalent to the adder 24 to obtain one sample value sequence of 9... (i=0, 1,..., N-1
) is given a delay of Z-'.

RDBPF22N+. , 22N 12, ..., 222N
Then, the delay circuits 23, 232, .
, . . . are given a delay of Z-i with respect to -1).

Since the sampling time slots of the outputs of the RDBPFs 22, 10, and 22N1i+ overlap in the sample value series after giving a delay of Z-i to the output of the RDBPF 22, the adder 24M divides the outputs of both outputs. Peace is achieved.

The fact that the SSB-FDM signal is obtained by the calculations of equations {11 and (2) performed in the embodiment of FIG. 1 will now be explained with reference to FIG.

In FIG. 3, reference numeral 410 is the Z transfer function G of RDBPF 22.

The Z transfer function Gi (1 Z2N) of RDBPF22i10, with (1 Z state) as the reference (that is, Gi (1 Z state)/
G. (-Z2N) phase characteristics, reference number 420 is RDB
PF G, shows the phase characteristics (with Z〇 as the reference) of the delay circuit of Z-i that is equivalently entered after (-Z2N). When the phase characteristics of reference numerals 410 and 420 are combined, the total phase characteristic becomes a stepped characteristic as shown by reference numeral 4301.

This is (relative) from the polyphase circuit to the output terminal
This is the overall phase characteristic. The overall (relative) phase characteristic from the input of the offset discrete Fourier processing circuit 210 is shown in reference numeral 4.
It is obtained by further adding the phase shift according to equation '2) to the characteristic indicated by 30. Reference numeral 440 is the overall (relative) phase characteristic when k = 0 in formula ■, reference numeral 45 Kawama k
;1, Reference number 46 The above-mentioned total when k = 2 (
relative) phase characteristics.

When considering such phase characteristics, it is assumed for convenience that all operations after the offset discrete Fourier processing circuit 210 are complex operations, and only the real part of the operation result is finally taken.

Of course, in reality, the offset discrete Fourier processing circuit 2
It is clear that the calculation for the imaginary part, which is discarded at the end, does not have to be performed from the beginning, since the calculations for the 10 skin bee are performed independently for the real and imaginary parts. According to the overall phase characteristic in Figure 3, k=0, that is, input signal ×
.

For (ZN), Obijo (0 to "S/2), k = 1, that is, for input signal
2~NaS), k=2, i.e. input signal X2(ZN)
For , the (relative) phase becomes 0 regardless of i only in the obi castle ('S ~ 3 na S/2), and in other obi castles the (relative) phase is an integer information of 2 bamboo i/su. takes the value of
If the phase is an integer multiple of 2mi/su, “i=o,1,
..., the vector sum for all i's cancels out and becomes 0. On the other hand, if the phase is independent of i, the vectors are added in phase. As a result, the input signal ×
. (ZN) is Obijo (o~〆Sノ2), ×, (ZN) is Obijo (NaS/2~'s), X2 (ZN) is Obijo (Na3~3
It occurs only in Na8/2),..., and disappears in other castles. Also, (2k+1) in formula ■ is changed to -(2k+1
), it can be easily determined from FIG. 3 that the signal remains only in the belt castle that is uniquely determined by the value of k. As a result, in the embodiment shown in FIG. 1, for the input signal F(ZN), the input signal C in FIG.
For N), complex digital belt filters (abbreviated as CDBPF) as shown in Figure 2 D,...,G are used.
A transfer characteristic equal to that of is obtained.

Therefore, the input signal f(ZN), X2(ZN),...×
N-2 (ZN) is Fig. 2A, input signal X, (ZN),
3(ZN)..., ×N-, (ZN) is preprocessed so that it has the spectrum shown in Figure 2B, and the input signal XN(Z
N), XN+・(ZN),. ．． ．． ,X2N-・kuZN)
If 0 is input to , output terminal 2 in Figure 1
The output obtained from 61 will have a frequency spectrum as shown in FIG.

However, since the output that is actually required is only the real part of the complex number as described above, it has a frequency spectrum as shown in FIG. 2. After decoding the sample value sequence having the spectrum shown in FIG. “S.
/2~N. An SSB-FDM signal spectrum such as reference numeral J is obtained by passing it through an analog band filter of S.

Also, if necessary, o~N. It is also possible to extract signals in a band of S/2. Furthermore, if the direction of the spectrum is required to be reversed, the above-mentioned preprocessing can be performed on even channels in the opposite direction. In the above explanation, it was assumed that there is a fixed relationship between the number of multiplexed channels N and the multiplexed signal sampling frequency (N.
By assuming an appropriate number of dummy channels in the number N of multiplexed channels, the relationship between the actual multiplexing degree of the SSB-FDM signal and the sampling frequency can be freely changed.

As a concrete example, considering a 60-channel FDM supergroup,
This SSB-FDM signal exists in the Z band city today from 312 to 55.

Also, the band width S/2 of one channel is 4KH2.
In this case, assuming 12 dummy channels, N=7
2, and the band of the 72-channel SSB-FDM signal is 288-57 (including the 312-55 HZ of the above).
If the port is HZ, then the sampling frequency is N. 〆S=57
class HZ, and no spectral overlap occurs. As will be described later, ``Using the FFT operation requires fewer multiplication circuits, especially when N is a value of a power of 2.

In the above example, to set N to a power of 2, set N to 64, including 4 dummy channels, and set the sampling frequency to N. NaS=5, Matsuhichi 2 can be set. In this case, it is necessary for the superband castles 312 to 55 to shift the HZ frequency to, for example, 8 to 24 Z band castles in advance. Next, referring to FIG. 4, an example of the demodulation layer of the SSB-FDM signal obtained by the modulation layer of the present invention (as shown in FIG. 1) will be explained. Frequency N. of SSB-FDM signal. The sample value series Y(Z) of NaS is input to the input terminal 561
, first, in the serial/parallel converter 5501, the given temporally serial sample value sequence is converted into temporally parallel N sample value sequences.

This operation involves a substantial delay, but here, terminal 5
Assume that the delay from terminal 61 to terminal 54 is Z, the delay from terminal 561 to terminal 542 is Z-1, and the delay from terminal 561 to terminal 54N is Z-(N-1). In other words, it is assumed that the sample value inputted latest in time appears at the terminal 54, and the sample value inputted earliest in terms of time appears at the terminal 54N at the same time. Terminals 54, 542,・
..., 54N, each sample value series is RD
Delay circuits 53, 532, 532, which are input to the BPFs 52, 522, ..., 52N and provide a delay of Z-N.
...,53N via ROBPF52 River,,52N+
2..., 522N.

From the input terminal 561 to the RDBPF52i, (i=0,1
, 2, ..., State-1) is input to the delay circuit 5.
Including the delay of 3, 532, ..., 53N, Z-
becomes equal to i.

RDBPF 52M in which Y(Z) applied to the input terminal 561 is delayed by Z-1 (i=0, 1, 2,..., S-1)
The sample value series at the input point is expressed as YN-,-i(Z). The Z transfer function of the RDBPF 52M is set equal to the aforementioned Gi (one Z state). The output of the RDBPF 52 is then provided to an offset discrete Fourier processing circuit 510'.

If the output of RDBPF52 river is A', (Z), then Ai
(Z)=Gi(-Z2N),YN-day(Z)B}, and the offset discrete Fourier processing circuit 510 is Ai(Z)
It is defined that the output X'k(Z) is obtained from the following equation.

The outputs of the offset discrete Fourier processing circuit 510 are terminals 51, 512, . . . , 51N'51'N,
51'N,51'N-,...,51'.

The fact that the SSB-FDM signal can be demodulated in FIG. 4 can be explained by referring back to FIG. 3. As in the case of Fig. 1, the Z transfer function Gi(-Z2N)/G
The phase characteristics of o(-Z2N) are as indicated by reference numeral 410 in FIG.
Since the delay until the signal is input to 52 is Z-i, its phase characteristic is expressed by reference numeral 4201 in FIG.

Therefore, the overall phase characteristic of the delay of Z-1 and the RDBPF 52i+ is as shown by reference numeral 430' in FIG. 3 (however, the phase characteristic of the RDBPF 52 is used as a reference).

Furthermore, considering the phase shift caused by the offset discrete Fourier processing circuit 5101, the input terminal 561 to the terminal 5
1,, the overall phase characteristics up to terminal 512, terminal 513, . . . are indicated by reference numbers 440, 450, 46 in FIG.
It will be shown as 0...,. As is clear from equation {4}, X′k(Z) is given as a vector sum for all i, so if the phase is an integer multiple of 2<i>/(is), it does not matter what the amplitude value is. The vector sum becomes 0.

Therefore, even if an SSB-FDM signal covering the entire band is given, only the signal component of the band whose phase is 0 will be extracted. That is, the output X'o (Z) has only the signal within the band (o, na s/2) from the phase characteristic 440 shown in Figure 3, and the output X', (Z) has the phase shown in Figure 3. Characteristic 45
Only signals within the range from 0 to Obijo (NaS/2, NaS) will be extracted. This ultimately leads to the signal in FIG.
This is equivalent to passing the signal through the filters shown in Figures C, D, . . . G and taking the real part of the output.

As in the case of the modulator described above, (2k+1
) can of course be set to -(2k+1). If the output X'k (Z) is then sampled at the frequency n S and a sample value series of the frequency n S called X'k (ZN) is obtained, the spectrum will be as shown in Fig. 2 A or B.
become that way.

Sampling at frequency 〆S results in output X′k(Z)
This means that only one out of N samples is effectively used, so there is no need to perform arithmetic operations on unnecessary samples in the offset discrete Fourier processing circuit 510 and the RDBPF 521.

As a result, the output of the serial-to-parallel converter 550 can be made into a sample value series of frequency nS. Terminals 54, 542
,...,54N, the sample value series appearing at the frequency 〆S
Even if the sample value series is , it contains all the sample values of the SSB-FDM signal applied to the terminal 661 in just the right amount, so there is no loss of information due to this. Therefore, ``YN-day (Z), A'i (Z), X'k (Z
) are henceforth all YN-, -, (ZN), A′i(ZN),
Reexpressed as X′k(ZN) and delay circuits 53, 5
32 ,...,5 3N, RDBPF5 2,10,
, the offset discrete Fourier processing circuit 610 can all be considered to operate at the sampling frequency 〆S.

Of the outputs X′k(ZN), k2N are unnecessary, and half of the outputs For the sample value series that produces (11
) The original baseband signal can be restored by multiplying by n.

In this way, N-channel baseband signal sample value sequences are obtained from the terminals 501, 502, . . . , 50N. Next, the offset discrete Fourier processing circuits 210 and 510' will be described in more detail.

The arithmetic expression of the offset discrete Fourier processing circuit 210 in the embodiment of FIG. For Kiln input Xk(ZN)
= 0, and the output A, (ZN) of the aforementioned circuit 210 is the sum of N terms. Also, since the input Xk (ZN) is all real signals, A2N-, (ZN) = -A*(ZN)(*
is a conjugate complex number). Furthermore, what needs to be found is only the real part, and it is clear that Re{AN(ZN)} is 0, so in the end, instead of formula (2), i=0, 1,...,N
For −1, calculate the following formula '5} or formula '6',
For i>N, Re{A2N-i(ZN)}=-Re
It may be determined using the relationship {Ai(ZN)}. Also,
When N can be further decomposed into products of prime numbers, the fast Fourier transform (FFT) technique, which is well known as time decimation or frequency decimation, can be applied to equation (2) to reduce the number of multiplications.

Apart from the above method, the terminals 21N', 212
′, 21, ′, are connected to terminals 21N, ..., 212, 2, respectively.
It is also possible to perform the calculation of equation (2) using the circuit shown in FIG.

In FIG. 5, reference numerals 21, 212, . ..., 2
1N, 21,', 212',..., 21N', 210
and reference numbers Ao, A, . ..., A2N-, is the second
have the same meaning and content as their corresponding counterparts in the figures.

Reference numeral 610 is an N-point real input discrete Fourier (inverse) transform circuit that performs the following calculation, and for its N postprime outputs, reference numeral 62i+. In the phase offset circuit shown as (i=0,1,...,N-1), exp(i2takei
/small) is multiplied by

Since the offset discrete Fourier processing circuit 510 needs to obtain only the real output, the phase offset circuit 62M only needs to perform calculations related to the real output.

Phase offset circuit 62i10. The output of is Ai(
i = 0, 1, ..., N-1), and at the same time,
This is input to the output circuit 630'. In the output circuit 630,
From Ai to A2N-F-Ai, AN ten,, ANze. …
, A2N-, is created and output. Note that adder 2 in Figure i
4,,242,... If subtraction is performed using 24N, the output circuit 630 only needs to be connected so that A-i=Ai.

The N-point real input discrete Fourier (inverse) transform circuit 610 in FIG. 5 only needs to perform half the number of multiplications performed by a normal N-point complex input discrete Fourier (inverse) transform circuit.

The number of multiplications in real input FFT is compared to general complex input FFT.
There are already some known examples of methods that reduce the number of multiplications by half, so a detailed explanation will be omitted here.

One of these known examples is detailed in the following document, for example. 196 Group October 2010 self-published publication “Commun”
cations of ACM, Vol. 11, NO
．． 10”, pages 703-710 of the paper “A F
ast F0urier Transfer plate Ngorj
thm ゎr Real-Val crotch dSeries” (
Reference 3). Note that the fact that the circuit in FIG. 5 performs the offset discrete Fourier processing shown by equation [21] means that
- When k(ZN)=Xk(ZN), it is confirmed that equation (2} is equivalent to the following equation.

Next, it will be explained that the offset discrete Fourier processing circuit 510 in the single sideband frequency division multiplex signal demodulation device of FIG. 4 can also be realized by the configuration shown in FIG. 6.

In FIG. 6, reference numbers 510, 51, 512,...
, 51N and reference letters A'o, A', . ..., A'2N
-,,X'o,X',...,X'2N-, represent the same meaning and content as the corresponding ones in FIG.

For input A'i, for i = 0, 1, ..., N-1, N complex numbers {A'i (ZN) where Ai is a real number and A is an imaginary number.
+iA..., (ZN)}, the phase offset circuit 71
, ten, is added.

In the phase offset circuit 71i+, exp{j2mi/
State} is multiplied by B′i(ZN)={A′i(ZN)+
iA'zu (ZN)}exp (i2kei/small)
■ is calculated. Phase offset circuit 71i
The complex output B'i (ZN) of +, is then given to an N-point discrete Fourier (inverse) transform circuit 720, and is calculated.

The calculation in the offset discrete Fourier processing circuit 5101 is to obtain . However, since A′i (ZN) is a real signal, there is a relationship of X′2N・rk(ZN) and X′k(ZN). , after all, X'2k (ZN) or X'2k
10, (ZN) is sufficient, and it can be seen that the component 510 in FIG. 6 can be replaced with the component 510 in FIG. 4.

In Shikinetane, when N can be decomposed into a product of prime numbers, the N-point discrete Fourier (inverse) transform circuit 72 Kawama FFT shown in FIG.
It can be realized with a small number of multiplications using the calculation method.

Furthermore, since only the real part is required for the output of the N-point discrete Fourier (inverse) transform circuit 720, the number of multiplications can also be reduced by omitting all operations related only to the imaginary part output. Next, the PoIJ phase circuit will be explained in detail.

The polyphase circuit consists of RDBPF22, 222,
..., 22 states or 52,,522,...,52 states.

The Z transfer function of the RDBPF 22M is Gi(-Z2N), and the sampling frequency N. as shown in FIG. Na S
A real digital low-pass filter for Obijona S/4 operating in
Let G(Z) be the Z transfer function of the RDLPF (abbreviated as RDLPF), then G. It can be derived from (Z).

That is, standards for in-band transmission characteristics and out-of-band attenuation are given to an RDLPF having a Z transfer function G(Z), and G(Z) is set to satisfy these standards.
is designed, then from G(Z), Gi that satisfies the following equation
(Z2N) is obtained.

Equation (12) shows that the impulse response of Gi(Z2N) is
This means that after giving a delay of 1, the sum of all i's matches the impulse response of G(Z). In other words, "The impulse response of Gi (Z) is equal to the impulse response of {G (Z).Zi} sampled at each sample point, that is, at the frequency 〆S〉2. Therefore ~ G Even if the amplitude-frequency characteristic of (Z) is as shown in Figure 7A, the amplitude-frequency characteristic of Gi (Z2N) is as shown in Figure 7B. Also ~ Gi (Z2N)/G
. The phase frequency characteristic of (Z2N) is exp{i2
汀〆,ノ(N.〆S)}, and due to the periodicity due to sampling, the overall characteristic is shown in Figure TC. The Z transfer function Gi(-Z2N) of the RDBPF 22M in FIG. 1 is equal to the Z transfer function Gi(Z2N) defined by equation 02) in which all Z2Ns are replaced by -Zz.

Conversion from Gi(Z2N) to Gi(-Z2N) involves a frequency shift of nanoS no 4, so t Gi(-Z2
The amplitude frequency characteristics of N) are shown in Figure 7 D, Gi(-Z2N)/
The phase frequency characteristics of Go (one Z) are as shown in FIG. 7 and 8.

In fact, if G(Z) is designed to satisfy desired standards such as in-band ripple and out-of-band attenuation, then G(
When Z) consists only of acyclic parts, G(
To obtain Gi(Z2N) from Z), the filter coefficients of G(Z) may be thinned out so as to satisfy equation (12).

This operation is extremely simple. If RDLPFG(Z) also has a cyclic part and is given by the Z transfer function of (10 x 10 x 20…10 x Shu-1) (1
By applying )-1, it can be rearranged into the form of equation (12) as shown below.

The first term above is G.

(The part excluding Z-i after the second term with Z fence is Gi (Z2N
) (i=1, 2,..., zu-1). RDBPF
22i ten, or 52M Z transfer function Gi (one Z) (
i=0, 1,...9 2N-1) is obtained by converting the pupil of Z to -Z in the formula for Gi(Z2N) obtained in this way.

A circuit implementation method of such an RDBPF can be implemented using conventionally known techniques.

．． By the way, the Z transfer function Gi (-Z2N) of ~RDBPF22i+, or 52... is common for all i (i.e., as can be easily understood with reference to equation (14))
i) has a denominator.

In other words, if we express Gi(-Z2N) by dividing it into a numerator and a denominator, we get Gi(-Z2N) and Pi(-Z2N)/Q(-
Z2N).

It can be seen that Q(-Z2N) is common to all i, and it is the numerator part that determines the phase characteristics specific to the polyphase circuit. From this fact, it is also possible to separate the calculation of 1/Q (one Z fence) from the position of the RDBPF 22M in Figure 1 and the position of RDBPF 52 in Figure 4.

In other words, in Figure 1, if the tl-Q (-Z small) arithmetic circuit is moved after the adder 24M or before the offset discrete Fourier processing circuit, N operations can be performed instead of ~1 operations. I can do it. Further, referring to Fig. 1, even if 1-Q (1-Z) operations are performed after the complex multiplication circuits 62, only N operations are required. Although it is equivalent to performing the process after the adders 24 . . . , it may also be performed after the parallel-to-serial converter 258 . In the case of FIG. 4, 1 no Q (1 Z
If we perform the calculation of the fence), ``the required amount of calculation can be halved.

As described in detail above, the single sideband frequency division multiplexing signal modulator according to the present invention basically consists of an offset discrete Fourier processing circuit operating at a sampling frequency of It is characterized in that it can be realized by a general connection with a polyphase circuit consisting of a filter, and requires arithmetic operations to convert a baseband signal into a polyphase signal, as seen in the known examples shown in 1 and 2 above. I don't.

This eliminates the need for arithmetic operations for converting between baseband signals and multiline signals, and the input/output of the offset discrete Fourier processing circuit is only the actual signal, so overall the number of multiplications per unit time is reduced. I will live. In addition, the calculation operation only requires two steps: offset discrete Fourier processing and polyphase, making it easier to downsize the device and simplify manufacturing and maintenance.Furthermore, the in-band transmission characteristics are determined only by the RDBPF characteristics of the polyphase circuit. Therefore, it has the advantage that it is easy to improve transmission characteristics.

The present invention also provides a baseband signal sample value series and an SS
Since it allows conversion between B-FDM signal sample value sequences, it can be applied very directly to the purpose of conversion between TDM and FDM signals.

In the above explanation, it was assumed that the input and output sample value series of the offset discrete Fourier processing circuit and the polyphase circuit exist in parallel, but a small number of basic FFT calculation elements, complex calculation circuits, RDBPF, etc. are time-divided. It goes without saying that the functions shown in FIG. 1 or 4 can be equivalently realized by using multiple devices.

In fact, in Fig. 1, when N-channel baseband signals are input serially in time, the preprocessing circuit, offset discrete Fourier processing circuit, RDBPF, adder, etc. can be operated in series, and the Series converter 2
50 becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a single sideband frequency division multiplex signal modulation device according to the present invention, and FIGS. 2 and 3 are for explaining the operation of the single sideband frequency division multiplex signal modulation device according to the present invention. FIG. 4 shows an example of a device for demodulating the SSB-FDM signal obtained by the modulation device shown in FIG. 1 of the present invention, and FIG. FIG. 6 is a diagram showing an example of the offset discrete Fourier processing circuit of FIG. 4, and FIG. 7 is a diagram for explaining a polyphase circuit used in the present invention. 1 and 4, reference numerals 200 are preprocessing circuits, reference numerals 210 and 510 are offset discrete Fourier processing circuits ``reference numerals 22,, 222,..., 222
N and 52, 522,..., 52 real digital bandpass filters forming a polyphase circuit, reference numeral 23
,,232,...,23N and 53.,532,...,
53N is a delay circuit, reference number 24, 242,...
24N is an adder, reference numeral 25 is a parallel-to-serial converter, reference numerals 201, 202, ..., 20M are input terminals for baseband signal sample value series, reference numeral 261' is SSB-
Output terminal for FDM signal sample value series, reference number 561
Reference numeral 550 is a serial/parallel converter, reference numeral 50 is a downstream processing circuit, and reference numerals 501, 502,..., 50N are output terminals for a baseband signal sample value series. show. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 6

Claims (1)

[Claims] 1. An offset discrete Fourier processing circuit that receives as input a real sample value series of a sampling frequency f_S of an N-channel baseband signal including an arbitrary number of dummy channels, and outputs a 2N real sample value series of a sampling frequency f_S. , 2N outputs of the offset discrete Fourier processing circuit are supplied as inputs.
A polyphase circuit consisting of real digital band filters, and means for outputting a series of 2N real sample values at a sampling frequency f_S from the polyphase circuit as a series of real sample values at a sampling frequency N·f_S. A single sideband frequency division multiplexing signal modulation device characterized in that: