JPS6022771B2 - Diagnosis method for data error detection and correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a diagnostic method for a data error detection and correction circuit that enables easy, accurate and quick diagnosis of read data and data error detection means.

A system for detecting and correcting errors in data using Hamming codes is well known, and a typical example thereof is shown in FIG.

In FIG. 1, 1 is a data processing device (CPU, channel, etc.), and 2 is a memory. When writing data to this memory 2, the data transferred from the data processing device 1 is stored in the write data register 4 through the data line 3. The write data stored in the write data register 4 is transferred to the memory 2 and the check bit generation circuit 6 through the data line 5. When the check bit generation circuit 6 receives the write data from the write data register 4 through the data line 6, it generates a check bit (so-called Hamming bit), and this check bit is transferred to the memory 2 through the data line 7 together with the write data. Ru. In this way, write data and check bits are written into the memory 2. On the other hand, when reading the data written in the memo IJ', the data line 8
The output data is transferred to the data error detection circuit 9 and the data correction circuit 1 through the data error detection circuit 9 and the data correction circuit 1.

Also, check bits are transferred from the memory 2 to the data error detection circuit 9 through the data line 11. Therefore, at the same time that the input data read from the memory 2 is transferred to the data error detection circuit 9 through the data line 8, the check bit is also transferred to the data error detection circuit 9 through the data line 11. Thereby, the data error detection circuit 9 detects whether there is an error in the input data or the check bit. If there is no error as a result of the detection by the data error detection circuit 9, the data correction circuit 10 does nothing, and the data read from the memory 2 is transferred to the data processing device 1 via the data line 12.

Further, when the data error detection circuit 9 detects that there is an error in the read data, the data error detection circuit 9 sends an error occurrence signal to the data correction circuit 10 through the data line 13.
At the same time, the error bit address signal is transferred from the data error detection circuit 9 to the data correction circuit 101 through the data line 14. As a result, data correction circuit 1
0 corrects the offer data based on these error occurrence signals and error bit addresses. Then, the corrected proposal data is sent to the data processing device 1 through the data line 12.
Transfer to. In this way, data errors are detected and corrected, and while this conventional method poses no problem in normal use, it When trying to diagnose yourself, use the following {1} to '4'
There are inconveniences as listed in section.

{1) Check bits are generated based on certain observations from the contents of data sent from a data processing device, and therefore it is difficult or impossible to arbitrarily set the contents of check bits. , the diagnosis of the memory area where the check bits are stored is bound to be incomplete.

(2) The data error detection circuit 9 may correct an uncorrectable error as a correctable error, and in that case, comparison with the original data (written data) becomes difficult.

When a '3' error occurs, it is difficult to determine whether it is due to a malfunction in the memory 2 or a malfunction in the data error detection circuit 9 or data correction circuit 10.

{4} If the problem is in the data error detection circuit 9 or the data correction circuit 10, it is difficult to determine whether the problem is in the check bit generation circuit 6 or the data error detection circuit 9.

This invention was made to eliminate the above-mentioned drawbacks of the conventional technology, and the four parts of the check bit generation circuit, data error detection circuit, data correction circuit, and memory can be tested separately from each other, making it easy to find faulty parts. It is an object of the present invention to provide a diagnostic method for data error detection and correction circuits that allows accurate diagnosis and easy comprehensive diagnosis of each circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a diagnostic method for a data error detection and correction circuit according to the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of one embodiment. In FIG. 2, the same parts as in FIG. 1 will be described with the same reference numerals. When transferring write data from the data processing device 1 (CPU, channel, etc.) to the memory 2, the write data is first stored in the write data register 4 from the data processing device 1 through the data line 3. The write data stored in the write data register 4 is transferred to the check bit generation circuit 6 and the memory 2 through the data line 5. Also,
Check bits are transferred from data processing device 1 through data line 15 to check bit register 6, where they are temporarily stored.

The check bits generated from check bit generation circuit 6 are transferred to check bit selection circuit 18 through data line 17. Further, the check bit stored in the transfer register 6 is transferred to the check bit selection circuit 12 through the data line 19. The check bit selection circuit 12 has the function of selecting either the check bit from the check bit generation circuit 6 or the check bit from the check bit register 16 and sending it to the memory 2.
On the other hand, when reading data from the memory 2, the output data from the memory 2 is transferred to a data error detection circuit 9 and a data correction circuit 10 through a data line 8. Further, the check bit is transferred from the memory 2 to the data error detection circuit 9 and the data processing device 1 through the data line 20. The data error detection circuit 9 is for checking whether there is an error in the input data and check bit read from the memory 2, and as a result of the check,
If there is an error, it is configured to transfer an error occurrence signal to the data correction circuit 10 through the data line 13, and is configured to send an error bit address to the data correction circuit 10 through the data line 14. There is. The output terminal of the data correction circuit 10 is the data line 1
2, and via this data line 12, if there is no error, the data read out from the memory 2 is transferred to the data processing device 1 as is, and if there is an error, it is transferred to the data processing device 1. Error-corrected proposal data is then transferred to this data processing device 1.

On the other hand, 21 indicates a diagnostic mode signal line, and this diagnostic mode signal line 21 connects the data processing device 1 and the data error detection circuit 9.
and the check bit selection circuit 12.
When the diagnostic mode signal line 21 is inactive, it is in a normal mode, and when it is active, it is in a diagnostic mode. Next, the operation of the diagnostic system for the data error detection and correction circuit of the present invention constructed as described above will be explained.

The write data from data processing device 1 is data line 3
The data is temporarily stored in the write data register 4 through the write data register 4. The write data stored in the write data register 4 is transferred to the check bit generation circuit 6 and the memory 2 through the data line 5. When the write data is transferred to the check bit generation circuit 6, a check bit is generated by the Hamming code method from the check bit generation circuit 6, and this check bit is transferred to the check bit selection circuit 18 through the data line 17. At the same time, a check bit is transferred from the data processing device 1 to the check bit register 16 through the data line 15, and this check bit is temporarily stored in the check bit register 16.

The check bits stored in check bit register 16 are transferred to check bit selection circuit 18 through data line 19. The check bit selection circuit 18 selects either the check bit from the check bit generation circuit 6 or the check bit transferred from the data processing device 1 through the check pit register 16. Assuming that the mode signal line 21 is inactive, that is, in the normal mode, the check bit selection circuit 18 selects the check bit from the check bit generation circuit 6. This check bit is transferred to memory 2. That is, along with the check bit,
Write data is written to memory 2. On the other hand, when the diagnostic mode signal line 21 is active, that is, in the diagnostic mode, the check bit selection circuit 18 selects the check bit transferred from the data processing device 1 via the check bit register 16, and selects this check bit. Transfer to memory 2.

Therefore, in the case of the diagnostic mode, the memory 2 will be written with write data and check bits from the data processing device 1. Next, a case will be described in which data written in the memory 2 as described above is read out.

First, the case where the diagnostic mode signal line 21 is in the normal mode will be described. In this case, the check bit generated and written in the check bit generation circuit 6 is transferred from the memory 2 to the data error detection circuit 9 through the data line 20. This check bit is also transferred to the data processing device 1. The data read out from the memory 2 is sent to the data error detection circuit 9 and the data correction circuit 101 through the data line 8. The data error detection circuit 9 detects whether or not there is an error in the read data and the check bit. If there is no error as a result of the detection, the data is passed through the data line 12 without any correction from the data correction circuit 10. The data is transferred to the data processing device 1.

When the data error detection circuit 9 detects an error, the data error detection circuit 9 transfers an error occurrence signal to the data correction circuit 10 through the data line 13, and also transmits the error bit address to the data correction circuit 10 through the data line 14. Forward. As a result, the data correction circuit 10
Then, predetermined corrections are made based on these error occurrence signals and the erroneous address, and the corrected logical output data is transferred to the data processing device 1 through the data line 12. On the other hand, when the diagnostic mode signal line 21 is in the diagnostic mode, the data error detection circuit 9 does not detect any errors. Therefore, the data correcting circuit 1 directly transfers the read data from the memory 2 to the data processing device 1 through the data line 12, regardless of whether there is an error in the read data. Since the present invention has a diagnostic function as described above, diagnosis as described in the following sections (i) to G is possible. (i) Writing to the memory 2 and making a proposal are performed in the diagnostic mode.

In this case, the data processing device 1 including the check bit
Since the data prepared in (that is, prepared by the program) is written as is into the memory 2, and the data read from the memory 2 is sent as is to the data processing device 1, only the memory 2 can be checked. Blood Writing is done in diagnostic mode, and discussion is done in normal mode. B) Prepare correct data and the corresponding correct check bits on the data processing device 1 side, and write them in diagnostic mode. This is read in normal mode and the data error detection circuit 9
Check whether it is determined that there is no error. {Low Prepare the corresponding incorrect data and check bits and write in diagnostic mode.

This is read in the normal mode and the data error detection circuit 9
It is checked whether the data correction circuit 10 detects an error and whether the data correction circuit 10 correctly corrects the data. blood
Writing is done in normal mode and in diagnostic mode.

In this case, it can be checked whether the check bit generation circuit 6 correctly generates check bits according to the data. OW Both writing and posting are performed in normal mode.

In this case, the data error detection circuit 9 and the data correction detection circuit 10 are all effective, allowing comprehensive diagnosis. In the above embodiment, the data error detection circuit 9 and the data correction circuit 10 using Hamming codes have been described, but the present invention is not limited thereto and can also be applied to a simple parity check circuit. It is something.

As described in detail above, according to the diagnostic method of the data error detection and correction circuit of the present invention, either the check bit generated by the check bit generation circuit or the check bit from the predetermined means from the write data is set to the diagnostic mode or normal mode. In addition to selecting the mode according to the mode, in this diagnostic mode, the presence or absence of any errors in the offer data is not detected, and in the normal mode, the detection means detects the presence or absence of errors in the check bit and offer data, so that there is no error. In this case, the read data is transferred as is to the predetermined means, and when an error is detected, the error is corrected by the correction means and then transferred to the predetermined means. , the four parts of memory can be tested separately from each other. Along with this, there is an advantage that the trouble spot can be easily, accurately and quickly discovered, and comprehensive diagnosis of each means can be easily performed.

[Brief explanation of the drawing]

Figure 1 shows a diagram of a conventional data error detection and correction method. FIG. 2 is a block diagram showing an embodiment of a diagnostic method for a data error detection and correction circuit according to the present invention. 1...
・Data processing device, 2...Memory, 4...Write data register, 6...Check bit generation circuit, 9...Data error detection circuit, 10...Data correction circuit, 16...Check bit register, 18...Check bit selection circuit, 2
1...Diagnostic mode signal line. Figure 1 Figure 2

Claims (1)

[Claims] 1. A data register that holds write data, a check bit register that holds check bits, a check bit generation circuit that receives the write data from the data register and generates the check bit, and a check bit from the check bit generation circuit or the check bit that generates the check bit. a selection circuit for selecting one of the check bits from the bit register; means for simultaneously writing the write data from the data register and the corresponding check bit from the selection circuit into memory; a data error detection circuit that detects data errors by check bits, a data correction circuit that corrects data read from the memory using correction information from the data error detection circuit, the selection circuit, and the data error. A method for diagnosing a data error detection and correction circuit, comprising means for diagnosing the check bit generation circuit, memory, data error detection circuit, and data correction circuit by setting the detection circuits to a diagnosis mode simultaneously or separately.