JPS6022787B2 - Command control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction control system, and more particularly to an instruction control system in a computer that is equipped with a vector register and executes operations on specified elements of the vector register.

As a control method for a computer that processes a large amount of vector data, a method is known in which a vector register is provided inside a processing device, and data in a storage device is once transferred to the vector register and then arithmetic processing is performed.

Figure 1 shows an example of the configuration of a vector register (VR).
This is a case where one needle is prepared.

FIG. 2 shows an example of an instruction format for handling such a vector register, which performs an operation between corresponding elements of vector registers R2 and R3, and stores the result in vector register RI. FIG. 3 shows a vector length register (VL), which specifies the number of elements to be operated on in the vector register, and is set, for example, by another instruction.

The operation of the computer will be described below using addition as an example of the operation. Vector length register (VL)
The value set in is assumed to be L (L≦M), and the element of the vector register is expressed by the subscript i.

In the case of the instruction in Figure 4, the sum of the elements of VR3 and VR4 is VR
2, and are executed sequentially from element 0 until the number of elements specified by the vector length register (VL), i.e., i=L-1. Expressed as a formula, it becomes as follows.

VR2.

← VR3. 10VR4oVR2. ← VR3,
10 VR4, VR22 ← VR32 10 VR42: : VR2i ← VR3i 10 VR4i ≦ VR2L-1 ← VR3L-1 10 VR4L-1 When these are illustrated, it becomes as shown in FIG.

Now, to explain the case where L=1, in this case,
There was only one operation, VR2. ←VR3. 10V
Execute R4o and exit. A problem in processing occurs when L=0, that is, when the contents of the vector length register (VL) are zero.

In the conventional system, when L=0 is detected, an interrupt is generated to proceed to another operation, or a state in which no operation data exists in the vector register is prevented from occurring from the beginning.

Therefore, it is necessary to determine whether L=0 or to determine in advance whether data to be operated on exists in the main memory or not, and condition determination processing and branch processing must be incorporated into the program. The problem with this method is that the program creation is complicated.

It is an object of the present invention to solve the above problems, facilitate program creation, and perform effective vector operations. , and a vector length register indicating the length of the element storing data in the vector register, and by specifying the vector register as an operand, data is sequentially extracted from each element of the specified vector register. , a computer that executes operations equal to the number of elements specified by the vector length register, includes a zero detection means for detecting that the contents of the vector length register are fog, and detects the drop before executing the operation. If the means detects that the contents of the vector length register are zero, the operation is not executed.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 6 is a block diagram of an embodiment according to the present invention, in which 1 is a processing unit, 2 is a main memory, 3 is a vector register (VR), 4 is a write register, 5 is a logical register, and 6 is a an arithmetic circuit, 7 an instruction control unit, 8 an instruction register,
9 is an instruction decode circuit, 10 is an AND circuit, 11 is an OR circuit, 12 is a no-operation (NOP) instruction signal line, 13 is a vector length register (VL), 13' is a data counter, 14 is a -1 circuit, 15 is a zero detection circuit, 1
6 is a timing signal line. When executing a vector operation, predetermined operand data is retrieved from the main memory 2 and stored in the vector register (VR) 3 in advance.

At the same time, the length of the data in the vector register (VR) 3 is stored in the vector length register (VL) 13.

At the beginning of an instruction, the contents of vector length register (VL) 13 are moved to data printer 13'. When a vector operation instruction is set in the instruction register 8 and decoded by the instruction decoding circuit 9, the data in the specified register of the vector register (VR) 3 is extracted and operated on by the operation circuit 6, and the operation result is stored in the vector again. The data is stored in the designated register of register (VR) 3. Each time this arithmetic operation is performed on one data element, one
The contents of the data counter 13' are incremented by 1 by the circuit 14. When the content of the data counter 13' becomes "0", the arithmetic operation ends and the next instruction starts. In the above operation, the value initially set in the data counter 13' is not "0", but is actually the value set in the vector register (VR) 3.
This is the operation when an operation is performed on the contents of
On the other hand, the contents of the vector length register (VL) 13 are “0”
That is, the operation when the initial value of the data counter 3' is "0" is as follows.

When a vector operation instruction is set in the instruction register 8 and decoded by the instruction decode circuit 9, when the zero detection circuit 15 detects that the content of the data counter 13' is "0", the timing signal line 16 is The output of the AND circuit 10 becomes "1" at a predetermined timing before the execution of the instruction that becomes "1".

As a result, the output of the OR circuit 11 becomes "1", a flip-flop (not shown) is set by the no-operation (NOP) instruction signal line 12, and the operation for the instruction is controlled not to be executed. When the instruction cycle ends, the next instruction is set in the instruction register 8 and executed.

Note that the configuration for no-operation (NOP) control including the flip-flop (not shown) is conventionally well known, and is not limited to the operation described above. No-operation instruction signal line 1
It is also possible to speed up the processing by terminating the instruction early with the instruction 2. Furthermore, by providing the usurp detection circuit in the vector length register (VL) 13, even faster instruction control becomes possible. In other words, it is also possible to control the instruction to proceed to the next instruction without inputting it to the instruction register 8. As described above, according to the present invention, when the contents of the vector length register (VL) are zero and there is no operation data in the vector register (VR), the operation instruction is not executed and the operation proceeds to the next operation. Therefore, there is no need to consider condition judgment processing, branch processing, etc. when creating a program.
This has the effect of making program creation easier.

Further, according to the present invention, the number of occurrences of interrupts during vector data calculation processing is reduced, so vector calculations can be performed efficiently.

[Brief explanation of the drawing]

Figure 1 is an example of the configuration of a vector register, Figure 2 is an example of an instruction format when using a vector register, Figure 3 is a vector length register, Figure 4 is an example of an instruction, and Figure 5 is an explanatory diagram of addition operation. , FIG. 6 is a block diagram of an embodiment according to the present invention. In FIG. 6, 1 is a processing unit, 2 is a main memory, 3 is a vector register, 6 is an arithmetic circuit, 7 is an instruction control unit, and 8
is an instruction register, 9 is an instruction decode circuit, and 12 is a no.
13 is a vector length register, 13' is a data counter, and 15 is a zero detection circuit. Figure 2 Figure 3 Chrysanthemum Figure 4 Little brother diagram

Claims (1)

[Claims] 1. Provides N vector registers each consisting of M elements and a vector length register indicating the length of the element storing data in the vector register, and by specifying the vector register as an operand, In a computer that sequentially extracts data from each element of the specified vector register and executes operations for the number of elements specified in the vector length register, a zero function that detects that the contents of the vector length register are zero. An instruction control method comprising: a detection means, and the operation is not executed if the zero detection means detects that the contents of the vector length register are zero prior to execution of the operation.