JPS6023379B2 - data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system having an error correction function for information read from a storage device.

In recent years, as the capacity of storage devices has increased, it has become essential to improve the reliability of storage devices.

The method of correcting 1-bit errors and detecting 2-bit errors by providing a Hamming test circuit and an error correction circuit for information read from a storage medium is widely used because it greatly contributes to improving reliability. . However, a new problem created by providing this test circuit is the time delay of the test circuit. For example, a Hamming test circuit that provides 8 redundant bits for 64 information bits requires five stages of exclusive OR gates, which has the major drawback of reducing the performance of the storage device. ing. In order to solve this drawback, a method has been proposed in which the information read from the storage medium is sent to the data processing device without waiting for the test results.

For example, the storage device checks the extracted information after sending it to the data processing device, and if a correctable error is detected, the storage device sends a signal specifying the correction location to the data processing device. There is a method in which errors in the read information are corrected within the data processing device by sending out the read information, or a method in which the read information is checked after sending out the read information in the same way, and if a correctable error is detected. , the storage device reports this fact to the data processing device, and the subsequent read information always passes through a checking circuit and an error correction circuit.

However, in the former method, after the data processing device starts using the read information sent from the storage device in the arithmetic unit, etc., the correction point designation signal is sent from the storage device, so the continuation of processing is temporarily stopped. This requires complicated control in which the process is interrupted, error correction is performed, and then the process is continued again. Furthermore, this method cannot be implemented in large-scale electronic computers that perform advance control of instructions because the control is complicated. In addition, the latter method has the disadvantage that, like the former method, when a correctable error occurs, the data processing device requires complicated control such as suspending and continuing the device, and furthermore, Since the inspection circuit and error correction circuit are always enabled after a possible error occurs, it also has the disadvantage that even if an error occurs only once, the subsequent performance of the storage device will be significantly degraded. are doing.

Therefore, an object of the present invention is to minimize the performance degradation caused by the read information inspection circuit, eliminate the complicated control of interrupting and continuing the device in the processing device, and furthermore, perform complicated control such as advance control. The object of the present invention is to provide a new error recovery method that can be easily applied to large-scale electronic computers.

In the present invention, the processing device has a retry function for erroneous processing, and the storage device has an error detection and correction function for the read information. Normally, the extracted information from the storage device is sent to the processing device as is, regardless of whether there is an error or not.
At the same time, the presence or absence of an error is detected. If an error is detected here, the previous device in the processing device is interrupted and a retry is instructed. In this retry, the storage device performs a reread. In this rereading, the presence or absence of an error in the read information is detected, and if there is no error, it is left as is, and if a correctable error is detected, it is corrected and then the read information is sent to the processing device. Also, if an uncorrectable error is detected here, the processing device is instructed to retry and re-reading the storage device is executed again. The present invention will be explained below with reference to an embodiment shown in FIG.

FIG. 1 shows a data processing system comprised of a central processing unit (hereinafter referred to as CPU) and a storage device (hereinafter referred to as MS), which is an example of a data processing apparatus. In FIG. 1, read information 3 from a storage unit 11 read in response to an access request 1 from the CPU is input to a test circuit 12 and an error correction circuit 13.

However, in normal times, the retry signal 2 from the retry control circuit 14 is "0", so the error correction circuit 13 is disabled, and the reading information 3 input to the circuit is transmitted to the inspection circuit 12. The read information 5 of the MS is sent directly without waiting for the determination of the syndrome bit 4 indicating the error status sent from the MS.
is sent to the CPU and processed. In addition, in parallel with this, the read information 3 is inspected by the inspection circuit 12, and if an error is detected, the CPU retry control circuit 14
An error signal 6 is sent to the CPU to instruct the CPU to retry the process.

During this retry, the CPU sets the retry signal 2 from the retry control circuit 14 to ``1'' and activates the access generation circuit 15 by the retry command signal 7 from the same circuit, so that the CPU can access the MS from the CPU. Send access request 1 to access reception circuit 16. At this time, when the access request 1 is sent to the MS, the read information 3 is retrieved from the storage section 11 and input to the inspection circuit 12 and yield correction circuit 13, as in normal times. However, at this time, since the retry signal 2 is set to '1', the error correction circuit 13 is enabled, and the read information 3 input to the circuit is corrected by the syndrome sent from the inspection circuit 12. Wait for bit 4 to be confirmed, and if bit 4 indicates a correctable error, correct the error, otherwise send it as is to the CPU as MS competition information 5 for processing. . At this time, if the error correction circuit 13 detects an uncorrectable error, the inspection circuit 12 sends an error signal 6 to the CPU retry control circuit 14 to instruct the CPU to try again.
After this, the same operation as above is repeated, and if an uncorrectable error is detected, the operation is repeated a predetermined number of times as necessary.
Retries are repeated. In this way, normally, the error correction circuit 13 is disabled, and the retry function of the data processing device is used to perform a retry based on the error signal from the inspection circuit 12.

By enabling the error correction circuit 13 only at this time, it is possible to minimize the performance degradation caused by the read information inspection circuit 12. In addition, if there is an error in the read information of the MS, instead of going through the process of interrupting the process, correcting the read information, and processing technology, the process is interrupted and the process is retried (requesting the storage device and clearing the read information). Since it uses a process that is extremely easy to control (including correction of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 11... storage section, 12...
...Inspection circuit, 13...Error correction circuit, 14...
. . . Retry control circuit, 15 . . . Access generation circuit, 16 . . . Access reception circuit. Aoi' figure

Claims (1)

[Claims] 1. In a data processing system that includes a processing device that has a retry function for erroneous processing and a storage device that receives access requests from the processing device and has an error detection and correction function for the read information, Normally, the read information is sent to the processing device regardless of whether there is an error in it, and the presence or absence of an error is detected.If an error is detected, the processing device interrupts the processing up to that point and causes the processing device to try again. means for causing the storage device to perform re-reading in a retry by the processing device; and detecting the presence or absence of an error in the read information of the storage device obtained by the re-reading, and if there is no error, then correcting it as is. A data processing system comprising means for correcting a possible error and sending the read information to a processing device, and for instructing the processing device to retry when an uncorrectable error is detected.