JPS6023429B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling memory access requests of a high-speed storage device connected to an arithmetic processing unit.

Conventionally, a storage device receives a memory access request signal, a proposal/write control signal, an address, and write data from an arithmetic processing unit, writes to a memory cell of a storage section, or issues a memory cell of a storage section, The operation of transferring the issue data to the arithmetic processing unit has been carried out. However, recently, storage devices have also been required to perform complex functions, ie, to execute instructions with maintenance and diagnosis in mind.

For example, if the storage device has 1-bit error correction and 2-bit error detection functions, error addresses and error syndromes, check bit opening instructions, input data register lowering instructions, write data register write and read instructions, addresses Providing a command to expose registers allows effective maintenance and diagnosis. In this case, the same command control line is used for the opening and writing of memory cells in the storage section, the writing of registers, and the closing command. In conventional storage devices, when the same instruction control lines are used, the storage device receives the instruction control signal, determines the instruction, and starts the operation, but with this, the access time of the storage device and the cycle time becomes slower. Therefore, in order to substantially speed up access time and cycle time, one of the operations is preceded before the discrimination operation, and if the discrimination of the operation is different from the preceding operation, the What is necessary is to stop the commanded action and perform the commanded action based on the discrimination.

The most suitable preceding operation is the operation of reading the contents from the storage means.

This is because, if we compare the proposal action and the writing action,
An issue operation does not change the stored contents; conversely, a write operation can change the stored contents.

Therefore, performing a read operation after a write operation has the risk of reading out the written content. Next, in the IC memory IJI, each cycle of the argument operation and the write operation is generally set such that the argument operation cycle is set in the first half and the write operation cycle is set in the second half. That is, even if the write operation is slightly delayed, the actual delay is small. moreover,
Generally, the access time of the storage means (main memory) is longer than the access time of the means (data register) that temporarily stores the data accessed in this storage means. Access is the first priority.

Taking the above points into consideration, the following storage device can be realized. An object of the present invention is to improve the access time and cycle time of a storage device and provide a faster storage device.

The present invention provides a storage device in which at least an issue command, a write command, and a command to a register are supplied from an arithmetic and control unit on the same command line, and a command determining means for determining any of the commands; If the determination result of the determination by the issuing means that starts the issuing operation to the storage unit in parallel with the determination and the issuing command is the issuing command, and if the determination result is the issuing command, the issuing means continues to perform the issuing operation; performs a write operation,
If the command is directed to the register, the memory device is configured to include means for performing an operation on the register.

The type of command for a memory access request from the arithmetic processing unit is sent to the storage device via an instruction control line, but in order to reduce the number of signal lines between the arithmetic processing unit and the storage device, there are usually three to four lines. is used to provide an encoded signal to the storage device. The storage device decodes this command control line to determine the command and initiate various command operations of the storage device. Decoding this command control line in storage
It takes time to determine which command to read.

Therefore, when a storage device receives a memory access request, it always starts the memory cell assignment operation, and in parallel, performs an instruction determination operation on the instruction control line, and when the instruction is determined, moves to each operation. There is no problem. In this case, in the case of other instructions, the read operation of the memory cell can be stopped midway so as not to destroy the contents of the memory cell, and the memory register operation can be started. Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, in one embodiment of the present invention, an address signal 3, a memory access request signal 4, an instruction control signal 5, and write data 6 are transferred from an arithmetic processing device 1 to a storage device 2; The read data 7 and error information 8 are transferred to the arithmetic processing unit 1.

In the memory device 2, the address signal 3 is held in the address register 9, and address data 15 is sent to the semiconductor memory cell matrix 22, which is a storage section. The memory access request signal 4 is received by a timing control circuit 10, and a timing signal 16 is sent to a storage section (semiconductor memory cell matrix) 22. The command control signal 5 is sent to the command discrimination circuit 11
, and sends a command signal 18 to each control circuit and an output/write instruction signal 17 to a storage section (memory cell matrix) 22.
send to

The write data register 12 receives and holds the write data 19, and sends the write data 19 to the storage unit 22. At the time of diagnosis, write data 47 is also sent to the output circuit 13, temporarily held, and then sent to the arithmetic processing unit 1. Storage section 22
The discussion data 20' read out from the discussion circuit 13
After being inspected and corrected, the data is transferred to the arithmetic processing unit 1 as extracted data 7. Readout circuit 1
The error signal 21 resulting from the check in step 3 is sent to the error control circuit 14, and the error information 8 is transferred to the arithmetic processing unit 1. The details of one embodiment of the instruction discrimination circuit 11 are shown in FIG.
The truth table is shown in Table 1.

Table 1 In Table 1 and FIG. 2, the instruction control signals INI and IN2 shown in Table 1 are applied to terminals 30 and 31, respectively
AND circuits 32, 33, 36, 37, 38
, 39, 40, 41 and NAND circuits 34, 35.
UT, 45 and 46 are output to terminals 17, 45 and 461, respectively.

A signal sent from the OUT terminal 17 is supplied to the storage section 22 as a write/write instruction signal 17.

This will be explained in more detail.

In the case of a logical issue instruction, the control signals INI and IN2 are “
0”, the output signal OUT from terminal 17 is “0”.
”, and this signal OUT is sent to the storage unit 2 as an argument instruction.
Sent to 2. In the case of a write command, the control signals . sent to.
Control signals INI and I in the case of a register import instruction
N2 becomes “1” and “0”, respectively, and control signals ml and IN2 become “1” in the case of a register write instruction.
Therefore, the output signal OUT from terminal 17 is “0”
This signal OUT is sent to the storage unit 22 as a read instruction.
sent to. Next, the detailed circuit and operation of the lecture circuit 13 will be explained with reference to FIGS. 1 and 3.

First, the operation of sending read data to the arithmetic processing unit 1 will be explained.

The proposal data 20 from the storage section 22 is set in the flip-flop 50'. At this time, if the instruction signal 46 from the instruction discrimination circuit 11 is "1", it is sent to the arithmetic processing unit. Second, when the data set in the flip-flop 50 is sent to the arithmetic processing unit 1, the read data 20' remains as the indicating signal 45 is "0", so the flip-flop 50
Without this setting, the data previously held in the flip-flop 501 is sent to the selection circuit 51, and the selection circuit 5
1, since the instruction signal 46 is "0", this data is sent to the arithmetic processing device 1.

Thirdly, when reading write data, the write data from the write data register 12 is supplied to the selection circuit 51 via the bus 47. The selection circuit 51 sends the write data to the arithmetic processing device 1 because the instruction signal 46 from the instruction determination circuit 11 is "0". Note that the flip-flop 60 is reset by the reset signal 52 in the initial state. As a result, the overall operation will be explained using FIG. 4.

Conventionally, the operation of a storage device has been shown by broken lines.

That is, when an instruction is determined after the address 15 is supplied, a timing (chip enable) signal 16 is supplied. Note that the write data V supply is performed together with the address supply. Further, the yielding operation is started after the command is determined. On the other hand, in the operation depicted by the solid line showing one embodiment in FIG. 4, the address signal 16 and timing signal 16 are sent as chip enable signals. The discussion write instruction signal 17 becomes a "0" level instruction 60 because the storage device 2 receives the memory access request signal 4 and first starts an argument operation. This is held until the instruction determination circuit determines it. When the instruction type is determined by the instruction discrimination circuit, if it is a write instruction, the read/write instruction signal 1 is output.
7 becomes the "1" level. A "0" level is given to read commands, register expose commands, and register write commands. In other words, in the operation of this embodiment, the reading operation of the storage unit precedes the operation regardless of whether or not a command is determined. It gets faster.

As described above, the present invention has the effect of greatly reducing the memory access time and memory cycle time of the storage device by starting the instruction determination operation and the issuing operation at the same time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage device that is an embodiment of the present invention, FIG. 2 is a partial detailed circuit diagram of the instruction discrimination circuit shown in FIG. 1, and FIG. The detailed circuit diagram, FIG. 4, is a time chart of various signals sent to the storage section 22 of FIG. 1. 1...Arithmetic processing unit, 2...Storage device, 3...
... Address signal, 4 ... Memory access request signal, 5 ... Command control signal, 6 ... Write data, 7 ... Proposal data, 8・・・・・・
...Error information, 9...Address register, 1
0... Timing control circuit, 11...
Instruction discrimination circuit, 12...Write data register, 1
3...readout circuit, 14...error control circuit, 15...address signal, 16...
Timing signal, 17...Proposal write instruction signal, 18...Command signal, 19...Write data, 20...Proposal data, 21...・
・Error signal, 22...Storage section, 30...
...Instruction control signal 1, 31...Instruction control signal 2
, 32, 33, 36, 37, 38, 39, 40, 41・
...AND circuit, 34, 35...NAND circuit, 45, 46...Instruction signal, 50...
・Flip-flop, 51...Selection circuit, 52...
...Reset signal. Mackerel 1, Mackerel 2, Kosan-Euro, Figure 4

Claims (1)

[Claims] 1 A storage device to which at least a read command, a write command, and a command to a register are supplied from an arithmetic and control unit on the same command line, comprising a command discriminating means for discriminating any one of the commands, and a command discriminating means for discriminating one of the commands, and a command discriminating means for discriminating the command in parallel with the command discriminating means. reading means for starting a read operation to the storage unit; if the determination result of the command determining means is the read command, the read operation is continued; if the determination result is the write command, the write operation is performed;
and means for performing an operation on the register if the command is directed to the register.