JPS6023437B2 - Storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to storage devices, and particularly to read-only memory devices.

MOSRO in which memory cells are arranged in m rows and columns
M is well known.

In this ROM, n memory cells are connected to one data line, and one of the cells is selected by a column address decoder. On the other hand, one of the m data lines is selected by the row address decoder and connected to the output circuit. Binary information is stored depending on whether the selected memory cell can discharge the charge on the data line. Information is provided by sensing the potential of the data line with a sense amplifier. In a conventional ROM, the potential of the data line can swing between the power supply voltage and the ground potential depending on the contents stored in the memory cell. As described above, since n memory cells are connected to the data line, the parasitic capacitance of the data line is relatively large. Charging and discharging this relatively large parasitic capacitance of the data line between the power supply voltage and the ground potential is disadvantageous in terms of high-speed resolution. SUMMARY OF THE INVENTION The present invention provides a sense amplifier for a ROM that can make the potential amplitude of a data line as small as possible and perform high-speed and stable logic. Hereinafter, the present invention will be explained in detail by one embodiment with reference to the drawings.

Although an n-channel E/D configuration in which a depletion type transistor is used as a load element will be explained as an example, the present invention is naturally applicable to a P-channel type and E/E configuration. FIG. 1 shows, as an example, two rows and two columns of memory cells and a sense amplifier.

11, 12, 21, 22 are memory cells, 51, 52 are column selection lines, 61, 62 are row selection lines, and 71, 72 are data lines.

101 is a power supply (for example, 15V), and 102 is a ground.

81 is the input of the sense amplifier, and the row selection transistor 31
, 32 to the data line. Reference numeral 82 is the output of the sense amplifier and serves as an input to an output buffer circuit (not shown).

41, 42, and 43 are transistors forming a sense amplifier.

Although 43 is shown as a depletion type transistor in the figure, it may of course be an enhancement type transistor or a linear resistance element.

The operation will be explained with reference to FIG. Either one of the column selection lines 51, 52 becomes "1", and the memory cells 11, 12 or 21, 22 are electrically connected to the data line. Then, one of the row selection lines 61, 62 becomes "1", one of the transistors 31, 32 becomes conductive, and one of the data lines 71, 72 is connected to the input 81 of the sense amplifier. At this time, the data line and sense-up input are at a high potential or a low potential depending on the state of the selected memory cell. One object of the present invention is to reduce the difference (amplitude) between high potential and low potential of the data line and sense amplifier input, thereby enabling high-speed operation. The threshold voltage of the transistor 41 is set to V, . , the threshold voltage of the transistor 42 is set to V,2, and the threshold voltage of the other enhancement type transistors (for example, 31, 32) is set to VTo.
Then, IVT.

lSIV,. The respective thresholds and value voltages are set so that the relationship l<IVT2l holds true.

As an example, VTo: 0.8V, Vn=3.0V, VT2
=3.5V. 91 does not have to be at the same potential as 101 as shown later, but for simplicity here, 91 is also 101.
Similarly, the power supply voltage V.

. shall be. Consider the case where 81 is now at a high potential and then changes to a low potential according to the state of the selected memory cell. When 81 is at high potential, the potential of 81 is Voo-V
The potential of T, , 82 is Voo.

When the potential of the transistor 81 starts to change to a low level, the transistor 41 first becomes conductive, and the potential of the transistor 82 also starts to change to a low level.

At this time, the transistor 42 is non-conductive and does not act as a load element for the data line 81 and the data line, so that the potential of the transistors 81 and 82 is quickly shifted to a low potential. The potential of 81 is Voo-VT
When the voltage drops to 2, the transistor 42 becomes conductive.

Transistor 42 has the effect of clamping the low potential of 81 so that it does not drop too much. Next, when 81 changes from a low potential to a high potential, first, the transistor 41
, 42 are conductive, and transistors 42 and 43 are connected to 81.
It acts as a load element for the data line, and the potential of 81 is V. o
-VT2, the transistor 42 becomes non-conductive and Vo
When the voltage becomes o-VT, the transistor 41 becomes non-conductive and the transistor 43 charges only the voltage 82 to Voo. As seen above, by controlling the voltages of the transistors 41 and 42, the voltage of the input 61 of the sense amplifier and the data line can be changed between the low potential clamped by Voo-Vn and the transistor 42.・While operating at low speed and high speed, the amplitude of the sense amplifier output 82 is kept at Vo~
By setting a low potential and a large potential, stable transmission to the output buffer can be achieved. As mentioned above, the parasitic capacitance of the data line and 81 is large, and it is extremely effective for high-speed operation to suppress the amplitude of charging and discharging of this capacitor. The main point of the present invention is that the gate voltage Vc of the transistors 41 and 42 is
It is located at the point where the T brush Vc-VT is reduced by 4, and 91 in Fig. 1 is set to a lower potential than 101, for example, VT, is changed to VT.
Even if VTo=VT, VT2 is set equal to o, exactly the same effect can be obtained.

From exactly the same meaning, the threshold of transistors 41 and 42,
Without changing the value voltage, as shown in Figure 2, the gate voltage of transistors 41 and 42 on the V side, VG Tsuru is set to VG4,>VG.
A similar effect can be obtained by establishing the following relationship.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram for explaining one embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining another embodiment. Figure 1 Figure 2

Claims (1)

[Claims] 1. A memory device including a plurality of memory cells arranged in rows and columns on a single semiconductor substrate and a sense amplifier coupled on these memory cells, wherein the sense amplifier has an input node, an output node, and the input node. a first transistor coupled between a node and an output node; a first load transistor coupled to the input node; and a second load transistor coupled to the output node; A memory device characterized in that the gate voltage of the first load transistor is set lower than the voltage.