JPS6023525B2 - Quadrature type detection circuit - Google Patents
Quadrature type detection circuitInfo
- Publication number
- JPS6023525B2 JPS6023525B2 JP14235777A JP14235777A JPS6023525B2 JP S6023525 B2 JPS6023525 B2 JP S6023525B2 JP 14235777 A JP14235777 A JP 14235777A JP 14235777 A JP14235777 A JP 14235777A JP S6023525 B2 JPS6023525 B2 JP S6023525B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- differential amplifier
- amplifier circuit
- phase
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Amplifiers (AREA)
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】
この発明はFM検波用に好適するクオドラチュア形検波
回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a quadrature detection circuit suitable for FM detection.
従来、FM受信機等に用いられるFM検波回路として第
1図に示すように構成されるクオドラチュア形検波回路
が知られていた。2. Description of the Related Art Conventionally, a quadrature detection circuit configured as shown in FIG. 1 has been known as an FM detection circuit used in FM receivers and the like.
すなわち、これはIF段等のFM(IF)信号源Vgか
らFM(IF)信号をトランジスタQ,,Q2でなる差
鰯増幅回路DA2を介してトランジスタQ3,Qでなる
下段差動増幅回路DA2とトランジスタQ〜Qでなる上
段差動増幅回路Dんとを有する二重平衡差鱗増幅回路D
BAとLC同調回路Tとでなるクオドラチュア形検波回
路Q−DETに供給するようにしたものである。In other words, the FM (IF) signal from the FM (IF) signal source Vg such as the IF stage is passed through the differential amplifier circuit DA2 consisting of transistors Q, , Q2, and then to the lower stage differential amplifier circuit DA2 consisting of transistors Q3 and Q. A double-balanced differential amplifier circuit D having an upper stage differential amplifier circuit D consisting of transistors Q to Q.
The signal is supplied to a quadrature type detection circuit Q-DET consisting of a BA and an LC tuning circuit T.
そして、かかるクオドラチュア形検波回路Q一DETは
FM入力信号に対し同調回路Tで90o移相波を作り、
FM波の周波数偏移による高低が90o移相波との間に
位相の進みと遅れとなって現われるので、この両波の積
成分つまり時間的に一致したときに流れる電流の増減で
検波出力を得るようにしたものであり、これは原FM入
力信号でスイッチングする下段差動堪鯛富回路Dんでも
つて、90o移相波が加えられる上段差動増幅回路Dへ
を制御することによりなされる。従って、この場合下段
差敷増幅回路Dんの出力端2と上段差動増幅回路Dんの
入力端3とに現われる信号はその位相差が正し〈く90
oに一致していなければならない。Then, the quadrature type detection circuit Q-DET generates a 90° phase shifted wave with the tuning circuit T for the FM input signal,
The height due to the frequency shift of the FM wave appears as a phase lead and lag between it and the 90° phase-shifted wave, so the detection output is determined by the product of these two waves, that is, the increase or decrease in the current that flows when they match in time. This is done by controlling the lower stage differential Taitomi circuit D, which switches with the original FM input signal, to the upper stage differential amplifier circuit D, to which the 90° phase shifted wave is applied. . Therefore, in this case, the phase difference between the signals appearing at the output terminal 2 of the lower differential amplifier circuit D and the input terminal 3 of the upper differential amplifier circuit D is correct.
o must match.
しかるに、下段差動増幅回路Dんの出力端2の信号は同
入力端1の信号よりずれるので、これを補償するために
上段差動増幅回路Dんの入力側にェミッタホロワトラン
ジスタQ,Q,oを追加して、該ェミツタホロワトラン
ジス夕Q9の入力機4の信号より前記上段差動増幅回路
○んの入力端3の信号をずらすようにしている。このよ
うなクオドラチュア形検波回路D−DBAでは、下段差
動増幅回路DA2のトランジスタQとQ4のベースに1
80o の位相差が生ずる。However, the signal at the output terminal 2 of the lower stage differential amplifier circuit D deviates from the signal at the input terminal 1, so in order to compensate for this, an emitter follower transistor Q, is installed on the input side of the upper stage differential amplifier circuit D. By adding Q and o, the signal at the input end 3 of the upper stage differential amplifier circuit ○ is shifted from the signal at the input device 4 of the emitter follower transistor Q9. In such a quadrature type detection circuit D-DBA, 1 is connected to the bases of transistors Q and Q4 of the lower stage differential amplifier circuit DA2.
A phase difference of 80° results.
即ち、び段を受ける差鰯増幅回路DA,のトランジスタ
Q,,Q2の負荷条件をSカーブの中点らで同じとする
ことが望ましいが、トランジスタQ2の負荷側コンデン
サC,によりアンバランスを生じていた。このようなア
ンバランスや二重平衡差動回路DBAの各トランジスタ
のストレィキヤパシタ等により、前記2−1間のずれと
4一3間のずれが一致しないために、結果として前記3
−2間の位相差を正し〈ム90oに一致させることがで
きなかった。このために、同調ずれや歪の悪化等が生じ
て検波特性を損なう欠点があった。そこで、この発明は
以上のような点に鑑みてなされたもので、簡易な位相補
正回路を付加することにより同調ずれ等をなくして検波
特性を良好にし得る極めて優れたクオドラチュア形検波
回路を提供することを目的としている。In other words, it is desirable that the load conditions of the transistors Q, , Q2 of the differential amplifier circuit DA, which receives the step, be the same from the midpoint of the S curve, but an unbalance may occur due to the capacitor C on the load side of the transistor Q2. was. Due to such unbalance and the stray capacitor of each transistor of the double-balanced differential circuit DBA, the deviation between 2-1 and the deviation between 4-3 do not match, resulting in
It was not possible to correct the phase difference between -2 and match the phase difference to 90o. For this reason, there has been a drawback that tuning shift and deterioration of distortion occur, impairing detection characteristics. Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide an extremely excellent quadrature type detection circuit that can eliminate tuning errors and improve detection characteristics by adding a simple phase correction circuit. The purpose is to
先ずこの発明の原理につき簡単に説明すると、上述の3
−2間が二9び よりも遅れた場合の歪技4・点はSカ
ーブの中点より周波数が高い方にずれると共にく900
よりも進んだ場合にはそれが反対に低い方にずれるよう
になる。First, to briefly explain the principle of this invention, the above-mentioned 3.
Distortion technique 4 when the interval between −2 and 29 is delayed from
If it goes further than that, it will shift to a lower position.
而して、通常3一2間は二900よりもずれるのでこの
位相ずれを補正するには上記二重平衡形差動増幅回路D
BAにおける下段差動増幅回路Dんでのスイッチングに
与える信号を、上記3一2の位相ずれに相当するだけず
らすような位相補正回路を付加してやればよいというこ
とに基いている。そして、かかる&相補正回路はクオド
ラチュア形検波回路のスイッチング部への信号を同調回
路(検波回路)への信号よりも位相をずらすための例え
ばコンデンサ等による位相補正回路を付加するだけで、
簡単にしてしかも確実に位相補正をなし得、以つてクオ
ドラチュア形検波回路の検波特性を良好にし得るように
した点にこの発明の特徴がある。以下図面を参照してこ
の発明の一実施例につき詳細に説明する。Since the phase difference between 3 and 2 is usually more than 2900 degrees, in order to correct this phase shift, the above-mentioned double balanced differential amplifier circuit D is used.
This is based on the fact that it is sufficient to add a phase correction circuit that shifts the signal applied to the switching in the lower stage differential amplifier circuit D in BA by an amount corresponding to the phase shift of 3-2. The &phase correction circuit can be constructed by simply adding a phase correction circuit such as a capacitor to shift the phase of the signal to the switching section of the quadrature type detection circuit from that of the signal to the tuning circuit (detection circuit).
The present invention is characterized in that phase correction can be performed simply and reliably, thereby improving the detection characteristics of the quadrature type detection circuit. An embodiment of the present invention will be described in detail below with reference to the drawings.
すなわち、IF段等のFM(IF)信号源VgからFM
(び)信号はトランジスタQ,.Q2でなる差動増幅回
路DA,を介して、トランジスタQ3,Qである下段差
動増幅回路DA2とトランジスタQ〜Qである上段差動
増幅回路DA3とを有する二重平衡差敷増幅回路DBA
と同調回路Tとでなるクオドラチュア形検波回路Q−D
ETに供給される。That is, from the FM (IF) signal source Vg such as the IF stage, the FM
(and) signals are transmitted by transistors Q, . A double-balanced differential amplifier circuit DBA has a lower stage differential amplifier circuit DA2, which is transistors Q3 and Q, and an upper stage differential amplifier circuit DA3, which is transistors Q to Q, via a differential amplifier circuit DA, which is composed of transistors Q2.
Quadrature type detection circuit Q-D consisting of and tuning circuit T
ET.
ここで、FM(IF)信号は二重平衡形菱鰯増幅回路D
SAの下段差敷増幅回路Dんに対しては直接的に供給さ
れ、上段差動増幅回路○んに対してはLC同調回路Tを
介して原FM(m)信号の900移相波とされた後、ェ
ミツタホロワトランジスタQ,Q,。を介して供給され
る。また、スイッチング部となる下段差動増幅回路DA
2の他方のトランジスタQのベースと、上段差動増幅回
路DA3の入力側に介在される他方のェミッタホロワト
ランジスタQ,oのベース間に位相補正回路PCを構成
する上記トランジスタQ2の負荷側のコンデンサC,と
同等のコンデンサCを付加する。而して以上の構成にお
いて、原FM入力信号でスイッチングする下段差動増幅
回路DA2でもつて、90o移相波が加えられる上段差
鰯増幅回路Dんを制御することにより、上述したような
FM検波作用がなされる。Here, the FM (IF) signal is a double-balanced rhombus amplifier circuit D.
It is directly supplied to the lower stage differential amplifier circuit D of the SA, and is converted into a 900 phase shifted wave of the original FM (m) signal through the LC tuning circuit T to the upper stage differential amplifier circuit ○. After that, the emitter follower transistors Q,Q,. Supplied via. In addition, the lower stage differential amplifier circuit DA, which serves as the switching section,
The load side of the transistor Q2 that constitutes a phase correction circuit PC between the base of the other transistor Q of No. 2 and the base of the other emitter follower transistor Q, o interposed on the input side of the upper stage differential amplifier circuit DA3. Add a capacitor C equivalent to the capacitor C. In the above configuration, even the lower stage differential amplifier circuit DA2 which switches with the original FM input signal can perform the above-mentioned FM detection by controlling the upper stage differential amplifier circuit D to which a 90o phase shifted wave is added. action is taken.
この場合、ェミッタホロワトランジスタQ,Q,oは上
段差動増幅回路DA3の入力端3と下段差動増幅回路D
A2の出力端2との位相差を正しくく900にするため
に下段側の出入力端2ーー間のずれだけ上段側の入出力
端4‐3間をずらせるものであるが、これだけでは実際
上両トランジスタのストレイキヤパシタやコンデンサC
,によるアンバランスによって2一1間と4一3間のず
れが一致せず、3−2間の位相差を二90o に一致さ
せることができない。しかるに、この発明は位相補正回
路PCとして付加したコンデンサCにより、クオドラチ
ュア形検波回路Q−DETのスイッチング部となる下段
差敷増幅回路Dんへの信号を同調回路(検波コィ.ル)
Tへの信号よりも上記3一2間の位相ずれに相当するだ
けずらすことにより、上記ストレイキャバシタやアンバ
ランス等による位相ずれに対して補償し得る。In this case, the emitter follower transistors Q, Q, o are connected to the input terminal 3 of the upper stage differential amplifier circuit DA3 and the lower stage differential amplifier circuit D.
In order to correctly set the phase difference with the output terminal 2 of A2 to 900, the input/output terminals 4-3 on the upper stage are shifted by the difference between the input/output terminals 2--on the lower stage, but this alone will not actually work. Stray capacitor and capacitor C of both upper transistors
, the deviations between 2-1 and 4-3 do not match, and the phase difference between 3-2 cannot be made to match 290 degrees. However, in this invention, a capacitor C added as a phase correction circuit PC is used to tune a signal to a lower differential amplifier circuit D, which is a switching section of a quadrature type detection circuit Q-DET, to a tuning circuit (detection coil).
By shifting the signal to T by an amount corresponding to the phase shift between 3 and 2, it is possible to compensate for the phase shift due to the stray capacitor, unbalance, etc.
即ち、結果的に3一2間の位相差を正しくく900にす
ることができるようになるこれは前述した原理で説明し
たようにFM検波出力として与えられるいわゆるSカー
ブの歪最小点が3−2間の位相差が二9びよりも遅れた
場合に周波数の高い方にずれ且つ二900よりも進んだ
場合に低い方にずれるようになるが、通常3一2間はく
900よりもずれるので、この位相ずれを補正するコン
デンサCからなる位相補正回路を付加してやればよいこ
とに基いているものである。なお、この発明は上記した
実施例のみに限定されることなく、この発明の要旨を逸
脱しない範囲で種々の変形を実施し得ることは言う迄も
ない。従って以上詳述したようにこの発明によれば髄易
な位相補正回路を付加することにより同調ずれ等をなく
して検波特性を良好にし得る極めて優れたクオドラチュ
ア形検波回路を提供することが可能となる。That is, as a result, the phase difference between 3 and 2 can be correctly set to 900. This is because, as explained in the above principle, the minimum distortion point of the so-called S curve given as the FM detection output is 3 - If the phase difference between 2 and 2 lags behind 290, it will shift toward the higher frequency side, and when it advances beyond 2900, it will shift toward the lower frequency, but normally it will deviate between 3 and 2 compared to 900. This is based on the fact that it is sufficient to add a phase correction circuit consisting of a capacitor C to correct this phase shift. It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made without departing from the spirit of the invention. Therefore, as detailed above, according to the present invention, it is possible to provide an extremely excellent quadrature type detection circuit that can eliminate tuning deviation and improve detection characteristics by adding an easy-to-use phase correction circuit. .
第1図は従来のクオドラチュア形検波回路を示す結線面
、第2図はこの発明に係るクオドラチュア形検波回路の
−実施例を示す結線図である。
Vg・・…・FM(IF)信号源、DA.・・・・・・
差動増幅回賂、DBA・・・・・・二重平衡差鰯増幅回
路、DA2・・・・・・下段差敷増幅回路、Dへ・・・
・・・上段差動増幅回路、Q一DET・・・・・・クオ
ドラチュア形検波回路、T・・・・・・同調回路、Q9
,Q,。・・・・・・ェミツタホロワトランジスタ、P
C・・・・・・位相補正回路。第1図
第2図FIG. 1 is a wiring diagram showing a conventional quadrature detection circuit, and FIG. 2 is a wiring diagram showing an embodiment of the quadrature detection circuit according to the present invention. Vg...FM (IF) signal source, DA.・・・・・・
Differential amplification circuit, DBA...Double balanced differential amplifier circuit, DA2...Lower stage differential amplifier circuit, to D...
...Upper stage differential amplifier circuit, Q-DET...Quadrature type detection circuit, T...Tuning circuit, Q9
,Q,. ...Emitter follower transistor, P
C... Phase correction circuit. Figure 1 Figure 2
Claims (1)
差動増幅回路と、該差動増幅回路から出力される被検波
用信号が与えられる下段差動部(スイツチング部)およ
び同調回路(検波コイル)を介して前記被検波用信号の
90°位相波が与えられる上段差動部とを有する二重平
衡差動回路とでなるクオドラチユア形検波回路において
、前記スイツチング部への信号を前記検波コイルの信号
よりも位相をずらすために一端が前記二重平衡差動回路
の上段差動部の入力端に接続され他端が前記スイツチン
グ部の入力端に接続されたコンデンサでなる位相補正回
路を付加したことを特徴とするクオドラチユア形検波回
路。1 A differential amplifier circuit consisting of transistors Q_1 and Q_2 receiving the IF stage, a lower stage differential section (switching section) to which the signal for the test wave outputted from the differential amplifier circuit is applied, and a tuning circuit (detection coil). and an upper stage differential section to which a 90° phase wave of the signal to be detected is applied. In order to shift the phase, a phase correction circuit made of a capacitor is added, one end of which is connected to the input end of the upper differential section of the double-balanced differential circuit, and the other end of which is connected to the input end of the switching section. A quadrature type detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14235777A JPS6023525B2 (en) | 1977-11-28 | 1977-11-28 | Quadrature type detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14235777A JPS6023525B2 (en) | 1977-11-28 | 1977-11-28 | Quadrature type detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5474663A JPS5474663A (en) | 1979-06-14 |
| JPS6023525B2 true JPS6023525B2 (en) | 1985-06-07 |
Family
ID=15313487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14235777A Expired JPS6023525B2 (en) | 1977-11-28 | 1977-11-28 | Quadrature type detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6023525B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02256754A (en) * | 1989-03-29 | 1990-10-17 | Natl House Ind Co Ltd | Fixing hardware for roof panel |
| JPH02129519U (en) * | 1989-03-29 | 1990-10-25 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4362999A (en) * | 1980-10-15 | 1982-12-07 | National Semiconductor Corporation | AM Stereo phase modulation decoder |
-
1977
- 1977-11-28 JP JP14235777A patent/JPS6023525B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02256754A (en) * | 1989-03-29 | 1990-10-17 | Natl House Ind Co Ltd | Fixing hardware for roof panel |
| JPH02129519U (en) * | 1989-03-29 | 1990-10-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5474663A (en) | 1979-06-14 |
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